karo-tx-uboot.git
6 years agocommon/board_r: manual relocation for cmd table
Andreas Bießmann [Mon, 19 Jan 2015 23:29:05 +0000 (00:29 +0100)]
common/board_r: manual relocation for cmd table

This is required for architectures still need manual relocation like avr32, mk68
and others.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
6 years agocommon: Move dram_init() declaration to common location
Michal Simek [Fri, 30 Jan 2015 09:51:46 +0000 (10:51 +0100)]
common: Move dram_init() declaration to common location

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoarc: build libgcc in U-Boot
Alexey Brodkin [Tue, 3 Feb 2015 10:58:20 +0000 (13:58 +0300)]
arc: build libgcc in U-Boot

This way we may have very limited set of functions implemented so we
save some space.

Also it allows us to build U-Boot for any ARC core with the same one
toolchain because we don't rely on pre-built libgcc.

For example:
 * we may use little-endian toolchain but build U-Boot for ether
endianess
 * we may use non-multilibbed uClibc toolchain but build U-Boot for
whatever ARC CPU flavour that current GCC supports

Private libgcc built from generic C implementation contributes only 144
bytes to .text section so we don't see significant degradation of size:
--->8---
$ arc-linux-size u-boot.libgcc-prebuilt
   text    data     bss     dec     hex filename
 222217   24912  214820  461949   70c7d u-boot.libgcc-prebuilt

$ arc-linux-size u-boot.libgcc-private
   text    data     bss     dec     hex filename
 222361   24912  214820  462093   70d0d u-boot.libgcc-private
--->8---

Also I don't notice visible performance degradation compared to
pre-built libgcc (where at least "*div*" functions are had-written in
assembly) on typical operations of downloading 10Mb uImage over TFTP and
bootm.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: move CPU flags selection to the main "config.mk"
Alexey Brodkin [Tue, 3 Feb 2015 10:58:19 +0000 (13:58 +0300)]
arc: move CPU flags selection to the main "config.mk"

As a preparation to ARCv2 port submission we're moving CPU slection
flags to a common location.
Also it will allow us to have more flexible CPU specification, not only
ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: move SYS_MONITOR_BASE setup in Konfig
Alexey Brodkin [Tue, 3 Feb 2015 10:58:18 +0000 (13:58 +0300)]
arc: move SYS_MONITOR_BASE setup in Konfig

Following SPARK ARC now has SYS_MONITOR_BASE setup via Kconfig.
This makes "include/configs/*.h" cleaner and more flexible.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.h
Alexey Brodkin [Tue, 3 Feb 2015 10:58:17 +0000 (13:58 +0300)]
arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.h

Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards
so there's no sense in separate per-board definitions.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: get rid of useless CONFIG_SKIP_LOWLEVEL_INIT
Alexey Brodkin [Tue, 3 Feb 2015 10:58:16 +0000 (13:58 +0300)]
arc: get rid of useless CONFIG_SKIP_LOWLEVEL_INIT

Currently there's nothing related to really low-level init on ARC so
CONFIG_SKIP_LOWLEVEL_INIT definition makes no sense.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.h
Alexey Brodkin [Tue, 3 Feb 2015 10:58:15 +0000 (13:58 +0300)]
arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.h

There're no other options for ARC except "generic board" so ther's no
point to define CONFIG_SYS_GENERIC_BOARD per board.

We now have it set fo all ARC boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: add selection of endianess in Kconfig
Alexey Brodkin [Tue, 3 Feb 2015 10:58:14 +0000 (13:58 +0300)]
arc: add selection of endianess in Kconfig

This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: select cache settings via menuconfig
Alexey Brodkin [Tue, 3 Feb 2015 10:58:13 +0000 (13:58 +0300)]
arc: select cache settings via menuconfig

This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: define and use PTAG AUX regs for MMUv3 only
Alexey Brodkin [Tue, 3 Feb 2015 10:58:12 +0000 (13:58 +0300)]
arc: define and use PTAG AUX regs for MMUv3 only

DC_PTAG and IC_PTAG registers only exist in MMUv3.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: add more flavours of ARC700 series CPU
Alexey Brodkin [Tue, 3 Feb 2015 10:58:11 +0000 (13:58 +0300)]
arc: add more flavours of ARC700 series CPU

Now we may select a particular version of ARC700:
 * ARC750D or
 * ARC770D

It allows more flexible (or more fine tuned) configuration of U-Boot.
Before that change we relied on minimal configuration but now we may
use specific features of each CPU.

Moreover allows us to escape manual selection of options that
exist in both CPUs but may have say different version like MMUv2 in
ARC750D vs MMUv3 in ARC770D.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: remove CPU hard-coded selection from board description in include/configs
Alexey Brodkin [Tue, 3 Feb 2015 10:58:10 +0000 (13:58 +0300)]
arc: remove CPU hard-coded selection from board description in include/configs

With switch to Kconfig we only need very board-specific descriptions in
include/configs.

CPU selection is performed with either defconfig or manually via
menuconfig.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
6 years agoarc: memcmp - fix zero-delay loop utilization
Igor Guryanov [Tue, 3 Feb 2015 10:58:09 +0000 (13:58 +0300)]
arc: memcmp - fix zero-delay loop utilization

It's prohibited to put branch instruction in the very end of zero-delay
loop. On execution this causes "Illegal instruction" exception.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
6 years agoarm, at91: taurus remove MACH_TYPE definitions in config file
Heiko Schocher [Wed, 21 Jan 2015 08:22:20 +0000 (09:22 +0100)]
arm, at91: taurus remove MACH_TYPE definitions in config file

remove MACH_TYPE definitions in config file, as they come from
the defconfig.

Signed-off-by: Heiko Schocher <hs@denx.de>
6 years agoarm, at91: add reset controller status register
Heiko Schocher [Wed, 21 Jan 2015 07:42:53 +0000 (08:42 +0100)]
arm, at91: add reset controller status register

add reset controller status register

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Bo Shen <voice.shen@atmel.com>
6 years agoarm, at91, taurus: enable WDT
Heiko Schocher [Wed, 21 Jan 2015 07:38:23 +0000 (08:38 +0100)]
arm, at91, taurus: enable WDT

enable WDT for the taurus board.

Signed-off-by: Heiko Schocher <hs@denx.de>
6 years agoarm, at91, wdt: make timeout configurable
Heiko Schocher [Wed, 21 Jan 2015 07:38:22 +0000 (08:38 +0100)]
arm, at91, wdt: make timeout configurable

make the HW WDT timeout configurable through the define
CONFIG_AT91_HW_WDT_TIMEOUT.

Signed-off-by: Heiko Schocher <hs@denx.de>
6 years agocommon/board_f: add at91 wdt
Heiko Schocher [Wed, 21 Jan 2015 07:38:21 +0000 (08:38 +0100)]
common/board_f: add at91 wdt

call hw_watchdog_init() also if CONFIG_AT91SAM9_WATCHDOG
is used.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agoarm, at91, wdt: do not disable WDT in SPL
Heiko Schocher [Wed, 21 Jan 2015 07:38:20 +0000 (08:38 +0100)]
arm, at91, wdt: do not disable WDT in SPL

if CONFIG_AT91SAM9_WATCHDOG is set, do not disable WDT in
SPL

Signed-off-by: Heiko Schocher <hs@denx.de>
6 years agoARM: at91: at91sam9x5: save environment to a FAT file in MMC card
Wu, Josh [Tue, 20 Jan 2015 02:33:33 +0000 (10:33 +0800)]
ARM: at91: at91sam9x5: save environment to a FAT file in MMC card

This patch will save U-Boot environment as a file: uboot.env, in FAT partition
instead of saving it in raw sector of MMC card.

This make us easier to manage the environment file.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: at91: sama5d3xek: save enviroment as a FAT file in MMC card
Wu, Josh [Tue, 20 Jan 2015 02:33:32 +0000 (10:33 +0800)]
ARM: at91: sama5d3xek: save enviroment as a FAT file in MMC card

This patch will save U-Boot environment as a file: uboot.env, in FAT partition
instead of in raw sector of MMC card.

This make us easier to manage the environment file.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: at91: sama5d3_xplained: save environment in a FAT file in MMC card
Wu, Josh [Tue, 20 Jan 2015 02:33:31 +0000 (10:33 +0800)]
ARM: at91: sama5d3_xplained: save environment in a FAT file in MMC card

This patch will save U-Boot environment as a file: uboot.env, in FAT partition
instead of saving it in raw sector of MMC card.

This make us easier to manage the environment file.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: at91: mmc portA support is only for at91sam9g20ek_2mmc board
Wu, Josh [Mon, 19 Jan 2015 07:25:56 +0000 (15:25 +0800)]
ARM: at91: mmc portA support is only for at91sam9g20ek_2mmc board

Current the MMC support will enable MCI port A, Which is only exist
for 2mmc board.
So by default we need to disable MMC (port A) support. And only enable
it for 2mmc board. Otherwise, dataflash won't work in at91sam9260ek board
as MMC has confliction with Dataflash in the CLK pin.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
6 years agomtd: atmel_nand: according to pmecc version to perform 0xff page correction
Wu, Josh [Fri, 16 Jan 2015 03:54:46 +0000 (11:54 +0800)]
mtd: atmel_nand: according to pmecc version to perform 0xff page correction

As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.

According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
6 years agoARM: atmel: cleanup: remove at91cap9 related code
Bo Shen [Fri, 16 Jan 2015 02:55:46 +0000 (10:55 +0800)]
ARM: atmel: cleanup: remove at91cap9 related code

As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
6 years agoARM: atmel: sama5d4_xplained: enable spl support
Bo Shen [Mon, 15 Dec 2014 05:24:39 +0000 (13:24 +0800)]
ARM: atmel: sama5d4_xplained: enable spl support

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: sama5d4ek: enable SPL support
Bo Shen [Mon, 15 Dec 2014 05:24:38 +0000 (13:24 +0800)]
ARM: atmel: sama5d4ek: enable SPL support

The sama5d4ek support boot up from NAND flash, SD/MMC card and
also the SPI flash.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: sama5d4: build related file when enable SPL
Bo Shen [Mon, 15 Dec 2014 05:24:37 +0000 (13:24 +0800)]
ARM: atmel: sama5d4: build related file when enable SPL

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: sama5d4: can access DDR in interleave mode
Bo Shen [Mon, 15 Dec 2014 05:24:36 +0000 (13:24 +0800)]
ARM: atmel: sama5d4: can access DDR in interleave mode

The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: sama5d4: add interrupt redirect function
Bo Shen [Mon, 15 Dec 2014 05:24:35 +0000 (13:24 +0800)]
ARM: atmel: sama5d4: add interrupt redirect function

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
6 years agoARM: atmel: sama5d4: add bus matrix init function
Bo Shen [Mon, 15 Dec 2014 05:24:34 +0000 (13:24 +0800)]
ARM: atmel: sama5d4: add bus matrix init function

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: sama5d4: add matrix1 base addr definition
Bo Shen [Mon, 15 Dec 2014 05:24:33 +0000 (13:24 +0800)]
ARM: atmel: sama5d4: add matrix1 base addr definition

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: spl: can not disable osc for sama5d4
Bo Shen [Mon, 15 Dec 2014 05:24:32 +0000 (13:24 +0800)]
ARM: atmel: spl: can not disable osc for sama5d4

The SAMA5D4 SoC on chip rc oscillator can not be disabled.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: spl: add saic to aic redirect function
Bo Shen [Mon, 15 Dec 2014 05:24:31 +0000 (13:24 +0800)]
ARM: atmel: spl: add saic to aic redirect function

Some SoC need to redirect the saic to aic to make the interrupt to
work, here add a weak function to be replaced by real function.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: spl: add weak bus matrix init function
Bo Shen [Mon, 15 Dec 2014 05:24:30 +0000 (13:24 +0800)]
ARM: atmel: spl: add weak bus matrix init function

Some SoC need to configure the bus matrix, add an weak function
to be replace by real function.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agoARM: atmel: sama5: add sfr register header file
Bo Shen [Mon, 15 Dec 2014 05:24:29 +0000 (13:24 +0800)]
ARM: atmel: sama5: add sfr register header file

The SFR (special function registers) can be shared bwteen
sama5d3 and sama5d4 soc.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adoptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
6 years agoARM: atmel: sama5: add bus matrix header file
Bo Shen [Mon, 15 Dec 2014 05:24:28 +0000 (13:24 +0800)]
ARM: atmel: sama5: add bus matrix header file

This matrix header file can be shared between sama5d3 and sama5d4 soc.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[whitespace adaptions for 80 char compliance]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
6 years agoARM: atmel: clock: make it possible to configure HMX32
Bo Shen [Mon, 15 Dec 2014 05:24:27 +0000 (13:24 +0800)]
ARM: atmel: clock: make it possible to configure HMX32

Signed-off-by: Bo Shen <voice.shen@atmel.com>
6 years agokwbimage: Make the Makefile pass in CONFIG_SYS_SPI_U_BOOT_OFFS
Tom Rini [Sat, 7 Feb 2015 12:03:00 +0000 (07:03 -0500)]
kwbimage: Make the Makefile pass in CONFIG_SYS_SPI_U_BOOT_OFFS

We can't use config.h directly as some platforms include headers that
aren't safe to use in normal Linux userland.

Signed-off-by: Tom Rini <trini@ti.com>
6 years agox86: Use tab instead of space to indent in PCIE_ECAM_BASE
Bin Meng [Mon, 2 Feb 2015 13:25:09 +0000 (21:25 +0800)]
x86: Use tab instead of space to indent in PCIE_ECAM_BASE

Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig
so it looks misaligned. Replace the space with tab to indent.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agobootstage: Fix typos in the comment
Bin Meng [Mon, 2 Feb 2015 13:25:08 +0000 (21:25 +0800)]
bootstage: Fix typos in the comment

There are two typos in the comment block in bootstage.h, fix them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Add Intel Galileo instructions in README.x86
Bin Meng [Wed, 4 Feb 2015 08:26:14 +0000 (16:26 +0800)]
x86: Add Intel Galileo instructions in README.x86

Add some instructions about building U-Boot for Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Add SD/MMC support to quark/galileo
Bin Meng [Wed, 4 Feb 2015 08:26:13 +0000 (16:26 +0800)]
x86: Add SD/MMC support to quark/galileo

Intel Galileo board has a microSD slot which is routed from Quark SoC
SDIO controller. Enable SD/MMC support so that we can use an SD card.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Add SPI support to quark/galileo
Bin Meng [Wed, 4 Feb 2015 08:26:12 +0000 (16:26 +0800)]
x86: Add SPI support to quark/galileo

The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: pci: Add pci ids for Quark SoC
Bin Meng [Wed, 4 Feb 2015 08:26:11 +0000 (16:26 +0800)]
x86: pci: Add pci ids for Quark SoC

Add pci ids for Intel Quark SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: galileo: Add GPIO support
Bin Meng [Wed, 4 Feb 2015 08:26:10 +0000 (16:26 +0800)]
x86: galileo: Add GPIO support

Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Initialize non-standard BARs
Bin Meng [Wed, 4 Feb 2015 08:26:09 +0000 (16:26 +0800)]
x86: quark: Initialize non-standard BARs

Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Call MRC in dram_init()
Bin Meng [Thu, 5 Feb 2015 15:42:28 +0000 (23:42 +0800)]
x86: quark: Call MRC in dram_init()

Now that we have added Quark MRC codes, call MRC in dram_init() so
that DRAM can be initialized on a Quark based board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agodt-bindings: Add Intel Quark MRC bindings
Bin Meng [Thu, 5 Feb 2015 15:42:27 +0000 (23:42 +0800)]
dt-bindings: Add Intel Quark MRC bindings

Add standard dt-bindings macros to be used by Intel Quark MRC node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agofdtdec: Add compatible id and string for Intel Quark MRC
Bin Meng [Thu, 5 Feb 2015 15:42:26 +0000 (23:42 +0800)]
fdtdec: Add compatible id and string for Intel Quark MRC

Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can
decode Intel Quark MRC node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Enable the Memory Reference Code build
Bin Meng [Thu, 5 Feb 2015 15:42:25 +0000 (23:42 +0800)]
x86: quark: Enable the Memory Reference Code build

Turn on the Memory Reference code build in the quark Makefile.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Add System Memory Controller support
Bin Meng [Thu, 5 Feb 2015 15:42:24 +0000 (23:42 +0800)]
x86: quark: Add System Memory Controller support

The codes are actually doing the memory initialization stuff.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Add utility codes needed for MRC
Bin Meng [Thu, 5 Feb 2015 15:42:23 +0000 (23:42 +0800)]
x86: quark: Add utility codes needed for MRC

Add various utility codes needed for Quark MRC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Add Memory Reference Code (MRC) main routines
Bin Meng [Thu, 5 Feb 2015 15:42:22 +0000 (23:42 +0800)]
x86: quark: Add Memory Reference Code (MRC) main routines

Add the main routines for Quark Memory Reference Code (MRC).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Bypass TSC calibration
Bin Meng [Thu, 5 Feb 2015 15:42:21 +0000 (23:42 +0800)]
x86: quark: Bypass TSC calibration

For some unknown reason, the TSC calibration via PIT does not work on
Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ
to 400 per Quark datasheet in the Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Allow overriding TSC_FREQ_IN_MHZ
Bin Meng [Thu, 5 Feb 2015 15:42:20 +0000 (23:42 +0800)]
x86: Allow overriding TSC_FREQ_IN_MHZ

We should allow the value of TSC_FREQ_IN_MHZ to be overridden by
the one in arch/cpu/<xxx>/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Enable the Intel quark/galileo build
Bin Meng [Mon, 2 Feb 2015 14:35:29 +0000 (22:35 +0800)]
x86: Enable the Intel quark/galileo build

Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Add basic Intel Galileo board support
Bin Meng [Mon, 2 Feb 2015 14:35:28 +0000 (22:35 +0800)]
x86: Add basic Intel Galileo board support

New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Add basic Intel Quark processor support
Bin Meng [Mon, 2 Feb 2015 14:35:27 +0000 (22:35 +0800)]
x86: Add basic Intel Quark processor support

Add minimum codes to support Intel Quark SoC. DRAM initialization
is not ready yet so a hardcoded gd->ram_size is assigned.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Add Cache-As-RAM initialization
Bin Meng [Mon, 2 Feb 2015 14:35:26 +0000 (22:35 +0800)]
x86: quark: Add Cache-As-RAM initialization

Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Define macros for pci configuration space access
Bin Meng [Mon, 2 Feb 2015 14:35:25 +0000 (22:35 +0800)]
x86: Define macros for pci configuration space access

Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to
arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these
macros can be used for pci configuration space access.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: quark: Add routines to access message bus registers
Bin Meng [Mon, 2 Feb 2015 14:35:24 +0000 (22:35 +0800)]
x86: quark: Add routines to access message bus registers

In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register (MDR).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Add header files for Intel Quark SoC defines
Bin Meng [Mon, 2 Feb 2015 14:35:23 +0000 (22:35 +0800)]
x86: Add header files for Intel Quark SoC defines

device.h for integrated pci devices' bdf on Quark SoC and quark.h for
various memory-mapped and i/o-mapped base addresses within SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Remove CONFIG_SATA_INTEL from x86-common.h
Bin Meng [Sat, 24 Jan 2015 09:17:08 +0000 (17:17 +0800)]
x86: Remove CONFIG_SATA_INTEL from x86-common.h

CONFIG_SATA_INTEL is not referenced anywhere, so remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
6 years agox86: Add support for Intel Minnowboard Max
Simon Glass [Wed, 28 Jan 2015 05:13:47 +0000 (22:13 -0700)]
x86: Add support for Intel Minnowboard Max

This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: Add some documentation on how to port U-Boot on x86
Simon Glass [Wed, 28 Jan 2015 05:13:46 +0000 (22:13 -0700)]
x86: Add some documentation on how to port U-Boot on x86

Some information has been gleaned on tools and procedures for porting
U-Boot to different x86 platforms. Add a few notes to start things off.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: Enable bootstage features
Simon Glass [Wed, 28 Jan 2015 05:13:45 +0000 (22:13 -0700)]
x86: Enable bootstage features

Allow measuring of boot time using bootstage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
6 years agoscsi: bootstage: Measure time taken to scan the bus
Simon Glass [Wed, 28 Jan 2015 05:13:44 +0000 (22:13 -0700)]
scsi: bootstage: Measure time taken to scan the bus

On some hardware this time can be significant. Add bootstage support for
measuring this. The result can be obtained using 'bootstage report' or
passed on to the Linux via the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: spi: Support ValleyView in ICH SPI driver
Simon Glass [Wed, 28 Jan 2015 05:13:43 +0000 (22:13 -0700)]
x86: spi: Support ValleyView in ICH SPI driver

The base address is found in a different way and the protection bit is also
in a different place. Otherwise it is very similar.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: Allow a UART to be set up before the FSP is ready
Simon Glass [Wed, 28 Jan 2015 05:13:42 +0000 (22:13 -0700)]
x86: Allow a UART to be set up before the FSP is ready

Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: Allow FSP Kconfig settings for all x86
Simon Glass [Wed, 28 Jan 2015 05:13:41 +0000 (22:13 -0700)]
x86: Allow FSP Kconfig settings for all x86

While queensbay is the first chip with these settings, others will want to
use them too. Make them common.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: Remove unnecessary casts and fix comment typos
Simon Glass [Wed, 28 Jan 2015 05:13:40 +0000 (22:13 -0700)]
x86: Remove unnecessary casts and fix comment typos

Tidy up the FSP support code a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 years agox86: mmc: Move common FSP functions into a common file
Simon Glass [Wed, 28 Jan 2015 05:13:39 +0000 (22:13 -0700)]
x86: mmc: Move common FSP functions into a common file

Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more flexibility.

This creates a generic PCI MMC device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
6 years agoarm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support
Stefan Roese [Mon, 19 Jan 2015 10:33:39 +0000 (11:33 +0100)]
arm: mvebu: maxbcm: Fix compilation warning and add Spansion SPI NOR support

This patch fixes the following compilation warning for maxbcm:

Building maxbcm board...
   text    data     bss     dec     hex filename
 160075    6596   38240  204911   3206f ./u-boot
board/maxbcm/maxbcm.c: In function 'reset_phy':
board/maxbcm/maxbcm.c:68:6: warning: unused variable 'reg' [-Wunused-variable]
  u16 reg;
      ^
board/maxbcm/maxbcm.c:66:6: warning: unused variable 'devadr' [-Wunused-variable]
  u16 devadr = CONFIG_PHY_BASE_ADDR;
      ^

Additionally support Spansion SPI NOR flash is added. With larger SPI device
support via the CONFIG_SPI_FLASH_BAR define.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoarm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr
Stefan Roese [Mon, 19 Jan 2015 10:33:40 +0000 (11:33 +0100)]
arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr

This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.

Support for some SoC's has been removed in this version. This is:

MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.

MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.

MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.

MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.

Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.

Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).

Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoarm: mvebu: Add Serdes PHY config code
Stefan Roese [Mon, 19 Jan 2015 10:33:41 +0000 (11:33 +0100)]
arm: mvebu: Add Serdes PHY config code

This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoarm: armada-xp: Add SPL support used to include the DDR training code
Stefan Roese [Mon, 19 Jan 2015 10:33:42 +0000 (11:33 +0100)]
arm: armada-xp: Add SPL support used to include the DDR training code

This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoscripts/Makefile.spl: Add MVEBU DDR code to SPL
Stefan Roese [Mon, 19 Jan 2015 10:33:43 +0000 (11:33 +0100)]
scripts/Makefile.spl: Add MVEBU DDR code to SPL

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agotools: kwbimage: Support u-boot.img padding to CONFIG_SYS_SPI_U_BOOT_OFFS
Stefan Roese [Mon, 19 Jan 2015 10:33:44 +0000 (11:33 +0100)]
tools: kwbimage: Support u-boot.img padding to CONFIG_SYS_SPI_U_BOOT_OFFS

This is used on the AXP boards, to pad u-boot.img to the desired offset in
SPI flash (only this boot target supported right now). This offset is
used by the SPL then to load u-boot.img into SDRAM and execute it there.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoMakefile: Add another kwb build target used on Marvell Armada-XP (AXP)
Stefan Roese [Mon, 19 Jan 2015 10:33:45 +0000 (11:33 +0100)]
Makefile: Add another kwb build target used on Marvell Armada-XP (AXP)

This build target now includes the SPL binary as the bin_hdr into the
kwb image. Its used on the AXP port with the mainlined DDR training code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoarm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot
Stefan Roese [Mon, 19 Jan 2015 10:33:46 +0000 (11:33 +0100)]
arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot

This patch adds SPL support to the db-mv784mp-gp eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoarm: maxbcm: Enable SPL to include DDR training code into U-Boot
Stefan Roese [Mon, 19 Jan 2015 10:33:47 +0000 (11:33 +0100)]
arm: maxbcm: Enable SPL to include DDR training code into U-Boot

This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoarm: mvebu: Placeholder bin_hdr file can now be removed
Stefan Roese [Mon, 19 Jan 2015 10:33:48 +0000 (11:33 +0100)]
arm: mvebu: Placeholder bin_hdr file can now be removed

With this patchset the Marvell bin_hdr (DDR training) code is intergrated
into mainline U-Boot. We can remove the placeholder file again, which was
only introduced to make U-Boot compile and link again.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoarm: armada-xp: Change built target to include the SPL binary as bin_hdr
Stefan Roese [Mon, 19 Jan 2015 10:33:49 +0000 (11:33 +0100)]
arm: armada-xp: Change built target to include the SPL binary as bin_hdr

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agokirkwood: sheevaplug: add FDT support
DrEagle [Wed, 17 Dec 2014 14:02:48 +0000 (15:02 +0100)]
kirkwood: sheevaplug: add FDT support

LIBFDT feature is required to support new kernels.

Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agokirkwood: sheevaplug: fix multiple defines
DrEagle [Wed, 17 Dec 2014 14:02:45 +0000 (15:02 +0100)]
kirkwood: sheevaplug: fix multiple defines

Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agokirkwood: sheevaplug: fix style
DrEagle [Wed, 17 Dec 2014 14:02:44 +0000 (15:02 +0100)]
kirkwood: sheevaplug: fix style

Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
6 years agoARM: UniPhier: leave the last element of boot_device_table empty
Masahiro Yamada [Thu, 5 Feb 2015 11:56:24 +0000 (20:56 +0900)]
ARM: UniPhier: leave the last element of boot_device_table empty

Checking if the pointer is NULL would be easier to know the tail
of the boot_device_table[] array.
For clarification, add the /* sentinel */ comment.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: refactor pinmon command
Masahiro Yamada [Thu, 5 Feb 2015 11:56:23 +0000 (20:56 +0900)]
ARM: UniPhier: refactor pinmon command

The return value of get_boot_mode_sel() is used as the index of
the boot_device_table[] array.  Its type should be "int" rather
than "u32".

Use only the iterator "i" for the loop in do_pinmon().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: enable I2C input pins for PH1-sLD8
Masahiro Yamada [Thu, 5 Feb 2015 05:43:00 +0000 (14:43 +0900)]
ARM: UniPhier: enable I2C input pins for PH1-sLD8

To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0)
and bit 11 (SCL1/SDA1) of IECTRL register must be set.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: do not compile unnecessary objects
Masahiro Yamada [Thu, 5 Feb 2015 05:42:58 +0000 (14:42 +0900)]
ARM: UniPhier: do not compile unnecessary objects

It is true that unused functions are removed from the ELF image
by the compiler's garbage collection but relying on it too much
does not look nice.
Currently, the build is taking more than it should.

Refactor the makefiles to compile only files that are really needed.
CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the
optimization.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: remove unused checkboard() functions
Masahiro Yamada [Thu, 5 Feb 2015 05:42:57 +0000 (14:42 +0900)]
ARM: UniPhier: remove unused checkboard() functions

Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), checkboard() is invoked only when
show_board_info() fails to get the model name from Device Tree.
It never happens because UniPhier SoCs now only work with
CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees
have the "model" property.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: revive support card info
Masahiro Yamada [Thu, 5 Feb 2015 05:42:56 +0000 (14:42 +0900)]
ARM: UniPhier: revive support card info

Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), the support card information has not been
displayed because check_support_card() is invoked only when
show_board_info() fails to get the model name from Device Tree.

This commit adds misc_init_f() function to call check_support_card()
from there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: move SPL init functions to spl_board_init()
Masahiro Yamada [Thu, 5 Feb 2015 05:42:55 +0000 (14:42 +0900)]
ARM: UniPhier: move SPL init functions to spl_board_init()

Now init functions called from board_postclk_init() and dram_init()
are only necessary for SPL.
Move them to spl_board_init() for clean-up.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: move pin_init() to board_early_init_f()
Masahiro Yamada [Thu, 5 Feb 2015 05:42:54 +0000 (14:42 +0900)]
ARM: UniPhier: move pin_init() to board_early_init_f()

Currently, I/O pin settings are not necessary for SPL.
The board_early_init_f() seems a suitable place to call pin_init().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: set I2C offset length of on-board EEPROM in DTS
Masahiro Yamada [Thu, 5 Feb 2015 05:30:26 +0000 (14:30 +0900)]
ARM: UniPhier: set I2C offset length of on-board EEPROM in DTS

The EEPROM chips on UniPhier reference daughter boards expect 2-byte
offset address.

Since 7132b9fd68a1 (dm: i2c: dts: Support an offset-len device tree
property), I2C sub-nodes can have "u-boot,i2c-offset-len" property.

It is convenient to set the default I2C offset address length in
Device Tree, so that we do not have to set it on the command line.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: move EEPROM device node into a separate DTS
Masahiro Yamada [Thu, 5 Feb 2015 05:30:25 +0000 (14:30 +0900)]
ARM: UniPhier: move EEPROM device node into a separate DTS

This EEPROM chip is installed on the expansion board commonly used
on UniPhier platform.  To avoid duplicated description, move the
EEPROM node to a separate file and include it from other device tree
sources.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoMAINTAINERS: claim maintainership of files with "uniphier" pattern
Masahiro Yamada [Thu, 5 Feb 2015 05:30:24 +0000 (14:30 +0900)]
MAINTAINERS: claim maintainership of files with "uniphier" pattern

The pattern "N:    uniphier" can cover
  - drivers/serial/serial_uniphier.c
  - drivers/i2c/i2c-uniphier.c
  - drivers/i2c/i2c-uniphier-f.c
  - arch/arm/dts/uniphier-*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: add a simple README file for UniPhier platform
Masahiro Yamada [Thu, 5 Feb 2015 05:30:23 +0000 (14:30 +0900)]
ARM: UniPhier: add a simple README file for UniPhier platform

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>