karo-tx-uboot.git
6 years agoatngwmkii: convert to generic board
Andreas Bießmann [Sun, 1 Mar 2015 21:01:13 +0000 (22:01 +0100)]
atngwmkii: convert to generic board

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
6 years agokconfig: remove unneeded U-Boot extension code
Masahiro Yamada [Fri, 27 Feb 2015 15:45:26 +0000 (00:45 +0900)]
kconfig: remove unneeded U-Boot extension code

This code was introduced to support the multiple .config
configuration in U-Boot.  We do not need it any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoserial: ns16550: Fix build error due to a typo
Axel Lin [Sat, 28 Feb 2015 07:55:36 +0000 (15:55 +0800)]
serial: ns16550: Fix build error due to a typo

Fix trivial typo.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Axel Lin <axel.lin@ingics.com>
6 years agoMAINTAINERS, git-mailrc: Update my email address
Tom Rini [Mon, 2 Mar 2015 13:37:50 +0000 (08:37 -0500)]
MAINTAINERS, git-mailrc: Update my email address

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoarmv7.h: Add <asm/io.h>
Tom Rini [Mon, 2 Mar 2015 13:24:45 +0000 (08:24 -0500)]
armv7.h: Add <asm/io.h>

With a389531 we now call readl() from this file so add <asm/io.h> so
that we have a prototype for the function.

Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agowarp: Select BOUNCE_BUFFER and CMD_EXT options
Fabio Estevam [Sat, 28 Feb 2015 18:16:43 +0000 (15:16 -0300)]
warp: Select BOUNCE_BUFFER and CMD_EXT options

Add EXT2/EXT4 and BOUNCE_BUFFER support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
6 years agowarp: Add USB Mass Storage support
Fabio Estevam [Sat, 28 Feb 2015 18:16:42 +0000 (15:16 -0300)]
warp: Add USB Mass Storage support

With UMS support we are able to flash the eMMC from U-boot, which is very
convenient.

Add UMS support to make the eMMC flashing process easier.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
6 years agomx6slevk: Provide a proper pad configuration for OTG1_ID pin
Fabio Estevam [Sat, 28 Feb 2015 17:25:46 +0000 (14:25 -0300)]
mx6slevk: Provide a proper pad configuration for OTG1_ID pin

Pass the same pad configuration as done in the kernel so that OTG1_ID pin can
properly work in device mode.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
6 years agopxa: colibri_pxa270: integrate latest validated register settings
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:19 +0000 (00:53 +0100)]
pxa: colibri_pxa270: integrate latest validated register settings

Integrate latest validated register settings from Toradex WinCE BSP
4.2 working accross all module versions from early V1.x, V1.2D, V2.2B
to V2.4A.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: colibri_pxa270: remove CONFIG_ENV_ADDR_REDUND
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:18 +0000 (00:53 +0100)]
pxa: colibri_pxa270: remove CONFIG_ENV_ADDR_REDUND

Usually not required for NOR flash.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: colibri_pxa270: fix wrong comment about voipac ethernet chip
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:17 +0000 (00:53 +0100)]
pxa: colibri_pxa270: fix wrong comment about voipac ethernet chip

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: colibri_pax270: fix CONFIG_BOOTCOMMAND
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:16 +0000 (00:53 +0100)]
pxa: colibri_pax270: fix CONFIG_BOOTCOMMAND

While 'mmc init' is no longer required the address to bootm the kernel
from NOR flash was wrong.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: colibri_pxa270: avoid overwriting factory configuration block
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:15 +0000 (00:53 +0100)]
pxa: colibri_pxa270: avoid overwriting factory configuration block

Specify a CONFIG_BOARD_SIZE_LIMIT of 256 KB in order to avoid
overwriting the factory configuration block located at offset 0x40000
in NOR flash.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: colibri_pxa270: disable loadb/s commands and long help
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:14 +0000 (00:53 +0100)]
pxa: colibri_pxa270: disable loadb/s commands and long help

To save more than 20 KB of precious space in NOR flash get rid of the
following configuration options:

CONFIG_CMD_LOADB
CONFIG_CMD_LOADS
CONFIG_SYS_LONGHELP

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: colibri_pxa270: migrate to generic board
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:13 +0000 (00:53 +0100)]
pxa: colibri_pxa270: migrate to generic board

Migrate Toradex Colibri PXA270 to use CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agopxa: balloon3/colibri_pxa270: fix environment optionally being nowhere
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:12 +0000 (00:53 +0100)]
pxa: balloon3/colibri_pxa270: fix environment optionally being nowhere

I couldn't quite figure out whether or not CONFIG_SYS_ENV_IS_NOWHERE
actually ever worked but nowadays this is called CONFIG_ENV_IS_NOWHERE.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: balloon3: fix comment about sdram banks
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:11 +0000 (00:53 +0100)]
pxa: balloon3: fix comment about sdram banks

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agopxa: balloon3: remove nowhere used symbol CONFIG_SYS_MEM_BUF_IMP
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:10 +0000 (00:53 +0100)]
pxa: balloon3: remove nowhere used symbol CONFIG_SYS_MEM_BUF_IMP

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agoremove nowhere used symbol CONFIG_SYS_CLKS_IN_HZ
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:09 +0000 (00:53 +0100)]
remove nowhere used symbol CONFIG_SYS_CLKS_IN_HZ

Basically finish what the following commit started a long time ago:

488f5d8790c451fc527fe5d2ef218f2a5e40ea17

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
For mx35pdk/woodburn:

Acked-by: Stefano Babic <sbabic@denx.de>
6 years agopxa: fix wrong comment about vpac270 being the arch number
Marcel Ziswiler [Sat, 28 Feb 2015 23:53:08 +0000 (00:53 +0100)]
pxa: fix wrong comment about vpac270 being the arch number

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
6 years agoimx6: Added DEK blob generator command
Raul Cardenas [Fri, 27 Feb 2015 17:22:06 +0000 (11:22 -0600)]
imx6: Added DEK blob generator command

Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a AES-256 key is randomly generated to encrypt the DEK.
This key is encrypted with the OTP Secret key
from SoC. The resulting blob consists of the encrypted
AES-256 key, the encrypted DEK, and a 16-bit MAC.

During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process,  is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.

Commands added
--------------
  dek_blob - encapsulating DEK as a cryptgraphic blob

Commands Syntax
---------------
  dek_blob src dst len

    Encapsulate and create blob of a len-bits DEK at
    address src and store the result at address dst.

Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com>
Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
6 years agomx6sabre: Select CMD_EXT4 options
Fabio Estevam [Thu, 26 Feb 2015 19:58:56 +0000 (16:58 -0300)]
mx6sabre: Select CMD_EXT4 options

Add EXT4 support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
6 years agomx6sabre: Enable User Mass Storage
Fabio Estevam [Thu, 26 Feb 2015 19:58:55 +0000 (16:58 -0300)]
mx6sabre: Enable User Mass Storage

User Mass Storage is very useful for flashing the on-board eMMC.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
6 years agoboard: tbs2910: Enable USB Mass Storage support
Soeren Moch [Thu, 26 Feb 2015 18:50:02 +0000 (19:50 +0100)]
board: tbs2910: Enable USB Mass Storage support

Add USB Mass Storage support. This is useful for flashing the on-board eMMC.

Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
6 years agomx35: Fix boot hang by avoiding vector relocation
Fabio Estevam [Mon, 23 Feb 2015 12:09:09 +0000 (09:09 -0300)]
mx35: Fix boot hang by avoiding vector relocation

Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx35
does not boot anymore.

Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX35 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.

This allows mx35 to boot again.

Cc: Sebastian Priebe <sebastian.priebe@cadcon.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
6 years agomx31: Fix boot hang by avoiding vector relocation
Fabio Estevam [Mon, 23 Feb 2015 12:09:08 +0000 (09:09 -0300)]
mx31: Fix boot hang by avoiding vector relocation

Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") mx31
does not boot anymore.

Add a specific relocate_vectors macro that skips the vector relocation, as the
i.MX31 SoC does not provide RAM at the high vectors address (0xFFFF0000), and
(0x00000000) maps to ROM.

This allows mx31 to boot again.

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
6 years agomx25pdk: Turn on the LCD supply
Fabio Estevam [Sat, 21 Feb 2015 19:22:50 +0000 (17:22 -0200)]
mx25pdk: Turn on the LCD supply

Currently there is no support for MC34704 PMIC in the mainline kernel.

Turn on the LCD supply via bootloader for the time being, so that we could
use the LCD in the kernel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
6 years agomc34704: Add the definition of ONOFFA bit
Fabio Estevam [Sat, 21 Feb 2015 19:22:49 +0000 (17:22 -0200)]
mc34704: Add the definition of ONOFFA bit

ONOFFA is the bit 3 of the GENERAL2 register.

Add its definition.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
6 years agoARM: HYP/non-sec: relocation before enable secondary cores
Peng Fan [Wed, 4 Feb 2015 10:15:09 +0000 (18:15 +0800)]
ARM: HYP/non-sec: relocation before enable secondary cores

If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined,
smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr(
_smp_pen), before code is relocated to secure ram.
So need relocation to secure ram before enable secondary cores.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
6 years agoARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros
Masahiro Yamada [Thu, 26 Feb 2015 17:27:06 +0000 (02:27 +0900)]
ARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros

Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs.  The line
size is still 128 byte.  Thus, the way size is 32KB/64KB for old/new
SoCs.

To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB.  It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initialization
Masahiro Yamada [Thu, 26 Feb 2015 17:27:05 +0000 (02:27 +0900)]
ARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initialization

This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: consolidate MEMCONF setting code
Masahiro Yamada [Thu, 26 Feb 2015 17:27:04 +0000 (02:27 +0900)]
ARM: UniPhier: consolidate MEMCONF setting code

This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.

The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: switch to 1CS support card
Masahiro Yamada [Thu, 26 Feb 2015 17:27:03 +0000 (02:27 +0900)]
ARM: UniPhier: switch to 1CS support card

The 3CS support card (CONFIG_DCC_MICRO_SUPPORT_CARD) used to be used
very often before, but it is recently getting a minority.  Swith to
the 1CS support card (CONFIG_PFC_MICRO_SUPPORT_CARD).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: support 1CS support card for all the UniPhier SoCs
Masahiro Yamada [Thu, 26 Feb 2015 17:27:02 +0000 (02:27 +0900)]
ARM: UniPhier: support 1CS support card for all the UniPhier SoCs

Two support card variants are used with UniPhier reference boards:
 - 1 chip select support card (original CPLD)
 - 3 chip selects support card (ARIMA-compatible CPLD)

Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: switch to xHCI for PH1-Pro4
Masahiro Yamada [Thu, 26 Feb 2015 17:27:01 +0000 (02:27 +0900)]
ARM: UniPhier: switch to xHCI for PH1-Pro4

PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously.  Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agousb: UniPhier: add UniPhier on-chip xHCI host driver support
Masahiro Yamada [Thu, 26 Feb 2015 17:27:00 +0000 (02:27 +0900)]
usb: UniPhier: add UniPhier on-chip xHCI host driver support

Support xHCI host driver used on Panasonic UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
6 years agoARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree
Masahiro Yamada [Thu, 26 Feb 2015 17:26:59 +0000 (02:26 +0900)]
ARM: UniPhier: add xHCI device nodes to PH1-Pro4 device tree

Each USB port corresponds to the following IP core:
 port0: xHCI (0x65a00000) SS+HS
 port1: xHCI (0x65c00000) HS (SS PHY is not implemented)
 port2: EHCI (0x5a800100) HS
 port3: EHCI (0x5a810100) HS

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4
Masahiro Yamada [Thu, 26 Feb 2015 17:26:58 +0000 (02:26 +0900)]
ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4

This is necessary to use the USB 3.0 host controllers on PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4
Masahiro Yamada [Thu, 26 Feb 2015 17:26:57 +0000 (02:26 +0900)]
ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4

This is necessary to use the xHCI cores for PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: replace "usb-ehci" with "generic-ehci"
Masahiro Yamada [Thu, 26 Feb 2015 17:26:56 +0000 (02:26 +0900)]
ARM: UniPhier: replace "usb-ehci" with "generic-ehci"

EHCI host controllers have a common register interface.
We may wish to implement a generic EHCI driver someday.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: move uniphier_ehci_reset() function
Masahiro Yamada [Thu, 26 Feb 2015 17:26:55 +0000 (02:26 +0900)]
ARM: UniPhier: move uniphier_ehci_reset() function

Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
6 years agoARM: UniPhier: remove EHCI platform devices
Masahiro Yamada [Thu, 26 Feb 2015 17:26:54 +0000 (02:26 +0900)]
ARM: UniPhier: remove EHCI platform devices

Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig).  Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers.  We still keep UART platform devices because they might
be useful for SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
6 years agoARM: UniPhier: enable STDMAC for EHCI
Masahiro Yamada [Thu, 26 Feb 2015 17:26:53 +0000 (02:26 +0900)]
ARM: UniPhier: enable STDMAC for EHCI

Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: reset NAND core in SPL for non-NAND boot mode
Masahiro Yamada [Thu, 26 Feb 2015 17:26:52 +0000 (02:26 +0900)]
ARM: UniPhier: reset NAND core in SPL for non-NAND boot mode

For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)

This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the power-on
reset except the NAND boot mode.  As a result, the NAND controller
begins automatic device scanning with wrong I/O pins and finally
hangs up.

Actually, U-Boot dies after printing "NAND:" on the console unless
the boot mode latch detected the NAND boot mode.

To work around this problem, reset the NAND core in SPL for non-NAND
boot modes.  If CONFIG_NAND_DENALI is enabled, the reset signal is
deasserted again in U-Boot proper.  At this time, I/O pins have been
correctly set up, the device scanning should succeed.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: split clkrst_init() into two functions
Masahiro Yamada [Thu, 26 Feb 2015 17:26:51 +0000 (02:26 +0900)]
ARM: UniPhier: split clkrst_init() into two functions

Split the current clkrst_init() into two functions:

 - early_clkrst_init(): called from SPL
  Deassert the reset signals of the memory controller and some other
  basic cores.

 - clkrst_init(): called from main U-boot
  Deassert the reset signals that are necessary for the access to
  peripherals etc.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*
Masahiro Yamada [Thu, 26 Feb 2015 17:26:50 +0000 (02:26 +0900)]
ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*

Follow the register macros in the LSI specification book.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: fix SBC init code
Masahiro Yamada [Thu, 26 Feb 2015 17:26:49 +0000 (02:26 +0900)]
ARM: UniPhier: fix SBC init code

Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: fix comments in PH1-Pro4 SBC code
Masahiro Yamada [Thu, 26 Feb 2015 17:26:48 +0000 (02:26 +0900)]
ARM: UniPhier: fix comments in PH1-Pro4 SBC code

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoserial: UniPhier: move LCR register setting to probe function
Masahiro Yamada [Thu, 26 Feb 2015 17:26:47 +0000 (02:26 +0900)]
serial: UniPhier: move LCR register setting to probe function

We do not have to set the LCR register every time we change the
baud-rate.  We just need to set it up once in the probe function.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoserial: UniPhier: use 32 bit register access
Masahiro Yamada [Thu, 26 Feb 2015 17:26:46 +0000 (02:26 +0900)]
serial: UniPhier: use 32 bit register access

For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11)
is not working correctly.  As a side effect, it also modifies MCR
register (offset = 0x10) and results in unexpected behavior.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: update defconfigs using savedefconfig
Masahiro Yamada [Thu, 26 Feb 2015 17:26:45 +0000 (02:26 +0900)]
ARM: UniPhier: update defconfigs using savedefconfig

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>
Masahiro Yamada [Thu, 26 Feb 2015 17:26:44 +0000 (02:26 +0900)]
ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>

Since commit 0e7368c6c426 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: move SoC headers to mach-uniphier/include/mach
Masahiro Yamada [Thu, 26 Feb 2015 17:26:43 +0000 (02:26 +0900)]
ARM: UniPhier: move SoC headers to mach-uniphier/include/mach

Move arch/arm/include/asm/arch-uniphier/*
  -> arch/arm/mach-uniphier/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoARM: UniPhier: move SoC sources to mach-uniphier
Masahiro Yamada [Thu, 26 Feb 2015 17:26:42 +0000 (02:26 +0900)]
ARM: UniPhier: move SoC sources to mach-uniphier

Move
arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
6 years agoExynos: Fix L2 cache timings on Exynos5420 and Exynos5800
Doug Anderson [Fri, 20 Feb 2015 07:57:20 +0000 (13:27 +0530)]
Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800

It was found that the L2 cache timings that we had before could cause
freezes and hangs.  We should make things more robust with better
timings.  Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).

This also provides a big cleanup of the L2 cache init code avoiding
some duplication.  The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
  time) and left resident in iRAM for the kernel to use when bringing
  up additional CPUs.  It used configure_l2_ctlr() and
  configure_l2_actlr() when it detected it was on an A15.  This was
  needed (despite the L2 cache registers being shared among all A15s)
  because we might have been the first man in after the whole A15
  cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
  time.  Strangely this called configure_l2_ctlr() but not
  configure_l2_actlr() which was almost certainly wrong.  Given that
  we'll call both (see next bullet) later in the boot process it
  didn't matter for normal boot, but I guess this is how L2 cache
  settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
  This should happen at boot time (normally in the SPL except for USB
  boot where it happens in main U-Boot).

Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time.  For resume time we'd get it
anyway when the 2nd A15 core came up.

Let's make this a whole lot simpler.  Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.

Intended net effects of this change (other than cleanup):
* Timings go from before:
    data: 0 cycle setup, 3 cycles (0x2) latency
    tag:  0 cycle setup, 3 cycles (0x2) latency
  after:
    data: 1 cycle setup, 4 cycles (0x3) latency
    tag:  1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.

One note is that we're still relying on luck to keep low_power_start()
working.  The compiler is being nice and not storing anything on the
stack.

Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL.  The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
  (after it has turned the L2 cache off).  This is why the functions
  are in a header file instead of lowlevel_init.c.

* Have the kernel save the L2 cache settings of the boot CPU and apply
  them to all other CPUs.  We get a little lucky here because the old
  code was using "|=" to modify the registers and all of the bits that
  it's setting are also present in the new settings (!).  That means
  that when the 2nd CPU in the A15 cluster comes up it doesn't
  actually mess up the settings of the 1st CPU in the A15 cluster.  An
  alternative option is to have the kernel write its own
  low_power_start() code.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: Make A7s boot with thumb-mode U-Boot on warm reset
Akshay Saraswat [Fri, 20 Feb 2015 07:57:19 +0000 (13:27 +0530)]
Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset

On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.

The A7 cores do jump to 0x0 but consider following instructions as a Thumb
instructions which in turn makes them loop inside the iROM code instead of
jumping to power_down_core.

This issue is fixed by replacing the "mov pc" instruction with a "bx"
instruction which switches state along with the jump to make the execution
unit consider the branch target as an ARM instruction.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: Fix secondary core booting for thumb
Akshay Saraswat [Fri, 20 Feb 2015 07:57:18 +0000 (13:27 +0530)]
Exynos542x: Fix secondary core booting for thumb

When compiled SPL for Thumb secondary cores failed to boot
at the kernel boot up. Only one core came up out of 4.
This was happening because the code relocated to the
address 0x02073000 by the primary core was an ARM asm
code which was executed by the secondary cores as if it
was a thumb code.
This patch fixes the issue of secondary cores considering
relocated code as Thumb instructions and not ARM instructions
by jumping to the relocated with the help of "bx" ARM instruction.
"bx" instruction changes the 5th bit of CPSR which allows
execution unit to consider the following instructions as ARM
instructions.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: add L2 control register configuration
Akshay Saraswat [Fri, 20 Feb 2015 07:57:17 +0000 (13:27 +0530)]
Exynos542x: add L2 control register configuration

This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
   0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
   We need to restore this here due to switching.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: cache: Disable clean/evict push to external
Akshay Saraswat [Fri, 20 Feb 2015 07:57:16 +0000 (13:27 +0530)]
Exynos542x: cache: Disable clean/evict push to external

L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: Add workaround for exynos iROM errata
Akshay Saraswat [Fri, 20 Feb 2015 07:57:15 +0000 (13:27 +0530)]
Exynos542x: Add workaround for exynos iROM errata

iROM logic provides undesired jump address for CPU2.
This patch adds a programmable susbstitute for a part of
iROM logic which wakes up cores and provides jump addresses.
This patch creates a logic to make all secondary cores jump
to a particular address which evades the possibility of CPU2
jumping to wrong address and create undesired results.

Logic of the workaround:

Step-1: iROM code checks value at address 0x2020028.
Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
else, it continues executing normally.
Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
0x2020028 and jump address (pointer to function low_power_start)
in (0x202000+CPUid*4).
Step-4: When secondary cores recieve event signal they jump to this address
and continue execution.

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: Add workaround for ARM errata 799270
Akshay Saraswat [Fri, 20 Feb 2015 07:57:14 +0000 (13:27 +0530)]
Exynos542x: Add workaround for ARM errata 799270

This patch adds workaround for the ARM errata 799270 which says
"If the L2 cache logic clock is stopped because of L2 inactivity,
setting or clearing the ACTLR.SMP bit might not be effective. The bit is
modified in the ACTLR, meaning a read of the register returns the
updated value. However the logic that uses that bit retains the previous
value."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: Add workaround for ARM errata 798870
Akshay Saraswat [Fri, 20 Feb 2015 07:57:13 +0000 (13:27 +0530)]
Exynos542x: Add workaround for ARM errata 798870

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: CPU: Power down all secondary cores
Akshay Saraswat [Fri, 20 Feb 2015 07:57:12 +0000 (13:27 +0530)]
Exynos542x: CPU: Power down all secondary cores

This patch adds code to shutdown secondary cores.
When U-boot comes up, all secondary cores appear powered on,
which is undesirable and causes side effects while
initializing these cores in kernel.

Secondary core power down happens in following steps:

Step-1: After Exynos power-on, primary core starts executing first.
Step-2: In iROM code every core has to check 2 flags i.e.
addresses 0x02020028 & 0x02020004.
Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
jump address for primary core and 0 for all secondary cores.
Step-4: Therefore, primary core follows normal iROM execution and jumps
to BL1 eventually, whereas all secondary cores enter WFE.
Step-5: When primary core comes into function secondary_cores_configure,
it puts pointer to function power_down_core into 0x02020004
and provides DSB and SEV for all cores so that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoExynos542x: Config: Add various configs
Akshay Saraswat [Fri, 20 Feb 2015 07:57:11 +0000 (13:27 +0530)]
Exynos542x: Config: Add various configs

This patch adds "iRAM, CPU state and low power" configs
which are the addresses acting as flag registers.

iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
to CONFIG_LOWPOWER_EN then it jumps to the address (0x02020000+CPUID*4).
This is a part of iROM logic. Rest other flags are being used at
various places during kernel switching and reset.
They are nowhere documented because they are part programming.
These configs are serving as flags for us because they are
representing the addresses in iRAM which we are using for
storing and extracting CPU Status and GIC status.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agoMAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibility
Lukasz Majewski [Thu, 26 Feb 2015 12:23:49 +0000 (13:23 +0100)]
MAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibility

After discussion during the last u-boot mini summit with USB maintainer -
Marek Vasut - it has been decided, that gadget development should be
coordinated by DFU custodian.

Such patch formalizes current development status.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
6 years agocrypto/fsl - Add progressive hashing support using hardware acceleration.
gaurav rana [Fri, 20 Feb 2015 07:21:46 +0000 (12:51 +0530)]
crypto/fsl - Add progressive hashing support using hardware acceleration.

Currently only normal hashing is supported using hardware acceleration.
Added support for progressive hashing using hardware.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
CC: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agocrypto/fsl: Make function names consistent for blob encapsulation/decapsulation.
gaurav rana [Wed, 25 Feb 2015 04:07:09 +0000 (09:37 +0530)]
crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.

This patch does the following:

1. The function names for encapsulation and decapsulation
were inconsitent in freescale's implementation and cmd_blob file.
This patch corrects the issues.
2. The function protopye is also modified to change the length parameter
from u8 to u32 to allow encapsulation and decapsulation of larger images.
3. Modified the description of km paramter in the command usage for better
readability.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
6 years agousb: gadget: fastboot: Set the Serial Number for Fastboot Gadget
Dileep Katta [Fri, 13 Feb 2015 06:33:43 +0000 (14:33 +0800)]
usb: gadget: fastboot: Set the Serial Number for Fastboot Gadget

Configure the serial number using the serial# environment variable
during the fastboot bind.

This enables "fastboot devices" to return the serial number for
the attached devices.

Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
6 years agofastboot: Correct fastboot_fail and fastboot_okay strings
Dileep Katta [Fri, 13 Feb 2015 06:33:42 +0000 (14:33 +0800)]
fastboot: Correct fastboot_fail and fastboot_okay strings

If the string is copied without NULL termination using strncpy(),
then strncat() on the next line, may concatenate the string after
some stale (or random) data, if the response string was not
zero-initialized.

Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
6 years agofastboot: OUT transaction length must be aligned to wMaxPacketSize
Dileep Katta [Mon, 16 Feb 2015 20:32:36 +0000 (02:02 +0530)]
fastboot: OUT transaction length must be aligned to wMaxPacketSize

OUT transactions must be aligned to wMaxPacketSize for each transfer,
or else transfer will not complete successfully. This patch modifies
rx_bytes_expected to return a transfer length that is aligned to
wMaxPacketSize.

Note that the value of wMaxPacketSize and ep->maxpacket may not be
the same value, and it is the value of wMaxPacketSize that should be
used for alignment. wMaxPacketSize is passed depending on the speed of
connection.

Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
6 years agofastboot: Add USB cable detect check
Rob Herring [Mon, 26 Jan 2015 21:14:41 +0000 (15:14 -0600)]
fastboot: Add USB cable detect check

Add a check for USB cable attached and only enter fastboot when a cable
is attached.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
6 years agousb: gadget: fastboot: Add fastboot erase
Dileep Katta [Tue, 17 Feb 2015 13:18:23 +0000 (18:48 +0530)]
usb: gadget: fastboot: Add fastboot erase

Adds the fastboot erase functionality, to erase a partition
specified by name. The erase is performed based on erase group size,
to avoid erasing other partitions. The start address and the size
is aligned to the erase group size for this.

Currently only supports erasing from eMMC.

Signed-off-by: Dileep Katta <dileep.katta@linaro.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
6 years agoodroid: adjust get_dfu_alt_*() functions to new declarations
Inha Song [Tue, 17 Feb 2015 11:24:12 +0000 (12:24 +0100)]
odroid: adjust get_dfu_alt_*() functions to new declarations

This change is required after updated dfu_alt_system/boot declarations.

Signed-off-by: Inha Song <ideal.song@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Odroid U3 (Exynos 4412)]
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
6 years agodfu: samsung: move call to set_dfu_alt_info() to dfu common code
Przemyslaw Marczak [Tue, 17 Feb 2015 11:24:11 +0000 (12:24 +0100)]
dfu: samsung: move call to set_dfu_alt_info() to dfu common code

This common call can be used for setting proper entities based
on dfu command arguments.
The config: CONFIG_SET_DFU_ALT_INFO, was used only for few configs,
and now it is common.

The board file should implement:
- set_dfu_alt_info() function

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Odroid U3 (Exynos 4412)]

6 years agofastboot: add support for "oem format" command
Rob Herring [Mon, 26 Jan 2015 21:49:01 +0000 (15:49 -0600)]
fastboot: add support for "oem format" command

Add "oem format" command to write partition table. This relies on the
env variable partitions to contain the list of partitions as required by
the gpt command.

Note that this does not erase any data other than the partition table.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Steve Rae <srae@broadcom.com>
6 years agofastboot: add "fastboot oem" command support
Michael Scott [Mon, 26 Jan 2015 21:49:00 +0000 (15:49 -0600)]
fastboot: add "fastboot oem" command support

Add code stub to handle "fastboot oem __" command. As unlock is a common
fastboot command, distinguish that it is not implemented.

Signed-off-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Steve Rae <srae@broadcom.com>
6 years agoedminiv2: drop CONFIG_CFI_LEGACY
Albert ARIBAUD [Sun, 1 Feb 2015 11:04:43 +0000 (12:04 +0100)]
edminiv2: drop CONFIG_CFI_LEGACY

Nowadays generic CFI code properly detects the ED Mini V2's
Macronix MC29LV400CB flash chip, therefore we can drop the
CONFIG_FLASH_CFI_LEGACY option and associated settings and code.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
6 years agoedminiv2: switch to SPL
Albert ARIBAUD [Sat, 31 Jan 2015 21:55:38 +0000 (22:55 +0100)]
edminiv2: switch to SPL

ED Mini V2 is based on Orion 5x which boots at fixed
address 0xFFFF0000 in NOR Flash. Place SPL there, and
switch U-Boot from .bin to .img format, stored in
NOR Flash at 0xFFF90000.

Note: this patch was tested on HW and works, i.e.
it boots U-Boot properly, but SPL console output
currently does not appear, due to GD being trashed
by arch/arm/lib/spl.c. This trashing is soon to be
removed, and then ED Mini V2 SPL console output will
become visible.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
6 years agoedminiv2: fix PCIE IO base address typo
Albert ARIBAUD [Sat, 31 Jan 2015 21:49:39 +0000 (22:49 +0100)]
edminiv2: fix PCIE IO base address typo

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
6 years agoedminiv2: switch to generic board support
Albert ARIBAUD [Sat, 31 Jan 2015 10:52:38 +0000 (11:52 +0100)]
edminiv2: switch to generic board support

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
6 years agoarm: rmobile: silk: Add support SDHI
Vladimir Barinov [Tue, 24 Feb 2015 16:55:46 +0000 (18:55 +0200)]
arm: rmobile: silk: Add support SDHI

This adds GPIO configuration and initialization function of SDHI on Silk board

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: silk: fix typo in device declaration
Vladimir Barinov [Tue, 24 Feb 2015 16:54:48 +0000 (18:54 +0200)]
arm: rmobile: silk: fix typo in device declaration

Fix typo in device declaration

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: silk: Disable ethernet pins pull-up
Vladimir Barinov [Tue, 24 Feb 2015 16:54:31 +0000 (18:54 +0200)]
arm: rmobile: silk: Disable ethernet pins pull-up

Disable pull-ups on ethrenet lines

Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: silk: Fix GPIO4_31 initialization
Vladimir Barinov [Tue, 24 Feb 2015 16:54:18 +0000 (18:54 +0200)]
arm: rmobile: silk: Fix GPIO4_31 initialization

Use gpio_direction_output instead of gpio_set_value
since the latter does not set output GPIO direction.

Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com>
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: Add Porter board support
Vladimir Barinov [Fri, 13 Feb 2015 22:06:13 +0000 (01:06 +0300)]
arm: rmobile: Add Porter board support

Porter is an entry level development board based on R-Car M2 SoC (R8A7791)

This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, SD, USB Host

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agosh: enable CONFIG_USE_PRIVATE_LIBGCC by default
Masahiro Yamada [Tue, 10 Feb 2015 12:37:02 +0000 (21:37 +0900)]
sh: enable CONFIG_USE_PRIVATE_LIBGCC by default

Now this feature works.  Let's turn it on by default so we do not
depend on specific tool-chains.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agosh: import missing private libraries from Linux 3.19
Masahiro Yamada [Tue, 10 Feb 2015 12:37:01 +0000 (21:37 +0900)]
sh: import missing private libraries from Linux 3.19

SuperH is supposed to support the Private Library feature, but it is
actually not working.

If CONFIG_USE_PRIVATE_LIBGCC is enabled, the build fails for the
undefined references to '__sdivsi3_i4i' and '__udivsi3_i4i'.

To fix this error, import missing libraries from Linux 3.19
and adjust them for U-Boot:
  - Remove "#include <linux/module.h>" and "EXPORT_SYMBOL(...)"
  - Use SPDX-License-Identifier
  - Remove white space

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agosh: rename some private libraries
Masahiro Yamada [Tue, 10 Feb 2015 12:37:00 +0000 (21:37 +0900)]
sh: rename some private libraries

Rename two files to the corresponding file names in Linux.
This helps us find missing libraries in the next commit.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoserial: sh: fix internal clock source on SCIF
Vladimir Barinov [Fri, 13 Feb 2015 22:05:18 +0000 (01:05 +0300)]
serial: sh: fix internal clock source on SCIF

The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows:

BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1,
the prescaler is 0 due to SCSMR settings, hence n=0

Also SCSCR must be set to use internal or external clock source.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoserial: sh: Remove invalid UTF-8 character
Nobuhiro Iwamatsu [Wed, 10 Dec 2014 05:42:05 +0000 (14:42 +0900)]
serial: sh: Remove invalid UTF-8 character

serial_sh.c contains invalid UTF-8 character.
This deletes the character.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: lager: Add support SDHI
Nobuhiro Iwamatsu [Fri, 21 Nov 2014 01:19:32 +0000 (10:19 +0900)]
arm: rmobile: lager: Add support SDHI

Lager board has two SDHI port as SDHI0 and SDHI2.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: gose: Add support SDHI
Nobuhiro Iwamatsu [Wed, 12 Nov 2014 02:29:39 +0000 (11:29 +0900)]
arm: rmobile: gose: Add support SDHI

Gose board has three SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: koelsch: Add support SDHI
Nobuhiro Iwamatsu [Wed, 12 Nov 2014 04:03:54 +0000 (13:03 +0900)]
arm: rmobile: koelsch: Add support SDHI

Koelsch board has three SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: alt: Add support SDHI
Nobuhiro Iwamatsu [Wed, 19 Nov 2014 05:26:33 +0000 (14:26 +0900)]
arm: rmobile: alt: Add support SDHI

Alt board has two SDHI port.
This adds GPIO configuration and initialization function of SDHI, and
enables MMC command.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: silk: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 07:20:04 +0000 (16:20 +0900)]
arm: rmobile: silk: Migrate serial driver to drivers model

This adds drivers model support of serial port to Silk board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: alt: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 07:20:04 +0000 (16:20 +0900)]
arm: rmobile: alt: Migrate serial driver to drivers model

This adds drivers model support of serial port to Alt board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: lager: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 07:20:04 +0000 (16:20 +0900)]
arm: rmobile: lager: Migrate serial driver to drivers model

This adds drivers model support of serial port to Lager board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: gose: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 02:24:01 +0000 (11:24 +0900)]
arm: rmobile: gose: Migrate serial driver to drivers model

This adds drivers model support of serial port to Gose board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agoarm: rmobile: koelsch: Migrate serial driver to drivers model
Nobuhiro Iwamatsu [Tue, 9 Dec 2014 02:24:01 +0000 (11:24 +0900)]
arm: rmobile: koelsch: Migrate serial driver to drivers model

This adds drivers model support of serial port to Koelsch board,
and migrate serial port to drivers model.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 years agozmx25: Convert to generic board
Fabio Estevam [Mon, 23 Feb 2015 11:51:38 +0000 (08:51 -0300)]
zmx25: Convert to generic board

Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal
from the project.

Cc: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>