Alban Bedel [Wed, 20 Nov 2013 16:42:46 +0000 (17:42 +0100)]
arm: tegra: Fix the CPU complex reset masks
The CPU complex reset masks are not matching with the datasheet for
the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20
and T30 the register consist of groups of 4 bits, with one bit for
each CPU core. On T20 the 2 high bits of each group are always stubbed
as there is only 2 cores.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Alban Bedel [Thu, 14 Nov 2013 09:58:30 +0000 (10:58 +0100)]
ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board
Add support for the new Tamonten™ NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Jim Lin [Wed, 6 Nov 2013 06:03:44 +0000 (14:03 +0800)]
ARM: config: USB: Tegra30/114: Fix EHCI timeout issue on "bootp"
Fix the timeout issue after running "bootp" command in u-boot
console. For example you see "EHCI timed out on TD- token=0x...".
TXFIFOTHRES bits of TXFILLTUNING register should be set to 0x10
after a controller reset and before RUN bit is set
(per technical reference manual).
Signed-off-by: Jim Lin <jilin@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Jimmy Zhang [Mon, 23 Sep 2013 20:07:49 +0000 (22:07 +0200)]
Tegra114: Fix PLLX M, N, P init settings
The M, N and P width have been changed from Tegra30. The maximum value
for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should
be set accordingly.
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Bo Shen [Tue, 10 Dec 2013 08:14:02 +0000 (16:14 +0800)]
arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position
In config_cmd_default.h, it will use CONFIG_SYS_NO_FLASH to decide
whether include CONFIG_CMD_FLASH and CONFIG_CMD_IMLS. So, move the
CONFIG_SYS_NO_FLASH to proper position, then we don't need to undef
these two commands.
Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Lokesh Vutla [Thu, 12 Dec 2013 10:06:21 +0000 (15:36 +0530)]
ARM: OMAP5: clocks: Update MPU settings for OPP_NOM
As per the latest 0.6 version of DM for OMAP5430 ES2.0,
MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU
should be locked at 2000MHz. Fixing the same and cleaning the
previously used dpll values.
Lokesh Vutla [Thu, 12 Dec 2013 10:04:56 +0000 (15:34 +0530)]
ARM: DRA7xx: Change clk divider setting
Commit "armv7: hw_data: change clock divider setting"
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.
Nikita Kiryanov [Wed, 11 Dec 2013 16:04:40 +0000 (18:04 +0200)]
arm: omap: cm_t35: update config file
This patch makes the following updates to the cm_t35 config file:
- Replace "ttyS" in default environment kernel bootargs with the new "ttyO"
notation.
- Remove "omapfb.debug=y" from default environment kernel bootargs.
- Define a minimal power-on delay for USB hub ports so that slow-to-power-on USB
sticks will have enough time to become responsive.
- Add support for bootz command
- ulpi_reset is not necessary and always fails with the following error message:
"ULPI: ulpi_reset: failed writing reset bit"
So, remove it.
Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 4 Dec 2013 14:14:20 +0000 (09:14 -0500)]
am335x_evm: Consolidate DFU environment parts into the DFU part of the file
To make managing the environment easier, add DFUARGS to
CONFIG_EXTRA_ENV_SETTINGS. Then we set DFUARGS down in the DFU part of
the file, and include (or not) the NAND part, based on if NAND is set.
Stefan Roese [Wed, 4 Dec 2013 12:54:18 +0000 (13:54 +0100)]
arm: omap3: Add SPL support to cm_t35
Add SPL U-Boot support to replace x-loader on the Compulab cm_t35
board. Currently only the 256MiB SDRAM board versions are supported.
Tested by booting via MMC and NAND.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Stefan Roese [Wed, 4 Dec 2013 08:27:37 +0000 (09:27 +0100)]
arm: omap3: Add HEAD acoustics (HA) board variant omap3_ha to tao3530
The Head acoustics (HA) baseboard used the Technexion TAO3530 SOM
and has only some minor differences to the Technexion Thunder baseboard.
This patch adds support for this HA baseboard / TAO3530 as the "omap3_ha"
build target.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de> Cc: Tom Rini <trini@ti.com>
Stefan Roese [Wed, 4 Dec 2013 08:27:35 +0000 (09:27 +0100)]
arm: omap3: Remove bootargs mem_size handling
The memory size is autodetected and is passed to the Linux kernel
either via ATAGs or device-tree (dtb). So there is no need to
pass it via the bootargs.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de> Cc: Tom Rini <trini@ti.com>
Stefan Roese [Wed, 4 Dec 2013 08:27:34 +0000 (09:27 +0100)]
arm: omap3: Add SPL support to tao3530
Add SPL support for the Technexion TAO3530 SOM to replace
x-loader. Tested with the Thunder baseboard. Currently this is
only tested with the TAO3530 SOM revision (Ax/Bx).
Tested by booting via MMC and NAND.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Thorsten Eisbein <thorsten.eisbein@head-acoustics.de> Cc: Tom Rini <trini@ti.com>
Lokesh Vutla [Wed, 4 Dec 2013 06:52:55 +0000 (12:22 +0530)]
ARM: OMAP4: Move TEXT_BASE down to non-HS limit
With the current scenario SPL size is being overlapped with the public
stack and not allowing any OMAP4 device to boot. So the suggestion came
up was to move the TEXT_BASE down to non-HS limit. Fixing the same and
also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image
downloadable area.
Discussion on this can be seen here:
https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html
Jeroen Hofstee [Thu, 21 Nov 2013 21:32:51 +0000 (22:32 +0100)]
ARM: fix the standalone programs
The standalone programs do not use the api calls, but rely
directly on u-boot variable gd->jt for the jump table. Commit fe1378a - "ARM: use r9 for gd" changed the register holding
the address of gd, but the assembly code in the standalone
examples was not updated accordingly. This broke the programs
on ARM relying on the jumptable in the v2013.10 release.
This patch unbricks them by using the correct register.
Cc: Michal Simek <monstr@monstr.eu> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Mike Frysinger [Tue, 3 Dec 2013 23:43:27 +0000 (16:43 -0700)]
sandbox: spi: Add new SPI flash driver
This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write. Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.
sjg@chromium.org added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.
Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
arm: at91: support for the Calao USB-A9263 board (based on AT91SAM9263)
Add support for USB-A9263 board manufactured by Calao Systems
(http://www.calao-systems.com/).
Code is based on old U-Boot sources (2010.09) released by Calao.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Mon, 2 Dec 2013 06:47:23 +0000 (07:47 +0100)]
arm, at91: add siemens corvus board
enable support for the siemens AT91SAM9G20 based board corvus.
Signed-off-by: Boris Schmidt <boris.schmidt@siemens.com> Reviewed-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Heiko Schocher [Mon, 2 Dec 2013 06:47:22 +0000 (07:47 +0100)]
arm, at91: add Siemens board taurus and axm
enable support for the siemens AT91SAM9G20 based boards taurus
and axm.
Signed-off-by: Roger Meier <r.meier@siemens.com> Reviewed-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Priyanka Jain [Thu, 28 Nov 2013 04:42:16 +0000 (10:12 +0530)]
powerpc: mmc: Add corenet devices support in esdhc spl
Existing eSDHC SPL framework assumes booting from sd-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Alexey Brodkin [Wed, 27 Nov 2013 13:00:52 +0000 (17:00 +0400)]
mmc/dwmmc: modify FIFO threshold only if value explicitly set
If platform provides "host->fifoth_val" it will be used for
initialization of DWMCI_FIFOTH register. Otherwise default value will be
used.
This implementation allows:
* escape unclear and recursive calculations that are currently in use
* use whatever custom value for DWMCI_FIFOTH initialization if any
particular SoC requires it
Albert ARIBAUD [Thu, 7 Nov 2013 13:21:46 +0000 (14:21 +0100)]
arm: keep all sections in ELF file
Current LDS files /DISCARD/ a lot of sections when linking ELF
files, causing diagnostic tools such as readelf or objdump to
produce partial output. Keep all section at link stage, filter
only at objcopy time so that .bin remains minimal.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Masahiro Yamada [Mon, 7 Oct 2013 02:46:56 +0000 (11:46 +0900)]
ARM: align MVBAR on 32 byte boundary
The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.
This commit moves ".algin 5" directive to the correct place.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: Andre Przywara <andre.przywara@linaro.org>
Roger Quadros [Mon, 2 Dec 2013 13:47:43 +0000 (15:47 +0200)]
usb: ehci-omap: Reset the USB Host OMAP module
In commit bb1f327 we removed the UHH reset to fix NFS root (over usb
ethernet) problems with Beagleboard (3530 ES1.0). However, this
seems to cause USB detection problems for Pandaboard, about (3/8).
On further investigation, it seems that doing the UHH reset is not
the cause of the original Beagleboard problem, but in the way the reset
was done.
This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based
on the UHH_REVISION register. This should fix the Beagleboard NFS
problem as well as the Pandaboard USB detection problem.
Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> CC: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Roger Quadros <rogerq@ti.com>
arm: omap3: Enable clocks for peripherals only if they are used
This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
activated. So if the board use the uart(x) as a console we need
to activate it. The Board's config should include define to enable
every subsystem that the board use. For a complete list
of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER
should be checked.
Right now the bootloader can enable and disable clocks for:
uart(x) using CONFIG_SYS_NS16550
gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 }
i2c bus using CONFIG_DRIVER_OMAP34XX_I2C.
Not required gptimer(x) and mcbsp(x) for booting are disabled by default and
are not supported by any define.
Their activation need to included in the per_clocks_enable if the
peripheral is included. Not booting board should enable the peripheral
clock connected to their driver
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Minkyu Kang [Fri, 6 Dec 2013 10:04:03 +0000 (19:04 +0900)]
arm: exynos: adds ifdef for spi boot
This patch fix following errors and warnings
spl_boot.c: In function 'exynos_spi_copy':
spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function)
spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in
spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function)
spl_boot.c: In function 'copy_uboot_to_ram':
spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable]
spl_boot.c: At top level:
spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function]
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Axel Lin [Mon, 2 Dec 2013 04:57:44 +0000 (12:57 +0800)]
spi: bfin_spi6xx: Remove unnecessary test for bus and pins[bus]
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Axel Lin [Mon, 2 Dec 2013 04:57:33 +0000 (12:57 +0800)]
spi: bfin_spi: Remove unnecessary test for bus and pins[bus]
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.
Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
i2c: samsung: register i2c busses for Exynso5420 and Exynos5250
This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels
on Exynos5420 and Exynos5250 and also adds support for init function
for hsi2c channels
Nikita Kiryanov [Thu, 28 Nov 2013 16:04:42 +0000 (18:04 +0200)]
arm: omap: i2c: don't zero cnt in i2c_write
Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
based devices. This seems to be related to the following advisory which
apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
OMAP4430 TRM:
Advisory:
I2C Module Does Not Allow 0-Byte Data Requests
Details:
When configured as the master, the I2C module does not allow 0-byte data
transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause
undefined behavior.
Workaround(s):
No workaround. Do not use 0-byte data requests.
The writes in question are unnecessary from a functional point of view.
Most of them are done after I/O has finished, and the only one that preceds
I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before
actual data transmission takes place.
Therefore, remove all writes that zero the cnt register.
Kuo-Jung Su [Mon, 2 Dec 2013 08:02:59 +0000 (16:02 +0800)]
cmd_eeprom: bug fix for i2c read/write
The local pointer of address (i.e., addr) only gets
referenced under SPI mode, and it won't be appropriate
to pass only 1-byte addr[1] to i2c_read/i2c_write while
CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 1.
1. In U-boot's I2C model, the address would be re-assembled
to a byte string in MSB order inside I2C controller drivers.
2. The 'CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW' option which could
be found at soft_i2c.c is always turned on in cmd_eeprom.c,
the addr[0] always contains the device address with overflowed
MSB address bits.
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
cc: Peter Tyser <ptyser@xes-inc.com> Cc: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com>
York Sun [Tue, 3 Dec 2013 21:16:59 +0000 (13:16 -0800)]
powerpc/mpc8349: Use generic mpc85xx DDR driver
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.
Priyanka Jain [Thu, 28 Nov 2013 04:38:12 +0000 (10:08 +0530)]
powerpc: spiflash:Add corenet devices support in eSPI SPL
Existing eSPI SPL framework assumes booting from spi-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
Po Liu [Tue, 26 Nov 2013 06:34:07 +0000 (14:34 +0800)]
powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
Currently, there is only one EEPROM on c29xpcie board which is AT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.
Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
Dave Liu [Thu, 28 Nov 2013 06:58:08 +0000 (14:58 +0800)]
powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.
Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
projects / karo-tx-uboot.git / log