git.kernelconcepts.de Git - karo-tx-uboot.git/blob

1 /dts-v1/;

2

3 /include/ "coreboot.dtsi"

4

5 / {

6 #address-cells = <1>;

7 #size-cells = <1>;

8 model = "Google Link";

9 compatible = "google,link", "intel,celeron-ivybridge";

10

11 config {

12 silent_console = <0>;

13 };

14

15 gpioa {

16 compatible = "intel,ich6-gpio";

17 u-boot,dm-pre-reloc;

18 reg = <0 0x10>;

19 bank-name = "A";

20 };

21

22 gpiob {

23 compatible = "intel,ich6-gpio";

24 u-boot,dm-pre-reloc;

25 reg = <0x30 0x10>;

26 bank-name = "B";

27 };

28

29 gpioc {

30 compatible = "intel,ich6-gpio";

31 u-boot,dm-pre-reloc;

32 reg = <0x40 0x10>;

33 bank-name = "C";

34 };

35

36 serial {

37 reg = <0x3f8 8>;

38 clock-frequency = <115200>;

39 };

40

41 chosen { };

42 memory { device_type = "memory"; reg = <0 0>; };

43

44 spd {

45 compatible = "memory-spd";

46 #address-cells = <1>;

47 #size-cells = <0>;

48 elpida_4Gb_1600_x16 {

49 reg = <0>;

50 data = [92 10 0b 03 04 19 02 02

51 03 52 01 08 0a 00 fe 00

52 69 78 69 3c 69 11 18 81

53 20 08 3c 3c 01 40 83 81

54 00 00 00 00 00 00 00 00

55 00 00 00 00 00 00 00 00

56 00 00 00 00 00 00 00 00

57 00 00 00 00 0f 11 42 00

58 00 00 00 00 00 00 00 00

59 00 00 00 00 00 00 00 00

60 00 00 00 00 00 00 00 00

61 00 00 00 00 00 00 00 00

62 00 00 00 00 00 00 00 00

63 00 00 00 00 00 00 00 00

64 00 00 00 00 00 02 fe 00

65 11 52 00 00 00 07 7f 37

66 45 42 4a 32 30 55 47 36

67 45 42 55 30 2d 47 4e 2d

68 46 20 30 20 02 fe 00 00

69 00 00 00 00 00 00 00 00

70 00 00 00 00 00 00 00 00

71 00 00 00 00 00 00 00 00

72 00 00 00 00 00 00 00 00

73 00 00 00 00 00 00 00 00

74 00 00 00 00 00 00 00 00

75 00 00 00 00 00 00 00 00

76 00 00 00 00 00 00 00 00

77 00 00 00 00 00 00 00 00

78 00 00 00 00 00 00 00 00

79 00 00 00 00 00 00 00 00

80 00 00 00 00 00 00 00 00

81 00 00 00 00 00 00 00 00];

82 };

83 samsung_4Gb_1600_1.35v_x16 {

84 reg = <1>;

85 data = [92 11 0b 03 04 19 02 02

86 03 11 01 08 0a 00 fe 00

87 69 78 69 3c 69 11 18 81

88 f0 0a 3c 3c 01 40 83 01

89 00 80 00 00 00 00 00 00

90 00 00 00 00 00 00 00 00

91 00 00 00 00 00 00 00 00

92 00 00 00 00 0f 11 02 00

93 00 00 00 00 00 00 00 00

94 00 00 00 00 00 00 00 00

95 00 00 00 00 00 00 00 00

96 00 00 00 00 00 00 00 00

97 00 00 00 00 00 00 00 00

98 00 00 00 00 00 00 00 00

99 00 00 00 00 00 80 ce 01

100 00 00 00 00 00 00 6a 04

101 4d 34 37 31 42 35 36 37

102 34 42 48 30 2d 59 4b 30

103 20 20 00 00 80 ce 00 00

104 00 00 00 00 00 00 00 00

105 00 00 00 00 00 00 00 00

106 00 00 00 00 00 00 00 00

107 00 00 00 00 00 00 00 00

108 00 00 00 00 00 00 00 00

109 00 00 00 00 00 00 00 00

110 00 00 00 00 00 00 00 00

111 00 00 00 00 00 00 00 00

112 00 00 00 00 00 00 00 00

113 00 00 00 00 00 00 00 00

114 00 00 00 00 00 00 00 00

115 00 00 00 00 00 00 00 00

116 00 00 00 00 00 00 00 00];

117 };

118 micron_4Gb_1600_1.35v_x16 {

119 reg = <2>;

120 data = [92 11 0b 03 04 19 02 02

121 03 11 01 08 0a 00 fe 00

122 69 78 69 3c 69 11 18 81

123 20 08 3c 3c 01 40 83 05

124 00 00 00 00 00 00 00 00

125 00 00 00 00 00 00 00 00

126 00 00 00 00 00 00 00 00

127 00 00 00 00 0f 01 02 00

128 00 00 00 00 00 00 00 00

129 00 00 00 00 00 00 00 00

130 00 00 00 00 00 00 00 00

131 00 00 00 00 00 00 00 00

132 00 00 00 00 00 00 00 00

133 00 00 00 00 00 00 00 00

134 00 00 00 00 00 80 2c 00

135 00 00 00 00 00 00 ad 75

136 34 4b 54 46 32 35 36 36

137 34 48 5a 2d 31 47 36 45

138 31 20 45 31 80 2c 00 00

139 00 00 00 00 00 00 00 00

140 00 00 00 00 00 00 00 00

141 00 00 00 00 00 00 00 00

142 ff ff ff ff ff ff ff ff

143 ff ff ff ff ff ff ff ff

144 ff ff ff ff ff ff ff ff

145 ff ff ff ff ff ff ff ff

146 ff ff ff ff ff ff ff ff

147 ff ff ff ff ff ff ff ff

148 ff ff ff ff ff ff ff ff

149 ff ff ff ff ff ff ff ff

150 ff ff ff ff ff ff ff ff

151 ff ff ff ff ff ff ff ff];

152 };

153 };

154

155 spi {

156 #address-cells = <1>;

157 #size-cells = <0>;

158 compatible = "intel,ich9";

159 spi-flash@0 {

160 reg = <0>;

161 compatible = "winbond,w25q64", "spi-flash";

162 memory-map = <0xff800000 0x00800000>;

163 };

164 };

165

166 lpc {

167 compatible = "intel,lpc";

168 #address-cells = <1>;

169 #size-cells = <1>;

170 gen-dec = <0x800 0xfc 0x900 0xfc>;

171 cros-ec@200 {

172 compatible = "google,cros-ec";

173 reg = <0x204 1 0x200 1 0x880 0x80>;

174

175 /* This describes the flash memory within the EC */

176 #address-cells = <1>;

177 #size-cells = <1>;

178 flash@8000000 {

179 reg = <0x08000000 0x20000>;

180 erase-value = <0xff>;

181 };

182 };

183 };

184

185 microcode {

186 update@0 {

187 #include "m12206a7_00000028.dtsi"

188 };

189 update@1 {

190 #include "m12306a9_00000017.dtsi"

191 };

192 };

193

194 };