From 19c9eb862853bc7c2bc611fbd485b576d3344fa6 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Fri, 9 Jan 2015 11:49:52 +0100 Subject: [PATCH] karo: tx6: add support for 16bit SDRAM bus width --- board/karo/tx6/lowlevel_init.S | 64 +++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 16 deletions(-) diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 3e1f7b73c0..d6d062a3a7 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -44,6 +44,20 @@ .endm #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val) +#if PHYS_SDRAM_1_WIDTH == 16 +#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val) +#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) +#else +#define MXC_DCD_ITEM_16(addr, val) +#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) +#endif +#if PHYS_SDRAM_1_WIDTH > 16 +#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val) +#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) +#else +#define MXC_DCD_ITEM_32(addr, val) +#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) +#endif #if PHYS_SDRAM_1_WIDTH == 64 #define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val) #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) @@ -697,8 +711,8 @@ dcd_hdr: /* DRAM_DQM[0..7] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK) @@ -743,8 +757,8 @@ dcd_hdr: /* DRAM_B[0..7]DS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK) @@ -781,8 +795,8 @@ dcd_hdr: /* MPRDDQBY[0..7]DL */ MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333) MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333) - MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333) - MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333) + MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333) + MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333) MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333) @@ -856,10 +870,13 @@ dcd_hdr: #define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0) /* Write leveling */ MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0)) - MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) + MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0)) +#if PHYS_SDRAM_1_WIDTH > 16 +#define DO_DDR_CALIB +#endif /* DQS gating calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ #if BANK_ADDR_BITS > 1 @@ -867,8 +884,8 @@ dcd_hdr: #endif MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000) @@ -881,7 +898,7 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ - MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800) +#ifdef DO_DDR_CALIB MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) @@ -891,17 +908,23 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - +#else /* DO_DDR_CALIB */ +#define MPMUR_FRC_MSR (1 << 11) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160) + MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150) + MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a) +#endif /* DO_DDR_CALIB */ /* DRAM_SDQS[0..7] pad config */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK) MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK) - +#ifdef DO_DDR_CALIB /* Read delay calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ @@ -909,7 +932,12 @@ dcd_hdr: MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - +#else /* DO_DDR_CALIB */ + MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c) + MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a) +#endif /* DO_DDR_CALIB */ +#ifdef DO_DDR_CALIB + /* Write delay calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f) @@ -921,7 +949,11 @@ dcd_hdr: MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f) #endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - +#else /* DO_DDR_CALIB */ + MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f) + MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f) + MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) +#endif /* DO_DDR_CALIB */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ #if BANK_ADDR_BITS > 1 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */ -- 2.39.2