From fcaa124b7bf70c4795eea2d0d7c6484752637bde Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Fri, 21 Aug 2015 16:21:56 +0200 Subject: [PATCH] karo: tx6: add missing setup of MMDC2_MPMUR0 --- board/karo/tx6/lowlevel_init.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index 7f47eb4d0e..4753c55d00 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -483,6 +483,7 @@ ivt_end: #define MMDC2_MPSWDRDR5 0x021b48ac #define MMDC2_MPSWDRDR6 0x021b48b0 #define MMDC2_MPSWDRDR7 0x021b48b4 +#define MMDC2_MPMUR0 0x021b48b8 #endif #ifdef CONFIG_SOC_MX6Q @@ -951,6 +952,7 @@ dcd_hdr: MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ #define MPMUR_FRC_MSR (1 << 11) MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) #ifdef DO_DDR_CALIB MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000) @@ -961,6 +963,7 @@ dcd_hdr: MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150) MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a) MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) #endif /* DO_DDR_CALIB */ MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) /* DRAM_SDQS[0..7] pad config */ @@ -1003,6 +1006,7 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f) MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f) MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR) + MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR) #endif /* DO_DDR_CALIB */ MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ #if BANK_ADDR_BITS > 1 -- 2.39.2