board/amcc/sequoia/sequoia.c

   1 /*
   2  * (C) Copyright 2006-2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <libfdt.h>
  14 #include <fdt_support.h>
  15 #include <asm/ppc4xx.h>
  16 #include <asm/ppc4xx-gpio.h>
  17 #include <asm/processor.h>
  18 #include <asm/io.h>
  19 #include <asm/bitops.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #if !defined(CONFIG_SYS_NO_FLASH)
  24 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  25 #endif
  26
  27 extern void __ft_board_setup(void *blob, bd_t *bd);
  28 ulong flash_get_size(ulong base, int banknum);
  29
  30 static inline u32 get_async_pci_freq(void)
  31 {
  32         if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
  33                 CONFIG_SYS_BCSR5_PCI66EN)
  34                 return 66666666;
  35         else
  36                 return 33333333;
  37 }
  38
  39 int board_early_init_f(void)
  40 {
  41         u32 sdr0_cust0;
  42         u32 sdr0_pfc1, sdr0_pfc2;
  43         u32 reg;
  44
  45         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  46         mtdcr(EBC0_CFGDATA, 0xb8400000);
  47
  48         /*
  49          * Setup the interrupt controller polarities, triggers, etc.
  50          */
  51         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  52         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  53         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
  54         mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
  55         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
  56         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
  57         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  58
  59         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  60         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  61         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  62         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
  63         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
  64         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
  65         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  66
  67         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  68         mtdcr(UIC2ER, 0x00000000);      /* disable all */
  69         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
  70         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
  71         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
  72         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
  73         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  74
  75         /* Check and reconfigure the PCI sync clock if necessary */
  76         ppc4xx_pci_sync_clock_config(get_async_pci_freq());
  77
  78         /* 50MHz tmrclk */
  79         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
  80
  81         /* clear write protects */
  82         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
  83
  84         /* enable Ethernet */
  85         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
  86
  87         /* enable USB device */
  88         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
  89
  90         /* select Ethernet (and optionally IIC1) pins */
  91         mfsdr(SDR0_PFC1, sdr0_pfc1);
  92         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
  93                 SDR0_PFC1_SELECT_CONFIG_4;
  94 #ifdef CONFIG_I2C_MULTI_BUS
  95         sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
  96 #endif
  97         /* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
  98         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  99         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
 100         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
 101
 102         mfsdr(SDR0_PFC2, sdr0_pfc2);
 103         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 104                 SDR0_PFC2_SELECT_CONFIG_4;
 105         mtsdr(SDR0_PFC2, sdr0_pfc2);
 106         mtsdr(SDR0_PFC1, sdr0_pfc1);
 107
 108         /* PCI arbiter enabled */
 109         mfsdr(SDR0_PCI0, reg);
 110         mtsdr(SDR0_PCI0, 0x80000000 | reg);
 111
 112         /* setup NAND FLASH */
 113         mfsdr(SDR0_CUST0, sdr0_cust0);
 114         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 115                 SDR0_CUST0_NDFC_ENABLE          |
 116                 SDR0_CUST0_NDFC_BW_8_BIT        |
 117                 SDR0_CUST0_NDFC_ARE_MASK        |
 118                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 119         mtsdr(SDR0_CUST0, sdr0_cust0);
 120
 121         return 0;
 122 }
 123
 124 int misc_init_r(void)
 125 {
 126 #if !defined(CONFIG_SYS_NO_FLASH)
 127         uint pbcr;
 128         int size_val = 0;
 129 #endif
 130 #ifdef CONFIG_440EPX
 131         unsigned long usb2d0cr = 0;
 132         unsigned long usb2phy0cr, usb2h0cr = 0;
 133         unsigned long sdr0_pfc1;
 134         char *act = getenv("usbact");
 135 #endif
 136         u32 reg;
 137
 138 #if !defined(CONFIG_SYS_NO_FLASH)
 139         /* Re-do flash sizing to get full correct info */
 140
 141         /* adjust flash start and offset */
 142         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 143         gd->bd->bi_flashoffset = 0;
 144
 145 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
 146     defined(CONFIG_SYS_RAMBOOT)
 147         mtdcr(EBC0_CFGADDR, PB3CR);
 148 #else
 149         mtdcr(EBC0_CFGADDR, PB0CR);
 150 #endif
 151         pbcr = mfdcr(EBC0_CFGDATA);
 152         size_val = ffs(gd->bd->bi_flashsize) - 21;
 153         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 154 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
 155     defined(CONFIG_SYS_RAMBOOT)
 156         mtdcr(EBC0_CFGADDR, PB3CR);
 157 #else
 158         mtdcr(EBC0_CFGADDR, PB0CR);
 159 #endif
 160         mtdcr(EBC0_CFGDATA, pbcr);
 161
 162         /*
 163          * Re-check to get correct base address
 164          */
 165         flash_get_size(gd->bd->bi_flashstart, 0);
 166
 167 #ifdef CONFIG_ENV_IS_IN_FLASH
 168         /* Monitor protection ON by default */
 169         (void)flash_protect(FLAG_PROTECT_SET,
 170                             -CONFIG_SYS_MONITOR_LEN,
 171                             0xffffffff,
 172                             &flash_info[0]);
 173
 174         /* Env protection ON by default */
 175         (void)flash_protect(FLAG_PROTECT_SET,
 176                             CONFIG_ENV_ADDR_REDUND,
 177                             CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 178                             &flash_info[0]);
 179 #endif
 180 #endif /* CONFIG_SYS_NO_FLASH */
 181
 182         /*
 183          * USB suff...
 184          */
 185 #ifdef CONFIG_440EPX
 186         if (act == NULL || strcmp(act, "hostdev") == 0) {
 187                 /* SDR Setting */
 188                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 189                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 190                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 191                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 192
 193                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 194                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 195                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 196                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 197                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 198                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 199                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 200                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 201                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 202                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 203
 204                 /*
 205                  * An 8-bit/60MHz interface is the only possible alternative
 206                  * when connecting the Device to the PHY
 207                  */
 208                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 209                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 210
 211                 /*
 212                  * To enable the USB 2.0 Device function
 213                  * through the UTMI interface
 214                  */
 215                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 216                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
 217
 218                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 219                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
 220
 221                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 222                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 223                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 224                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 225
 226                 /*clear resets*/
 227                 udelay (1000);
 228                 mtsdr(SDR0_SRST1, 0x00000000);
 229                 udelay (1000);
 230                 mtsdr(SDR0_SRST0, 0x00000000);
 231
 232                 printf("USB:   Host(int phy) Device(ext phy)\n");
 233
 234         } else if (strcmp(act, "dev") == 0) {
 235                 /*-------------------PATCH-------------------------------*/
 236                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 237
 238                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 239                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 240                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 241                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 242                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 243                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 244                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 245                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 246                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 247
 248                 udelay (1000);
 249                 mtsdr(SDR0_SRST1, 0x672c6000);
 250
 251                 udelay (1000);
 252                 mtsdr(SDR0_SRST0, 0x00000080);
 253
 254                 udelay (1000);
 255                 mtsdr(SDR0_SRST1, 0x60206000);
 256
 257                 *(unsigned int *)(0xe0000350) = 0x00000001;
 258
 259                 udelay (1000);
 260                 mtsdr(SDR0_SRST1, 0x60306000);
 261                 /*-------------------PATCH-------------------------------*/
 262
 263                 /* SDR Setting */
 264                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 265                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 266                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 267                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 268
 269                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 270                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 271                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 272                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 273                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 274                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 275                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 276                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 277                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 278                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 279
 280                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 281                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 282
 283                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 284                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
 285
 286                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 287                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 288
 289                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 290                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 291                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 292                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 293
 294                 /* clear resets */
 295                 udelay (1000);
 296                 mtsdr(SDR0_SRST1, 0x00000000);
 297                 udelay (1000);
 298                 mtsdr(SDR0_SRST0, 0x00000000);
 299
 300                 printf("USB:   Device(int phy)\n");
 301         }
 302 #endif /* CONFIG_440EPX */
 303
 304         mfsdr(SDR0_SRST1, reg);         /* enable security/kasumi engines */
 305         reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
 306         mtsdr(SDR0_SRST1, reg);
 307
 308         /*
 309          * Clear PLB4A0_ACR[WRP]
 310          * This fix will make the MAL burst disabling patch for the Linux
 311          * EMAC driver obsolete.
 312          */
 313         reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
 314         mtdcr(PLB4A0_ACR, reg);
 315
 316         return 0;
 317 }
 318
 319 int checkboard(void)
 320 {
 321         char buf[64];
 322         int i = getenv_f("serial#", buf, sizeof(buf));
 323         u8 rev;
 324         u32 clock = get_async_pci_freq();
 325
 326 #ifdef CONFIG_440EPX
 327         printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
 328 #else
 329         printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 330 #endif
 331
 332         rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
 333         printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 334
 335         if (i > 0) {
 336                 puts(", serial# ");
 337                 puts(buf);
 338         }
 339         putc('\n');
 340
 341         /*
 342          * Reconfiguration of the PCI sync clock is already done,
 343          * now check again if everything is in range:
 344          */
 345         if (ppc4xx_pci_sync_clock_config(clock)) {
 346                 printf("ERROR: PCI clocking incorrect (async=%d "
 347                        "sync=%ld)!\n", clock, get_PCI_freq());
 348         }
 349
 350         return (0);
 351 }
 352
 353 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 354 /*
 355  * Assign interrupts to PCI devices.
 356  */
 357 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 358 {
 359         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
 360 }
 361 #endif
 362
 363 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 364 /*
 365  * On NAND-booting sequoia, we need to patch the chips select numbers
 366  * in the dtb (CS0 - NAND, CS3 - NOR)
 367  */
 368 void ft_board_setup(void *blob, bd_t *bd)
 369 {
 370         int rc;
 371         int len;
 372         int nodeoffset;
 373         struct fdt_property *prop;
 374         u32 *reg;
 375         char path[32];
 376
 377         /* First do common fdt setup */
 378         __ft_board_setup(blob, bd);
 379
 380         /* And now configure NOR chip select to 3 instead of 0 */
 381         strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
 382         nodeoffset = fdt_path_offset(blob, path);
 383         prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
 384         if (prop == NULL) {
 385                 printf("Unable to update NOR chip select for NAND booting\n");
 386                 return;
 387         }
 388         reg = (u32 *)&prop->data[0];
 389         reg[0] = 3;
 390         rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
 391         if (rc) {
 392                 printf("Unable to update property NOR mappings, err=%s\n",
 393                        fdt_strerror(rc));
 394                 return;
 395         }
 396
 397         /* And now configure NAND chip select to 0 instead of 3 */
 398         strcpy(path, "/plb/opb/ebc/ndfc@3,0");
 399         nodeoffset = fdt_path_offset(blob, path);
 400         prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
 401         if (prop == NULL) {
 402                 printf("Unable to update NDFC chip select for NAND booting\n");
 403                 return;
 404         }
 405         reg = (u32 *)&prop->data[0];
 406         reg[0] = 0;
 407         rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
 408         if (rc) {
 409                 printf("Unable to update property NDFC mappings, err=%s\n",
 410                        fdt_strerror(rc));
 411                 return;
 412         }
 413 }
 414 #endif /* CONFIG_NAND_U_BOOT */