board/sbc8560/init.S

   1 /*
   2 * Copyright (C) 2002,2003, Motorola Inc.
   3 * Xianghua Xiao <X.Xiao@motorola.com>
   4 *
   5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   6 * Added support for Wind River SBC8560 board
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27 #include <ppc_asm.tmpl>
  28 #include <ppc_defs.h>
  29 #include <asm/cache.h>
  30 #include <asm/mmu.h>
  31 #include <config.h>
  32 #include <mpc85xx.h>
  33
  34 #define entry_start \
  35         mflr    r1      ;       \
  36         bl      0f      ;
  37
  38 #define entry_end \
  39 0:      mflr    r0      ;       \
  40         mtlr    r1      ;       \
  41         blr             ;
  42
  43
  44 /* LAW(Local Access Window) configuration:
  45  * 0000_0000-0800_0000: DDR(512M) -or- larger
  46  * c000_0000-cfff_ffff: PCI(256M)
  47  * d000_0000-dfff_ffff: RapidIO(256M)
  48  * e000_0000-ffff_ffff: localbus(512M)
  49  *   e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
  50  *   e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
  51  *   e800_0000-efff_ffff: LBC 128M, nothing here
  52  *   f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
  53  *   f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
  54  *   f800_0000-fdff_ffff: LBC 64M, nothing here
  55  *   fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
  56  *   fd00_0000-fdff_ffff: LBC 16M, nothing here
  57  *   fe00_0000-feff_ffff: LBC 16M, nothing here
  58  *   ff00_0000-ff6f_ffff: LBC 7M, nothing here
  59  *   ff70_0000-ff7f_ffff: CCSRBAR 1M
  60  *   ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
  61  * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
  62  *       Window.
  63  * Note: If flash is 8M at default position(last 8M),no LAW needed.
  64  */
  65
  66 #if !defined(CONFIG_SPD_EEPROM)
  67   #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
  68   #define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
  69 #else
  70   #define LAWBAR0 0
  71   #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
  72 #endif
  73
  74 #define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
  75 #define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
  76
  77 #define LAWBAR2 ((0xe0000000>>12) & 0xfffff)
  78 #define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))
  79
  80         .section .bootpg, "ax"
  81         .globl  law_entry
  82 law_entry:
  83         entry_start
  84         .long 0x03
  85         .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
  86         entry_end
  87
  88 /* TLB1 entries configuration: */
  89
  90         .section        .bootpg, "ax"
  91         .globl          tlb1_entry
  92
  93 tlb1_entry:
  94         entry_start
  95
  96         .long 0x08      /* the following data table uses a few of 16 TLB entries */
  97
  98 /* TLB for CCSRBAR (IMMR) */
  99
 100         .long TLB1_MAS0(1,1,0)
 101         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
 102         .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 103         .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 104
 105 /* TLB for Local Bus stuff, just map the whole 512M */
 106 /* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
 107
 108         .long TLB1_MAS0(1,2,0)
 109         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 110         .long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 111         .long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 112
 113         .long TLB1_MAS0(1,3,0)
 114         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 115         .long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0)
 116         .long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
 117
 118 #if !defined(CONFIG_SPD_EEPROM)
 119         .long TLB1_MAS0(1,4,0)
 120         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 121         .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
 122         .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 123
 124         .long TLB1_MAS0(1,5,0)
 125         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 126         .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
 127         .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 128 #else
 129         .long TLB1_MAS0(1,4,0)
 130         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
 131         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
 132         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
 133
 134         .long TLB1_MAS0(1,5,0)
 135         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
 136         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
 137         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
 138 #endif
 139
 140         .long TLB1_MAS0(1,6,0)
 141         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
 142 #ifdef CONFIG_L2_INIT_RAM
 143         .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
 144 #else
 145         .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
 146 #endif
 147         .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 148
 149         .long TLB1_MAS0(1,7,0)
 150         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 151         .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 152         .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 153
 154 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
 155         .long TLB1_MAS0(1,15,0)
 156         .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
 157         .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
 158         .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
 159 #else
 160         .long TLB1_MAS0(1,15,0)
 161         .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
 162         .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
 163         .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
 164 #endif
 165         entry_end