board/trizepsiv/conxs.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefano Babic, DENX Gmbh, sbabic@denx.de
   4  *
   5  * (C) Copyright 2004
   6  * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
   7  *
   8  * (C) Copyright 2002
   9  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10  *
  11  * (C) Copyright 2002
  12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13  * Marius Groeger <mgroeger@sysgo.de>
  14  *
  15  * SPDX-License-Identifier:     GPL-2.0+
  16  */
  17
  18 #include <common.h>
  19 #include <asm/arch/pxa-regs.h>
  20 #include <asm/arch/pxa.h>
  21 #include <asm/arch/regs-mmc.h>
  22 #include <netdev.h>
  23 #include <asm/io.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #define         RH_A_PSM        (1 << 8)        /* power switching mode */
  28 #define         RH_A_NPS        (1 << 9)        /* no power switching */
  29
  30 extern struct serial_device serial_ffuart_device;
  31 extern struct serial_device serial_btuart_device;
  32 extern struct serial_device serial_stuart_device;
  33
  34 #if CONFIG_MK_POLARIS
  35 #define BOOT_CONSOLE    "serial_stuart"
  36 #else
  37 #define BOOT_CONSOLE    "serial_ffuart"
  38 #endif
  39 /* ------------------------------------------------------------------------- */
  40
  41 /*
  42  * Miscelaneous platform dependent initialisations
  43  */
  44
  45 int usb_board_init(void)
  46 {
  47         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  48                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  49                 UHCHR);
  50
  51         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  52
  53         while (readl(UHCHR) & UHCHR_FSBIR)
  54                 ;
  55
  56         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  57         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  58
  59         /* Clear any OTG Pin Hold */
  60         if (readl(PSSR) & PSSR_OTGPH)
  61                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  62
  63         writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
  64         writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
  65
  66         /* Set port power control mask bits, only 3 ports. */
  67         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  68
  69         return 0;
  70 }
  71
  72 void usb_board_init_fail(void)
  73 {
  74         return;
  75 }
  76
  77 void usb_board_stop(void)
  78 {
  79         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
  80         udelay(11);
  81         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
  82
  83         writel(readl(UHCCOMS) | 1, UHCCOMS);
  84         udelay(10);
  85
  86         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
  87
  88         return;
  89 }
  90
  91 int board_init (void)
  92 {
  93         /* We have RAM, disable cache */
  94         dcache_disable();
  95         icache_disable();
  96
  97         /* arch number of ConXS Board */
  98         gd->bd->bi_arch_number = 776;
  99
 100         /* adress of boot parameters */
 101         gd->bd->bi_boot_params = 0xa000003c;
 102
 103         return 0;
 104 }
 105
 106 int board_late_init(void)
 107 {
 108         char *console=getenv("boot_console");
 109
 110         if ((console == NULL) || (strcmp(console,"serial_btuart") &&
 111                 strcmp(console,"serial_stuart") &&
 112                 strcmp(console,"serial_ffuart"))) {
 113                         console = BOOT_CONSOLE;
 114         }
 115         setenv("stdout",console);
 116         setenv("stdin", console);
 117         setenv("stderr",console);
 118         return 0;
 119 }
 120
 121 int dram_init(void)
 122 {
 123         pxa2xx_dram_init();
 124         gd->ram_size = PHYS_SDRAM_1_SIZE;
 125         return 0;
 126 }
 127
 128 void dram_init_banksize(void)
 129 {
 130         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 131         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 132 }
 133
 134 #ifdef CONFIG_DRIVER_DM9000
 135 int board_eth_init(bd_t *bis)
 136 {
 137         return dm9000_initialize(bis);
 138 }
 139 #endif
 140
 141 #ifdef CONFIG_CMD_MMC
 142 int board_mmc_init(bd_t *bis)
 143 {
 144         pxa_mmc_register(0);
 145         return 0;
 146 }
 147 #endif