2 * U-boot - traps.c Routines related to interrupts and exceptions
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * This file is based on
7 * No original Copyright holder listed,
8 * Probabily original (C) Roman Zippel (assigned DJD, 1999)
10 * Copyright 2003 Metrowerks - for Blackfin
11 * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
12 * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
14 * (C) Copyright 2000-2004
15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
17 * Licensed under the GPL-2 or later.
21 #include <linux/types.h>
22 #include <asm/traps.h>
25 #include <asm/mach-common/bits/core.h>
26 #include <asm/mach-common/bits/mpu.h>
27 #include <asm/mach-common/bits/trace.h>
30 #define trace_buffer_save(x) \
32 (x) = bfin_read_TBUFCTL(); \
33 bfin_write_TBUFCTL((x) & ~TBUFEN); \
36 #define trace_buffer_restore(x) \
37 bfin_write_TBUFCTL((x))
39 /* The purpose of this map is to provide a mapping of address<->cplb settings
40 * rather than an exact map of what is actually addressable on the part. This
41 * map covers all current Blackfin parts. If you try to access an address that
42 * is in this map but not actually on the part, you won't get an exception and
43 * reboot, you'll get an external hardware addressing error and reboot. Since
44 * only the ends matter (you did something wrong and the board reset), the means
45 * are largely irrelevant.
49 uint32_t data_flags, inst_flags;
51 const struct memory_map const bfin_memory_map[] = {
52 { /* external memory */
55 .data_flags = SDRAM_DGENERIC,
56 .inst_flags = SDRAM_IGENERIC,
61 .data_flags = SDRAM_EBIU,
62 .inst_flags = SDRAM_INON_CHBL,
64 { /* everything on chip */
67 .data_flags = L1_DMEMORY,
68 .inst_flags = L1_IMEMORY,
72 void trap_c(struct pt_regs *regs)
74 uint32_t trapnr = (regs->seqstat & EXCAUSE);
78 /* 0x26 - Data CPLB Miss */
81 if (ANOMALY_05000261) {
82 static uint32_t last_cplb_fault_retx;
84 * Work around an anomaly: if we see a new DCPLB fault,
85 * return without doing anything. Then,
86 * if we get the same fault again, handle it.
88 if (last_cplb_fault_retx != regs->retx) {
89 last_cplb_fault_retx = regs->retx;
97 /* 0x27 - Instruction CPLB Miss */
99 volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
100 uint32_t new_cplb_addr = 0, new_cplb_data = 0;
101 static size_t last_evicted;
103 unsigned long tflags;
106 * Keep the trace buffer so that a miss here points people
107 * to the right place (their code). Crashes here rarely
108 * happen. If they do, only the Blackfin maintainer cares.
110 trace_buffer_save(tflags);
112 new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
114 for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
115 /* if the exception is inside this range, lets use it */
116 if (new_cplb_addr >= bfin_memory_map[i].start &&
117 new_cplb_addr < bfin_memory_map[i].end)
120 if (i == ARRAY_SIZE(bfin_memory_map)) {
121 printf("%cCPLB exception outside of memory map at 0x%p\n",
122 (data ? 'D' : 'I'), (void *)new_cplb_addr);
125 debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
126 new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
129 CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
130 CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
132 CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
133 CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
136 /* find the next unlocked entry and evict it */
137 i = last_evicted & 0xF;
138 debug("last evicted = %i\n", i);
139 CPLB_DATA = CPLB_DATA_BASE + i;
140 while (*CPLB_DATA & CPLB_LOCK) {
141 debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
142 i = (i + 1) & 0xF; /* wrap around */
143 CPLB_DATA = CPLB_DATA_BASE + i;
145 CPLB_ADDR = CPLB_ADDR_BASE + i;
147 debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
148 last_evicted = i + 1;
150 /* need to turn off cplbs whenever we muck with the cplb table */
151 #if ENDCPLB != ENICPLB
152 # error cplb enable bit violates my sanity
154 uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
155 bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
156 *CPLB_ADDR = new_cplb_addr;
157 *CPLB_DATA = new_cplb_data;
158 bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
161 /* dump current table for debugging purposes */
162 CPLB_ADDR = CPLB_ADDR_BASE;
163 CPLB_DATA = CPLB_DATA_BASE;
164 for (i = 0; i < 16; ++i)
165 debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
167 trace_buffer_restore(tflags);
172 /* All traps come here */
177 #ifdef CONFIG_DEBUG_DUMP
178 # define ENABLE_DUMP 1
180 # define ENABLE_DUMP 0
183 #ifndef CONFIG_KALLSYMS
184 const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
191 static void decode_address(char *buf, unsigned long address)
193 unsigned long sym_addr;
194 void *paddr = (void *)address;
195 const char *sym = symbol_lookup(address, &sym_addr);
198 sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
203 sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
204 else if (address >= CONFIG_SYS_MONITOR_BASE &&
205 address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
206 sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
208 sprintf(buf, "<0x%p> /* unknown address */", paddr);
211 static char *strhwerrcause(uint16_t hwerrcause)
213 switch (hwerrcause) {
214 case 0x02: return "system mmr error";
215 case 0x03: return "external memory addressing error";
216 case 0x12: return "performance monitor overflow";
217 case 0x18: return "raise 5 instruction";
218 default: return "undef";
222 static char *strexcause(uint16_t excause)
225 case 0x00 ... 0xf: return "custom exception";
226 case 0x10: return "single step";
227 case 0x11: return "trace buffer full";
228 case 0x21: return "undef inst";
229 case 0x22: return "illegal inst";
230 case 0x23: return "dcplb prot violation";
231 case 0x24: return "misaligned data";
232 case 0x25: return "unrecoverable event";
233 case 0x26: return "dcplb miss";
234 case 0x27: return "multiple dcplb hit";
235 case 0x28: return "emulation watchpoint";
236 case 0x2a: return "misaligned inst";
237 case 0x2b: return "icplb prot violation";
238 case 0x2c: return "icplb miss";
239 case 0x2d: return "multiple icplb hit";
240 case 0x2e: return "illegal use of supervisor resource";
241 default: return "undef";
245 void dump(struct pt_regs *fp)
249 uint16_t hwerrcause, excause;
254 /* fp->ipend is garbage, so load it ourself */
255 fp->ipend = bfin_read_IPEND();
257 hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
258 excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
260 printf("SEQUENCER STATUS:\n");
261 printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
262 fp->seqstat, fp->ipend, fp->syscfg);
263 printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
264 printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause));
265 for (i = 6; i <= 15; ++i) {
266 if (fp->ipend & (1 << i)) {
267 decode_address(buf, bfin_read32(EVT0 + 4*i));
268 printf(" physical IVG%i asserted : %s\n", i, buf);
271 decode_address(buf, fp->rete);
272 printf(" RETE: %s\n", buf);
273 decode_address(buf, fp->retn);
274 printf(" RETN: %s\n", buf);
275 decode_address(buf, fp->retx);
276 printf(" RETX: %s\n", buf);
277 decode_address(buf, fp->rets);
278 printf(" RETS: %s\n", buf);
279 /* we lie and store RETI in "pc" */
280 decode_address(buf, fp->pc);
281 printf(" RETI: %s\n", buf);
283 if (fp->seqstat & EXCAUSE) {
284 decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
285 printf("DCPLB_FAULT_ADDR: %s\n", buf);
286 decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
287 printf("ICPLB_FAULT_ADDR: %s\n", buf);
290 printf("\nPROCESSOR STATE:\n");
291 printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
292 fp->r0, fp->r1, fp->r2, fp->r3);
293 printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
294 fp->r4, fp->r5, fp->r6, fp->r7);
295 printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
296 fp->p0, fp->p1, fp->p2, fp->p3);
297 printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
298 fp->p4, fp->p5, fp->fp, (unsigned long)fp);
299 printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
300 fp->lb0, fp->lt0, fp->lc0);
301 printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
302 fp->lb1, fp->lt1, fp->lc1);
303 printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
304 fp->b0, fp->l0, fp->m0, fp->i0);
305 printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
306 fp->b1, fp->l1, fp->m1, fp->i1);
307 printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
308 fp->b2, fp->l2, fp->m2, fp->i2);
309 printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
310 fp->b3, fp->l3, fp->m3, fp->i3);
311 printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
312 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
314 printf("USP : %08lx ASTAT: %08lx\n",
320 void dump_bfin_trace_buffer(void)
323 unsigned long tflags;
329 trace_buffer_save(tflags);
331 printf("Hardware Trace:\n");
333 if (bfin_read_TBUFSTAT() & TBUFCNT) {
334 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
335 decode_address(buf, bfin_read_TBUF());
336 printf("%4i Target : %s\n", i, buf);
337 decode_address(buf, bfin_read_TBUF());
338 printf(" Source : %s\n", buf);
342 trace_buffer_restore(tflags);
345 void bfin_panic(struct pt_regs *regs)
348 unsigned long tflags;
349 trace_buffer_save(tflags);
356 "Ack! Something bad happened to the Blackfin!\n"
360 dump_bfin_trace_buffer();
362 bfin_reset_or_hang();