2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/cache.h>
33 #if defined(CONFIG_OF_FLAT_TREE)
41 uint lcrr; /* local bus clock ratio register */
42 uint clkdiv; /* clock divider portion of lcrr */
77 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
87 case PVR_FAM(PVR_85xx):
94 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
96 get_sys_info(&sysinfo);
98 puts("Clock Configuration:\n");
99 printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
100 printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
101 printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
103 #if defined(CFG_LBC_LCRR)
107 volatile immap_t *immap = (immap_t *)CFG_IMMR;
108 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
113 clkdiv = lcrr & 0x0f;
114 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
115 #ifdef CONFIG_MPC8548
117 * Yes, the entire PQ38 family use the same
118 * bit-representation for twice the clock divider values.
122 printf("LBC:%4lu MHz\n",
123 sysinfo.freqSystemBus / 1000000 / clkdiv);
125 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
128 if (ver == SVR_8560) {
129 printf("CPM: %lu Mhz\n",
130 sysinfo.freqSystemBus / 1000000);
133 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
139 /* ------------------------------------------------------------------------- */
141 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
148 /* e500 v2 core has reset control register */
149 volatile unsigned int * rstcr;
150 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
151 *rstcr = 0x2; /* HRESET_REQ */
154 * Initiate hard reset in debug control register DBCR0
155 * Make sure MSR[DE] = 1
167 * Get timebase clock frequency
169 unsigned long get_tbclk (void)
174 get_sys_info(&sys_info);
175 return ((sys_info.freqSystemBus + 7L) / 8L);
179 #if defined(CONFIG_WATCHDOG)
183 int re_enable = disable_interrupts();
184 reset_85xx_watchdog();
185 if (re_enable) enable_interrupts();
189 reset_85xx_watchdog(void)
192 * Clear TSR(WIS) bit by writing 1
199 #endif /* CONFIG_WATCHDOG */
201 #if defined(CONFIG_DDR_ECC)
202 void dma_init(void) {
203 volatile immap_t *immap = (immap_t *)CFG_IMMR;
204 volatile ccsr_dma_t *dma = &immap->im_dma;
206 dma->satr0 = 0x02c40000;
207 dma->datr0 = 0x02c40000;
208 asm("sync; isync; msync");
212 uint dma_check(void) {
213 volatile immap_t *immap = (immap_t *)CFG_IMMR;
214 volatile ccsr_dma_t *dma = &immap->im_dma;
215 volatile uint status = dma->sr0;
217 /* While the channel is busy, spin */
218 while((status & 4) == 4) {
223 printf ("DMA Error: status = %x\n", status);
228 int dma_xfer(void *dest, uint count, void *src) {
229 volatile immap_t *immap = (immap_t *)CFG_IMMR;
230 volatile ccsr_dma_t *dma = &immap->im_dma;
232 dma->dar0 = (uint) dest;
233 dma->sar0 = (uint) src;
235 dma->mr0 = 0xf000004;
236 asm("sync;isync;msync");
237 dma->mr0 = 0xf000005;
238 asm("sync;isync;msync");
244 #ifdef CONFIG_OF_FLAT_TREE
246 ft_cpu_setup(void *blob, bd_t *bd)
252 clock = bd->bi_busfreq;
253 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
255 *p = cpu_to_be32(clock);
257 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
259 *p = cpu_to_be32(clock);
261 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
263 *p = cpu_to_be32(clock);
265 #if defined(CONFIG_MPC85XX_TSEC1)
266 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
267 memcpy(p, bd->bi_enetaddr, 6);
270 #if defined(CONFIG_HAS_ETH1)
271 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
272 memcpy(p, bd->bi_enet1addr, 6);
275 #if defined(CONFIG_HAS_ETH2)
276 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
277 memcpy(p, bd->bi_enet2addr, 6);
280 #if defined(CONFIG_HAS_ETH3)
281 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
282 memcpy(p, bd->bi_enet3addr, 6);