cpu/mpc8xxx/ddr/ctrl_regs.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <asm/fsl_ddr_sdram.h>
  17
  18 #include "ddr.h"
  19
  20 extern unsigned int picos_to_mclk(unsigned int picos);
  21 /*
  22  * Determine Rtt value.
  23  *
  24  * This should likely be either board or controller specific.
  25  *
  26  * Rtt(nominal):
  27  *      0 = Rtt disabled
  28  *      1 = 75 ohm
  29  *      2 = 150 ohm
  30  *      3 = 50 ohm
  31  *
  32  * FIXME: Apparently 8641 needs a value of 2
  33  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  34  *
  35  * FIXME: There was some effort down this line earlier:
  36  *
  37  *      unsigned int i;
  38  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  39  *              if (popts->dimmslot[i].num_valid_cs
  40  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  41  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  42  *                      rtt = 2;
  43  *                      break;
  44  *              }
  45  *      }
  46  */
  47 static inline int fsl_ddr_get_rtt(void)
  48 {
  49         int rtt;
  50
  51 #if defined(CONFIG_FSL_DDR1)
  52         rtt = 0;
  53 #elif defined(CONFIG_FSL_DDR2)
  54         rtt = 3;
  55 #else
  56 #error "Need Rtt value for DDR3"
  57 #endif
  58
  59         return rtt;
  60 }
  61
  62 /* Chip Select Configuration (CSn_CONFIG) */
  63 static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
  64                                const memctl_options_t *popts,
  65                                const dimm_params_t *dimm_params)
  66 {
  67         unsigned int cs_n_en = 0; /* Chip Select enable */
  68         unsigned int intlv_en = 0; /* Memory controller interleave enable */
  69         unsigned int intlv_ctl = 0; /* Interleaving control */
  70         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
  71         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
  72         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
  73         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
  74         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
  75         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
  76
  77         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
  78         if ((((i&1) == 0)
  79             && (dimm_params[i/2].n_ranks == 1))
  80             || (dimm_params[i/2].n_ranks == 2)) {
  81                 unsigned int n_banks_per_sdram_device;
  82                 cs_n_en = 1;
  83                 if (i == 0) {
  84                         /* These fields only available in CS0_CONFIG */
  85                         intlv_en = popts->memctl_interleaving;
  86                         intlv_ctl = popts->memctl_interleaving_mode;
  87                 }
  88                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
  89                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
  90                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
  91                 n_banks_per_sdram_device
  92                         = dimm_params[i/2].n_banks_per_sdram_device;
  93                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
  94                 row_bits_cs_n = dimm_params[i/2].n_row_addr - 12;
  95                 col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
  96         }
  97
  98         ddr->cs[i].config = (0
  99                 | ((cs_n_en & 0x1) << 31)
 100                 | ((intlv_en & 0x3) << 29)
 101                 | ((intlv_ctl & 0xf) << 24)
 102                 | ((ap_n_en & 0x1) << 23)
 103
 104                 /* XXX: some implementation only have 1 bit starting at left */
 105                 | ((odt_rd_cfg & 0x7) << 20)
 106
 107                 /* XXX: Some implementation only have 1 bit starting at left */
 108                 | ((odt_wr_cfg & 0x7) << 16)
 109
 110                 | ((ba_bits_cs_n & 0x3) << 14)
 111                 | ((row_bits_cs_n & 0x7) << 8)
 112                 | ((col_bits_cs_n & 0x7) << 0)
 113                 );
 114         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 115 }
 116
 117 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 118 /* FIXME: 8572 */
 119 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 120 {
 121         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 122
 123         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 124         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 125 }
 126
 127 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 128
 129 #if defined(CONFIG_FSL_DDR2)
 130 /*
 131  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 132  *
 133  * Avoid writing for DDR I.  The new PQ38 DDR controller
 134  * dreams up non-zero default values to be backwards compatible.
 135  */
 136 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 137 {
 138         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 139         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 140         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 141         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 142         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 143
 144         /* Active powerdown exit timing (tXARD and tXARDS). */
 145         unsigned char act_pd_exit_mclk;
 146         /* Precharge powerdown exit timing (tXP). */
 147         unsigned char pre_pd_exit_mclk;
 148         /* Precharge powerdown exit timing (tAXPD). */
 149         unsigned char taxpd_mclk;
 150         /* Mode register set cycle time (tMRD). */
 151         unsigned char tmrd_mclk;
 152
 153         /* (tXARD and tXARDS). Empirical? */
 154         act_pd_exit_mclk = 2;
 155
 156         /* XXX:  tXARD = 2, tXARDS = 7 - AL. * Empirical? */
 157         pre_pd_exit_mclk = 6;
 158
 159         /* FIXME:  tXP = 2 on Micron 667 MHz DIMM */
 160         taxpd_mclk = 8;
 161
 162         tmrd_mclk = 2;
 163
 164         ddr->timing_cfg_0 = (0
 165                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 166                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 167                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 168                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 169                 | ((act_pd_exit_mclk & 0x7) << 20)  /* ACT_PD_EXIT */
 170                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 171                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 172                 | ((tmrd_mclk & 0xf) << 0)      /* MRS_CYC */
 173                 );
 174         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 175 }
 176 #endif  /* defined(CONFIG_FSL_DDR2) */
 177
 178 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 179 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 180                                const common_timing_params_t *common_dimm)
 181 {
 182         /* Extended Activate to precharge interval (tRAS) */
 183         unsigned int ext_acttopre = 0;
 184         unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
 185         unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
 186         unsigned int cntl_adj = 0; /* Control Adjust */
 187
 188         /* If the tRAS > 19 MCLK, we use the ext mode */
 189         if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
 190                 ext_acttopre = 1;
 191
 192         ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
 193         ddr->timing_cfg_3 = (0
 194                 | ((ext_acttopre & 0x1) << 24)
 195                 | ((ext_refrec & 0xF) << 16)
 196                 | ((ext_caslat & 0x1) << 12)
 197                 | ((cntl_adj & 0x7) << 0)
 198                 );
 199         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 200 }
 201
 202 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 203 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 204                                const common_timing_params_t *common_dimm,
 205                                unsigned int cas_latency)
 206 {
 207         /* Precharge-to-activate interval (tRP) */
 208         unsigned char pretoact_mclk;
 209         /* Activate to precharge interval (tRAS) */
 210         unsigned char acttopre_mclk;
 211         /*  Activate to read/write interval (tRCD) */
 212         unsigned char acttorw_mclk;
 213         /* CASLAT */
 214         unsigned char caslat_ctrl;
 215         /*  Refresh recovery time (tRFC) ; trfc_low */
 216         unsigned char refrec_ctrl;
 217         /* Last data to precharge minimum interval (tWR) */
 218         unsigned char wrrec_mclk;
 219         /* Activate-to-activate interval (tRRD) */
 220         unsigned char acttoact_mclk;
 221         /* Last write data pair to read command issue interval (tWTR) */
 222         unsigned char wrtord_mclk;
 223
 224         pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
 225         acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
 226         acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
 227
 228         /*
 229          * Translate CAS Latency to a DDR controller field value:
 230          *
 231          *      CAS Lat DDR I   DDR II  Ctrl
 232          *      Clocks  SPD Bit SPD Bit Value
 233          *      ------- ------- ------- -----
 234          *      1.0     0               0001
 235          *      1.5     1               0010
 236          *      2.0     2       2       0011
 237          *      2.5     3               0100
 238          *      3.0     4       3       0101
 239          *      3.5     5               0110
 240          *      4.0             4       0111
 241          *      4.5                     1000
 242          *      5.0             5       1001
 243          */
 244 #if defined(CONFIG_FSL_DDR1)
 245         caslat_ctrl = (cas_latency + 1) & 0x07;
 246 #elif defined(CONFIG_FSL_DDR2)
 247         caslat_ctrl = 2 * cas_latency - 1;
 248 #else
 249 #error "Need CAS Latency help for DDR3 in fsl_ddr_sdram.c"
 250 #endif
 251
 252         refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
 253         wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
 254         acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
 255         wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
 256
 257         ddr->timing_cfg_1 = (0
 258                 | ((pretoact_mclk & 0x0F) << 28)
 259                 | ((acttopre_mclk & 0x0F) << 24)
 260                 | ((acttorw_mclk & 0xF) << 20)
 261                 | ((caslat_ctrl & 0xF) << 16)
 262                 | ((refrec_ctrl & 0xF) << 12)
 263                 | ((wrrec_mclk & 0x0F) << 8)
 264                 | ((acttoact_mclk & 0x07) << 4)
 265                 | ((wrtord_mclk & 0x07) << 0)
 266                 );
 267         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 268 }
 269
 270 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 271 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 272                                const memctl_options_t *popts,
 273                                const common_timing_params_t *common_dimm,
 274                                unsigned int cas_latency,
 275                                unsigned int additive_latency)
 276 {
 277         /* Additive latency */
 278         unsigned char add_lat_mclk;
 279         /* CAS-to-preamble override */
 280         unsigned short cpo;
 281         /* Write latency */
 282         unsigned char wr_lat;
 283         /*  Read to precharge (tRTP) */
 284         unsigned char rd_to_pre;
 285         /* Write command to write data strobe timing adjustment */
 286         unsigned char wr_data_delay;
 287         /* Minimum CKE pulse width (tCKE) */
 288         unsigned char cke_pls;
 289         /* Window for four activates (tFAW) */
 290         unsigned short four_act;
 291
 292         /* FIXME add check that this must be less than acttorw_mclk */
 293         add_lat_mclk = additive_latency;
 294         cpo = popts->cpo_override;
 295
 296 #if defined(CONFIG_FSL_DDR1)
 297         /*
 298          * This is a lie.  It should really be 1, but if it is
 299          * set to 1, bits overlap into the old controller's
 300          * otherwise unused ACSM field.  If we leave it 0, then
 301          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 302          */
 303         wr_lat = 0;
 304 #elif defined(CONFIG_FSL_DDR2)
 305         wr_lat = cas_latency + additive_latency - 1;
 306 #else
 307 #error "Fix WR_LAT for DDR3"
 308 #endif
 309
 310         rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
 311         wr_data_delay = popts->write_data_delay;
 312         cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
 313         four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
 314
 315         ddr->timing_cfg_2 = (0
 316                 | ((add_lat_mclk & 0xf) << 28)
 317                 | ((cpo & 0x1f) << 23)
 318                 | ((wr_lat & 0xf) << 19)
 319                 | ((rd_to_pre & 0x7) << 13)
 320                 | ((wr_data_delay & 0x7) << 10)
 321                 | ((cke_pls & 0x7) << 6)
 322                 | ((four_act & 0x3f) << 0)
 323                 );
 324         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 325 }
 326
 327 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 328 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 329                                const memctl_options_t *popts,
 330                                const common_timing_params_t *common_dimm)
 331 {
 332         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 333         unsigned int sren;              /* Self refresh enable (during sleep) */
 334         unsigned int ecc_en;            /* ECC enable. */
 335         unsigned int rd_en;             /* Registered DIMM enable */
 336         unsigned int sdram_type;        /* Type of SDRAM */
 337         unsigned int dyn_pwr;           /* Dynamic power management mode */
 338         unsigned int dbw;               /* DRAM dta bus width */
 339         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 340         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 341         unsigned int threeT_en;         /* Enable 3T timing */
 342         unsigned int twoT_en;           /* Enable 2T timing */
 343         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 344         unsigned int x32_en = 0;        /* x32 enable */
 345         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 346         unsigned int hse;               /* Global half strength override */
 347         unsigned int mem_halt = 0;      /* memory controller halt */
 348         unsigned int bi = 0;            /* Bypass initialization */
 349
 350         mem_en = 1;
 351         sren = popts->self_refresh_in_sleep;
 352         if (common_dimm->all_DIMMs_ECC_capable) {
 353                 /* Allow setting of ECC only if all DIMMs are ECC. */
 354                 ecc_en = popts->ECC_mode;
 355         } else {
 356                 ecc_en = 0;
 357         }
 358
 359         rd_en = (common_dimm->all_DIMMs_registered
 360                  && !common_dimm->all_DIMMs_unbuffered);
 361
 362         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 363
 364         dyn_pwr = popts->dynamic_power;
 365         dbw = popts->data_bus_width;
 366         /* DDR3 must use 8-beat bursts when using 32-bit bus mode */
 367         if ((sdram_type == SDRAM_TYPE_DDR3) && (dbw == 0x1))
 368                 eight_be = 1;
 369         threeT_en = popts->threeT_en;
 370         twoT_en = popts->twoT_en;
 371         ba_intlv_ctl = popts->ba_intlv_ctl;
 372         hse = popts->half_strength_driver_enable;
 373
 374         ddr->ddr_sdram_cfg = (0
 375                         | ((mem_en & 0x1) << 31)
 376                         | ((sren & 0x1) << 30)
 377                         | ((ecc_en & 0x1) << 29)
 378                         | ((rd_en & 0x1) << 28)
 379                         | ((sdram_type & 0x7) << 24)
 380                         | ((dyn_pwr & 0x1) << 21)
 381                         | ((dbw & 0x3) << 19)
 382                         | ((eight_be & 0x1) << 18)
 383                         | ((ncap & 0x1) << 17)
 384                         | ((threeT_en & 0x1) << 16)
 385                         | ((twoT_en & 0x1) << 15)
 386                         | ((ba_intlv_ctl & 0x7F) << 8)
 387                         | ((x32_en & 0x1) << 5)
 388                         | ((pchb8 & 0x1) << 4)
 389                         | ((hse & 0x1) << 3)
 390                         | ((mem_halt & 0x1) << 1)
 391                         | ((bi & 0x1) << 0)
 392                         );
 393         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 394 }
 395
 396 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 397 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 398                                const memctl_options_t *popts)
 399 {
 400         unsigned int frc_sr = 0;        /* Force self refresh */
 401         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 402         unsigned int dll_rst_dis;       /* DLL reset disable */
 403         unsigned int dqs_cfg;           /* DQS configuration */
 404         unsigned int odt_cfg;           /* ODT configuration */
 405         unsigned int num_pr;            /* Number of posted refreshes */
 406         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 407         unsigned int ap_en;             /* Address Parity Enable */
 408         unsigned int d_init;            /* DRAM data initialization */
 409         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 410         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 411
 412         dll_rst_dis = 1;        /* Make this configurable */
 413         dqs_cfg = popts->DQS_config;
 414         if (popts->cs_local_opts[0].odt_rd_cfg
 415             || popts->cs_local_opts[0].odt_wr_cfg) {
 416                 /* FIXME */
 417                 odt_cfg = 2;
 418         } else {
 419                 odt_cfg = 0;
 420         }
 421
 422         num_pr = 1;     /* Make this configurable */
 423
 424         /*
 425          * 8572 manual says
 426          *     {TIMING_CFG_1[PRETOACT]
 427          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 428          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 429          *      << DDR_SDRAM_INTERVAL[REFINT]
 430          */
 431
 432         obc_cfg = 0;    /* Make this configurable? */
 433         ap_en = 0;      /* Make this configurable? */
 434
 435 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 436         /* Use the DDR controller to auto initialize memory. */
 437         d_init = 1;
 438         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 439         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 440 #else
 441         /* Memory will be initialized via DMA, or not at all. */
 442         d_init = 0;
 443 #endif
 444
 445         ddr->ddr_sdram_cfg_2 = (0
 446                 | ((frc_sr & 0x1) << 31)
 447                 | ((sr_ie & 0x1) << 30)
 448                 | ((dll_rst_dis & 0x1) << 29)
 449                 | ((dqs_cfg & 0x3) << 26)
 450                 | ((odt_cfg & 0x3) << 21)
 451                 | ((num_pr & 0xf) << 12)
 452                 | ((obc_cfg & 0x1) << 6)
 453                 | ((ap_en & 0x1) << 5)
 454                 | ((d_init & 0x1) << 4)
 455                 | ((rcw_en & 0x1) << 2)
 456                 | ((md_en & 0x1) << 0)
 457                 );
 458         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 459 }
 460
 461 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 462 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
 463 {
 464         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 465         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 466
 467         ddr->ddr_sdram_mode_2 = (0
 468                                  | ((esdmode2 & 0xFFFF) << 16)
 469                                  | ((esdmode3 & 0xFFFF) << 0)
 470                                  );
 471         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 472 }
 473
 474 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
 475 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 476                                const memctl_options_t *popts,
 477                                const common_timing_params_t *common_dimm)
 478 {
 479         unsigned int refint;    /* Refresh interval */
 480         unsigned int bstopre;   /* Precharge interval */
 481
 482         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
 483
 484         bstopre = popts->bstopre;
 485
 486         /* refint field used 0x3FFF in earlier controllers */
 487         ddr->ddr_sdram_interval = (0
 488                                    | ((refint & 0xFFFF) << 16)
 489                                    | ((bstopre & 0x3FFF) << 0)
 490                                    );
 491         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
 492 }
 493
 494 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
 495 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 496                                const memctl_options_t *popts,
 497                                const common_timing_params_t *common_dimm,
 498                                unsigned int cas_latency,
 499                                unsigned int additive_latency)
 500 {
 501         unsigned short esdmode;         /* Extended SDRAM mode */
 502         unsigned short sdmode;          /* SDRAM mode */
 503
 504         /*
 505          * FIXME: This ought to be pre-calculated in a
 506          * technology-specific routine,
 507          * e.g. compute_DDR2_mode_register(), and then the
 508          * sdmode and esdmode passed in as part of common_dimm.
 509          */
 510
 511         /* Extended Mode Register */
 512         unsigned int mrs = 0;           /* Mode Register Set */
 513         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
 514         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
 515         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
 516         unsigned int ocd = 0;           /* 0x0=OCD not supported,
 517                                            0x7=OCD default state */
 518         unsigned int rtt;
 519         unsigned int al;                /* Posted CAS# additive latency (AL) */
 520         unsigned int ods = 0;           /* Output Drive Strength:
 521                                                 0 = Full strength (18ohm)
 522                                                 1 = Reduced strength (4ohm) */
 523         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
 524                                                        1=Disable (Test/Debug) */
 525
 526         /* Mode Register (MR) */
 527         unsigned int mr;        /* Mode Register Definition */
 528         unsigned int pd;        /* Power-Down Mode */
 529         unsigned int wr;        /* Write Recovery */
 530         unsigned int dll_res;   /* DLL Reset */
 531         unsigned int mode;      /* Normal=0 or Test=1 */
 532         unsigned int caslat = 0;/* CAS# latency */
 533         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
 534         unsigned int bt;
 535         unsigned int bl;        /* BL: Burst Length */
 536
 537 #if defined(CONFIG_FSL_DDR2)
 538         const unsigned int mclk_ps = get_memory_clk_period_ps();
 539 #endif
 540
 541         rtt = fsl_ddr_get_rtt();
 542
 543         al = additive_latency;
 544
 545         esdmode = (0
 546                 | ((mrs & 0x3) << 14)
 547                 | ((outputs & 0x1) << 12)
 548                 | ((rdqs_en & 0x1) << 11)
 549                 | ((dqs_en & 0x1) << 10)
 550                 | ((ocd & 0x7) << 7)
 551                 | ((rtt & 0x2) << 5)   /* rtt field is split */
 552                 | ((al & 0x7) << 3)
 553                 | ((rtt & 0x1) << 2)   /* rtt field is split */
 554                 | ((ods & 0x1) << 1)
 555                 | ((dll_en & 0x1) << 0)
 556                 );
 557
 558         mr = 0;          /* FIXME: CHECKME */
 559
 560         /*
 561          * 0 = Fast Exit (Normal)
 562          * 1 = Slow Exit (Low Power)
 563          */
 564         pd = 0;
 565
 566 #if defined(CONFIG_FSL_DDR1)
 567         wr = 0;       /* Historical */
 568 #elif defined(CONFIG_FSL_DDR2)
 569         wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
 570 #else
 571 #error "Write tWR_auto for DDR3"
 572 #endif
 573         dll_res = 0;
 574         mode = 0;
 575
 576 #if defined(CONFIG_FSL_DDR1)
 577         if (1 <= cas_latency && cas_latency <= 4) {
 578                 unsigned char mode_caslat_table[4] = {
 579                         0x5,    /* 1.5 clocks */
 580                         0x2,    /* 2.0 clocks */
 581                         0x6,    /* 2.5 clocks */
 582                         0x3     /* 3.0 clocks */
 583                 };
 584                 caslat = mode_caslat_table[cas_latency - 1];
 585         } else {
 586                 printf("Warning: unknown cas_latency %d\n", cas_latency);
 587         }
 588 #elif defined(CONFIG_FSL_DDR2)
 589         caslat = cas_latency;
 590 #else
 591 #error "Fix the mode CAS Latency for DDR3"
 592 #endif
 593         bt = 0;
 594
 595         switch (popts->burst_length) {
 596         case 4:
 597                 bl = 2;
 598                 break;
 599         case 8:
 600                 bl = 3;
 601                 break;
 602         default:
 603                 printf("Error: invalid burst length of %u specified. "
 604                         " Defaulting to 4 beats.\n",
 605                         popts->burst_length);
 606                 bl = 2;
 607                 break;
 608         }
 609
 610         sdmode = (0
 611                   | ((mr & 0x3) << 14)
 612                   | ((pd & 0x1) << 12)
 613                   | ((wr & 0x7) << 9)
 614                   | ((dll_res & 0x1) << 8)
 615                   | ((mode & 0x1) << 7)
 616                   | ((caslat & 0x7) << 4)
 617                   | ((bt & 0x1) << 3)
 618                   | ((bl & 0x7) << 0)
 619                   );
 620
 621         ddr->ddr_sdram_mode = (0
 622                                | ((esdmode & 0xFFFF) << 16)
 623                                | ((sdmode & 0xFFFF) << 0)
 624                                );
 625         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 626 }
 627
 628
 629 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
 630 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
 631 {
 632         unsigned int init_value;        /* Initialization value */
 633
 634         init_value = 0xDEADBEEF;
 635         ddr->ddr_data_init = init_value;
 636 }
 637
 638 /*
 639  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
 640  * The old controller on the 8540/60 doesn't have this register.
 641  * Hope it's OK to set it (to 0) anyway.
 642  */
 643 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 644                                          const memctl_options_t *popts)
 645 {
 646         unsigned int clk_adjust;        /* Clock adjust */
 647
 648         clk_adjust = popts->clk_adjust;
 649         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
 650 }
 651
 652 /* DDR Initialization Address (DDR_INIT_ADDR) */
 653 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
 654 {
 655         unsigned int init_addr = 0;     /* Initialization address */
 656
 657         ddr->ddr_init_addr = init_addr;
 658 }
 659
 660 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
 661 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
 662 {
 663         unsigned int uia = 0;   /* Use initialization address */
 664         unsigned int init_ext_addr = 0; /* Initialization address */
 665
 666         ddr->ddr_init_ext_addr = (0
 667                                   | ((uia & 0x1) << 31)
 668                                   | (init_ext_addr & 0xF)
 669                                   );
 670 }
 671
 672 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
 673 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
 674 {
 675         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
 676         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
 677         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
 678         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
 679         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 680
 681         ddr->timing_cfg_4 = (0
 682                              | ((rwt & 0xf) << 28)
 683                              | ((wrt & 0xf) << 24)
 684                              | ((rrt & 0xf) << 20)
 685                              | ((wwt & 0xf) << 16)
 686                              | (dll_lock & 0x3)
 687                              );
 688         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
 689 }
 690
 691 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
 692 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
 693 {
 694         unsigned int rodt_on = 0;       /* Read to ODT on */
 695         unsigned int rodt_off = 0;      /* Read to ODT off */
 696         unsigned int wodt_on = 0;       /* Write to ODT on */
 697         unsigned int wodt_off = 0;      /* Write to ODT off */
 698
 699         ddr->timing_cfg_5 = (0
 700                              | ((rodt_on & 0x1f) << 24)
 701                              | ((rodt_off & 0x7) << 20)
 702                              | ((wodt_on & 0x1f) << 12)
 703                              | ((wodt_off & 0x7) << 8)
 704                              );
 705         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
 706 }
 707
 708 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
 709 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr)
 710 {
 711         unsigned int zq_en = 0; /* ZQ Calibration Enable */
 712         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
 713         /* Normal Operation Full Calibration Time (tZQoper) */
 714         unsigned int zqoper = 0;
 715         /* Normal Operation Short Calibration Time (tZQCS) */
 716         unsigned int zqcs = 0;
 717
 718         ddr->ddr_zq_cntl = (0
 719                             | ((zq_en & 0x1) << 31)
 720                             | ((zqinit & 0xF) << 24)
 721                             | ((zqoper & 0xF) << 16)
 722                             | ((zqcs & 0xF) << 8)
 723                             );
 724 }
 725
 726 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
 727 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
 728 {
 729         unsigned int wrlvl_en = 0; /* Write Leveling Enable */
 730         /*
 731          * First DQS pulse rising edge after margining mode
 732          * is programmed (tWL_MRD)
 733          */
 734         unsigned int wrlvl_mrd = 0;
 735         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
 736         unsigned int wrlvl_odten = 0;
 737         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
 738         unsigned int wrlvl_dqsen = 0;
 739         /* WRLVL_SMPL: Write leveling sample time */
 740         unsigned int wrlvl_smpl = 0;
 741         /* WRLVL_WLR: Write leveling repeition time */
 742         unsigned int wrlvl_wlr = 0;
 743         /* WRLVL_START: Write leveling start time */
 744         unsigned int wrlvl_start = 0;
 745
 746         ddr->ddr_wrlvl_cntl = (0
 747                                | ((wrlvl_en & 0x1) << 31)
 748                                | ((wrlvl_mrd & 0x7) << 24)
 749                                | ((wrlvl_odten & 0x7) << 20)
 750                                | ((wrlvl_dqsen & 0x7) << 16)
 751                                | ((wrlvl_smpl & 0xf) << 12)
 752                                | ((wrlvl_wlr & 0x7) << 8)
 753                                | ((wrlvl_start & 0x1F) << 0)
 754                                );
 755 }
 756
 757 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
 758 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
 759 {
 760         /* Self Refresh Idle Threshold */
 761         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
 762 }
 763
 764 /* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */
 765 static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr)
 766 {
 767         /* Termination value during pre-drive conditioning */
 768         unsigned int tvpd = 0;
 769         unsigned int pd_en = 0;         /* Pre-Drive Conditioning Enable */
 770         unsigned int pdar = 0;          /* Pre-Drive After Read */
 771         unsigned int pdaw = 0;          /* Pre-Drive After Write */
 772         unsigned int pd_on = 0;         /* Pre-Drive Conditioning On */
 773         unsigned int pd_off = 0;        /* Pre-Drive Conditioning Off */
 774
 775         ddr->ddr_pd_cntl = (0
 776                             | ((pd_en & 0x1) << 31)
 777                             | ((tvpd & 0x7) << 28)
 778                             | ((pdar & 0x7F) << 20)
 779                             | ((pdaw & 0x7F) << 12)
 780                             | ((pd_on & 0x1F) << 6)
 781                             | ((pd_off & 0x1F) << 0)
 782                             );
 783 }
 784
 785
 786 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
 787 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
 788 {
 789         unsigned int rcw0 = 0;  /* RCW0: Register Control Word 0 */
 790         unsigned int rcw1 = 0;  /* RCW1: Register Control Word 1 */
 791         unsigned int rcw2 = 0;  /* RCW2: Register Control Word 2 */
 792         unsigned int rcw3 = 0;  /* RCW3: Register Control Word 3 */
 793         unsigned int rcw4 = 0;  /* RCW4: Register Control Word 4 */
 794         unsigned int rcw5 = 0;  /* RCW5: Register Control Word 5 */
 795         unsigned int rcw6 = 0;  /* RCW6: Register Control Word 6 */
 796         unsigned int rcw7 = 0;  /* RCW7: Register Control Word 7 */
 797
 798         ddr->ddr_sdram_rcw_1 = (0
 799                                 | ((rcw0 & 0xF) << 28)
 800                                 | ((rcw1 & 0xF) << 24)
 801                                 | ((rcw2 & 0xF) << 20)
 802                                 | ((rcw3 & 0xF) << 16)
 803                                 | ((rcw4 & 0xF) << 12)
 804                                 | ((rcw5 & 0xF) << 8)
 805                                 | ((rcw6 & 0xF) << 4)
 806                                 | ((rcw7 & 0xF) << 0)
 807                                 );
 808 }
 809
 810 /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
 811 static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
 812 {
 813         unsigned int rcw8 = 0;  /* RCW0: Register Control Word 8 */
 814         unsigned int rcw9 = 0;  /* RCW1: Register Control Word 9 */
 815         unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */
 816         unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */
 817         unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */
 818         unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */
 819         unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */
 820         unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */
 821
 822         ddr->ddr_sdram_rcw_2 = (0
 823                                 | ((rcw8 & 0xF) << 28)
 824                                 | ((rcw9 & 0xF) << 24)
 825                                 | ((rcw10 & 0xF) << 20)
 826                                 | ((rcw11 & 0xF) << 16)
 827                                 | ((rcw12 & 0xF) << 12)
 828                                 | ((rcw13 & 0xF) << 8)
 829                                 | ((rcw14 & 0xF) << 4)
 830                                 | ((rcw15 & 0xF) << 0)
 831                                 );
 832 }
 833
 834 unsigned int
 835 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 836 {
 837         unsigned int res = 0;
 838
 839         /*
 840          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
 841          * not set at the same time.
 842          */
 843         if (ddr->ddr_sdram_cfg & 0x10000000
 844             && ddr->ddr_sdram_cfg & 0x00008000) {
 845                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
 846                                 " should not be set at the same time.\n");
 847                 res++;
 848         }
 849
 850         return res;
 851 }
 852
 853 unsigned int
 854 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 855                                fsl_ddr_cfg_regs_t *ddr,
 856                                const common_timing_params_t *common_dimm,
 857                                const dimm_params_t *dimm_params,
 858                                unsigned int dbw_cap_adj)
 859 {
 860         unsigned int i;
 861         unsigned int cas_latency;
 862         unsigned int additive_latency;
 863         unsigned int sr_it;
 864
 865         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
 866
 867         if (common_dimm == NULL) {
 868                 printf("Error: subset DIMM params struct null pointer\n");
 869                 return 1;
 870         }
 871
 872         /*
 873          * Process overrides first.
 874          *
 875          * FIXME: somehow add dereated caslat to this
 876          */
 877         cas_latency = (popts->cas_latency_override)
 878                 ? popts->cas_latency_override_value
 879                 : common_dimm->lowest_common_SPD_caslat;
 880
 881         additive_latency = (popts->additive_latency_override)
 882                 ? popts->additive_latency_override_value
 883                 : common_dimm->additive_latency;
 884
 885         sr_it = (popts->auto_self_refresh_en)
 886                 ? popts->sr_it
 887                 : 0;
 888
 889         /* Chip Select Memory Bounds (CSn_BNDS) */
 890         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 891                 phys_size_t sa = 0;
 892                 phys_size_t ea = 0;
 893
 894                 if (popts->ba_intlv_ctl && (i > 0) &&
 895                         ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
 896                         /* Don't set up boundaries for other CS
 897                          * other than CS0, if bank interleaving
 898                          * is enabled and not CS2+CS3 interleaved.
 899                          */
 900                         break;
 901                 }
 902
 903                 if (dimm_params[i/2].n_ranks == 0) {
 904                         debug("Skipping setup of CS%u "
 905                                 "because n_ranks on DIMM %u is 0\n", i, i/2);
 906                         continue;
 907                 }
 908                 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
 909                         /*
 910                          * This works superbank 2CS
 911                          * There are 2 memory controllers configured
 912                          * identically, memory is interleaved between them,
 913                          * and each controller uses rank interleaving within
 914                          * itself. Therefore the starting and ending address
 915                          * on each controller is twice the amount present on
 916                          * each controller.
 917                          */
 918                         unsigned long long rank_density
 919                                         = dimm_params[0].capacity;
 920                         ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
 921                 }
 922                 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
 923                         /*
 924                          * If memory interleaving between controllers is NOT
 925                          * enabled, the starting address for each memory
 926                          * controller is distinct.  However, because rank
 927                          * interleaving is enabled, the starting and ending
 928                          * addresses of the total memory on that memory
 929                          * controller needs to be programmed into its
 930                          * respective CS0_BNDS.
 931                          */
 932                         unsigned long long rank_density
 933                                                 = dimm_params[i/2].rank_density;
 934                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 935                         case FSL_DDR_CS0_CS1_CS2_CS3:
 936                                 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
 937                                  * needs to be set.
 938                                  */
 939                                 sa = common_dimm->base_address;
 940                                 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
 941                                 break;
 942                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 943                                 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
 944                                  * and CS2_CNDS need to be set.
 945                                  */
 946                                 if (!(i&1)) {
 947                                         sa = dimm_params[i/2].base_address;
 948                                         ea = sa + (i * (rank_density >>
 949                                                 dbw_cap_adj)) - 1;
 950                                 }
 951                                 break;
 952                         case FSL_DDR_CS0_CS1:
 953                                 /* CS0+CS1 interleaving, CS0_CNDS needs
 954                                  * to be set
 955                                  */
 956                                 sa = common_dimm->base_address;
 957                                 ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
 958                                 break;
 959                         case FSL_DDR_CS2_CS3:
 960                                 /* CS2+CS3 interleaving*/
 961                                 if (i == 2) {
 962                                         sa = dimm_params[i/2].base_address;
 963                                         ea = sa + (2 * (rank_density >>
 964                                                 dbw_cap_adj)) - 1;
 965                                 }
 966                                 break;
 967                         default:  /* No bank(chip-select) interleaving */
 968                                 break;
 969                         }
 970                 }
 971                 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
 972                         /*
 973                          * Only the rank on CS0 of each memory controller may
 974                          * be used if memory controller interleaving is used
 975                          * without rank interleaving within each memory
 976                          * controller.  However, the ending address programmed
 977                          * into each CS0 must be the sum of the amount of
 978                          * memory in the two CS0 ranks.
 979                          */
 980                         if (i == 0) {
 981                                 unsigned long long rank_density
 982                                                 = dimm_params[0].rank_density;
 983                                 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
 984                         }
 985
 986                 }
 987                 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
 988                         /*
 989                          * No rank interleaving and no memory controller
 990                          * interleaving.
 991                          */
 992                         unsigned long long rank_density
 993                                                 = dimm_params[i/2].rank_density;
 994                         sa = dimm_params[i/2].base_address;
 995                         ea = sa + (rank_density >> dbw_cap_adj) - 1;
 996                         if (i&1) {
 997                                 if ((dimm_params[i/2].n_ranks == 1)) {
 998                                         /* Odd chip select, single-rank dimm */
 999                                         sa = 0;
1000                                         ea = 0;
1001                                 } else {
1002                                         /* Odd chip select, dual-rank DIMM */
1003                                         sa += rank_density >> dbw_cap_adj;
1004                                         ea += rank_density >> dbw_cap_adj;
1005                                 }
1006                         }
1007                 }
1008
1009                 sa >>= 24;
1010                 ea >>= 24;
1011
1012                 ddr->cs[i].bnds = (0
1013                         | ((sa & 0xFFF) << 16)  /* starting address MSB */
1014                         | ((ea & 0xFFF) << 0)   /* ending address MSB */
1015                         );
1016
1017                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1018                 set_csn_config(i, ddr, popts, dimm_params);
1019                 set_csn_config_2(i, ddr);
1020         }
1021
1022 #if defined(CONFIG_FSL_DDR2)
1023         set_timing_cfg_0(ddr);
1024 #endif
1025
1026         set_timing_cfg_3(ddr, common_dimm);
1027         set_timing_cfg_1(ddr, common_dimm, cas_latency);
1028         set_timing_cfg_2(ddr, popts, common_dimm,
1029                                 cas_latency, additive_latency);
1030
1031         set_ddr_sdram_cfg(ddr, popts, common_dimm);
1032
1033         set_ddr_sdram_cfg_2(ddr, popts);
1034         set_ddr_sdram_mode(ddr, popts, common_dimm,
1035                                 cas_latency, additive_latency);
1036         set_ddr_sdram_mode_2(ddr);
1037         set_ddr_sdram_interval(ddr, popts, common_dimm);
1038         set_ddr_data_init(ddr);
1039         set_ddr_sdram_clk_cntl(ddr, popts);
1040         set_ddr_init_addr(ddr);
1041         set_ddr_init_ext_addr(ddr);
1042         set_timing_cfg_4(ddr);
1043         set_timing_cfg_5(ddr);
1044
1045         set_ddr_zq_cntl(ddr);
1046         set_ddr_wrlvl_cntl(ddr);
1047
1048         set_ddr_pd_cntl(ddr);
1049         set_ddr_sr_cntr(ddr, sr_it);
1050
1051         set_ddr_sdram_rcw_1(ddr);
1052         set_ddr_sdram_rcw_2(ddr);
1053
1054         return check_fsl_memctl_config_regs(ddr);
1055 }