cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_ddr_sdram.h>
  11
  12 #include "ddr.h"
  13
  14 /* Board-specific functions defined in each board's ddr.c */
  15 extern void fsl_ddr_board_options(memctl_options_t *popts,
  16                 dimm_params_t *pdimm,
  17                 unsigned int ctrl_num);
  18
  19 unsigned int populate_memctl_options(int all_DIMMs_registered,
  20                         memctl_options_t *popts,
  21                         dimm_params_t *pdimm,
  22                         unsigned int ctrl_num)
  23 {
  24         unsigned int i;
  25 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
  26         const char *p;
  27 #endif
  28
  29         /* Chip select options. */
  30
  31         /* Pick chip-select local options. */
  32         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  33                 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
  34
  35                 /* only for single CS? */
  36                 popts->cs_local_opts[i].odt_rd_cfg = 0;
  37
  38                 popts->cs_local_opts[i].odt_wr_cfg = 1;
  39                 popts->cs_local_opts[i].auto_precharge = 0;
  40         }
  41
  42         /* Pick interleaving mode. */
  43
  44         /*
  45          * 0 = no interleaving
  46          * 1 = interleaving between 2 controllers
  47          */
  48         popts->memctl_interleaving = 0;
  49
  50         /*
  51          * 0 = cacheline
  52          * 1 = page
  53          * 2 = (logical) bank
  54          * 3 = superbank (only if CS interleaving is enabled)
  55          */
  56         popts->memctl_interleaving_mode = 0;
  57
  58         /*
  59          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
  60          * 1: page:      bit to the left of the column bits selects the memctl
  61          * 2: bank:      bit to the left of the bank bits selects the memctl
  62          * 3: superbank: bit to the left of the chip select selects the memctl
  63          *
  64          * NOTE: ba_intlv (rank interleaving) is independent of memory
  65          * controller interleaving; it is only within a memory controller.
  66          * Must use superbank interleaving if rank interleaving is used and
  67          * memory controller interleaving is enabled.
  68          */
  69
  70         /*
  71          * 0 = no
  72          * 0x40 = CS0,CS1
  73          * 0x20 = CS2,CS3
  74          * 0x60 = CS0,CS1 + CS2,CS3
  75          * 0x04 = CS0,CS1,CS2,CS3
  76          */
  77         popts->ba_intlv_ctl = 0;
  78
  79         /* Memory Organization Parameters */
  80         popts->registered_dimm_en = all_DIMMs_registered;
  81
  82         /* Operational Mode Paramters */
  83
  84         /* Pick ECC modes */
  85 #ifdef CONFIG_DDR_ECC
  86         popts->ECC_mode = 1;              /* 0 = disabled, 1 = enabled */
  87 #else
  88         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
  89 #endif
  90         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
  91
  92         /*
  93          * Choose DQS config
  94          * 0 for DDR1
  95          * 1 for DDR2
  96          */
  97 #if defined(CONFIG_FSL_DDR1)
  98         popts->DQS_config = 0;
  99 #elif defined(CONFIG_FSL_DDR2)
 100         popts->DQS_config = 1;
 101 #else
 102 #error "Fix DQS for DDR3"
 103 #endif
 104
 105         /* Choose self-refresh during sleep. */
 106         popts->self_refresh_in_sleep = 1;
 107
 108         /* Choose dynamic power management mode. */
 109         popts->dynamic_power = 0;
 110
 111         /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
 112         popts->data_bus_width = 0;
 113
 114         /* Choose burst length. */
 115         popts->burst_length = 4;        /* has to be 4 for DDR2 */
 116
 117         /* Global Timing Parameters. */
 118         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 119
 120         /* Pick a caslat override. */
 121         popts->cas_latency_override = 0;
 122         popts->cas_latency_override_value = 3;
 123         if (popts->cas_latency_override) {
 124                 debug("using caslat override value = %u\n",
 125                        popts->cas_latency_override_value);
 126         }
 127
 128         /* Decide whether to use the computed derated latency */
 129         popts->use_derated_caslat = 0;
 130
 131         /* Choose an additive latency. */
 132         popts->additive_latency_override = 0;
 133         popts->additive_latency_override_value = 3;
 134         if (popts->additive_latency_override) {
 135                 debug("using additive latency override value = %u\n",
 136                        popts->additive_latency_override_value);
 137         }
 138
 139         /*
 140          * 2T_EN setting
 141          *
 142          * Factors to consider for 2T_EN:
 143          *      - number of DIMMs installed
 144          *      - number of components, number of active ranks
 145          *      - how much time you want to spend playing around
 146          */
 147         popts->twoT_en = 0;
 148         popts->threeT_en = 0;
 149
 150         /*
 151          * BSTTOPRE precharge interval
 152          *
 153          * Set this to 0 for global auto precharge
 154          *
 155          * FIXME: Should this be configured in picoseconds?
 156          * Why it should be in ps:  better understanding of this
 157          * relative to actual DRAM timing parameters such as tRAS.
 158          * e.g. tRAS(min) = 40 ns
 159          */
 160         popts->bstopre = 0x100;
 161
 162         /* Minimum CKE pulse width -- tCKE(MIN) */
 163         popts->tCKE_clock_pulse_width_ps
 164                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 165
 166         /*
 167          * Window for four activates -- tFAW
 168          *
 169          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 170          * FIXME: varies depending upon number of column addresses or data
 171          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 172          */
 173 #if defined(CONFIG_FSL_DDR1)
 174         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 175
 176 #elif defined(CONFIG_FSL_DDR2)
 177         /*
 178          * x4/x8;  some datasheets have 35000
 179          * x16 wide columns only?  Use 50000?
 180          */
 181         popts->tFAW_window_four_activates_ps = 37500;
 182
 183 #elif defined(CONFIG_FSL_DDR3)
 184 #error "FIXME determine four activates for DDR3"
 185 #endif
 186
 187         /*
 188          * Check interleaving configuration from environment.
 189          * Please refer to doc/README.fsl-ddr for the detail.
 190          *
 191          * If memory controller interleaving is enabled, then the data
 192          * bus widths must be programmed identically for the 2 memory
 193          * controllers.
 194          *
 195          * XXX: Attempt to set both controllers to the same chip select
 196          * interleaving mode. It will do a best effort to get the
 197          * requested ranks interleaved together such that the result
 198          * should be a subset of the requested configuration.
 199          */
 200 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 201         if ((p = getenv("memctl_intlv_ctl")) != NULL) {
 202                 if (pdimm[0].n_ranks == 0) {
 203                         printf("There is no rank on CS0. Because only rank on "
 204                                 "CS0 and ranks chip-select interleaved with CS0"
 205                                 " are controller interleaved, force non memory "
 206                                 "controller interleaving\n");
 207                         popts->memctl_interleaving = 0;
 208                 } else {
 209                         popts->memctl_interleaving = 1;
 210                         if (strcmp(p, "cacheline") == 0)
 211                                 popts->memctl_interleaving_mode =
 212                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 213                         else if (strcmp(p, "page") == 0)
 214                                 popts->memctl_interleaving_mode =
 215                                         FSL_DDR_PAGE_INTERLEAVING;
 216                         else if (strcmp(p, "bank") == 0)
 217                                 popts->memctl_interleaving_mode =
 218                                         FSL_DDR_BANK_INTERLEAVING;
 219                         else if (strcmp(p, "superbank") == 0)
 220                                 popts->memctl_interleaving_mode =
 221                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 222                         else
 223                                 popts->memctl_interleaving_mode =
 224                                                 simple_strtoul(p, NULL, 0);
 225                 }
 226         }
 227
 228         if( (p = getenv("ba_intlv_ctl")) != NULL) {
 229                 if (strcmp(p, "cs0_cs1") == 0)
 230                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 231                 else if (strcmp(p, "cs2_cs3") == 0)
 232                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 233                 else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
 234                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 235                 else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
 236                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 237                 else
 238                         popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
 239
 240                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 241                 case FSL_DDR_CS0_CS1_CS2_CS3:
 242                 case FSL_DDR_CS0_CS1:
 243                         if (pdimm[0].n_ranks != 2) {
 244                                 popts->ba_intlv_ctl = 0;
 245                                 printf("Not enough bank(chip-select) for "
 246                                         "CS0+CS1, force non-interleaving!\n");
 247                         }
 248                         break;
 249                 case FSL_DDR_CS2_CS3:
 250                         if (pdimm[1].n_ranks !=2){
 251                                 popts->ba_intlv_ctl = 0;
 252                                 printf("Not enough bank(CS) for CS2+CS3, "
 253                                         "force non-interleaving!\n");
 254                         }
 255                         break;
 256                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 257                         if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
 258                                 popts->ba_intlv_ctl = 0;
 259                                 printf("Not enough bank(CS) for CS0+CS1 or "
 260                                         "CS2+CS3, force non-interleaving!\n");
 261                         }
 262                         break;
 263                 default:
 264                         popts->ba_intlv_ctl = 0;
 265                         break;
 266                 }
 267         }
 268 #endif
 269
 270         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 271
 272         return 0;
 273 }