drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <asm/io.h>
  32 #include <asm/arch/mmc_host_def.h>
  33 #include <asm/arch/sys_proto.h>
  34
  35 /* If we fail after 1 second wait, something is really bad */
  36 #define MAX_RETRY_MS    1000
  37
  38 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size);
  39 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz);
  40 static struct mmc hsmmc_dev[2];
  41 unsigned char mmc_board_init(hsmmc_t *mmc_base)
  42 {
  43 #if defined(CONFIG_TWL4030_POWER)
  44         twl4030_power_mmc_init();
  45 #endif
  46
  47 #if defined(CONFIG_OMAP34XX)
  48         t2_t *t2_base = (t2_t *)T2_BASE;
  49         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  50
  51         writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
  52                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
  53                 &t2_base->pbias_lite);
  54
  55         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  56                 &t2_base->devconf0);
  57
  58         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
  59                 &t2_base->devconf1);
  60
  61         writel(readl(&prcm_base->fclken1_core) |
  62                 EN_MMC1 | EN_MMC2 | EN_MMC3,
  63                 &prcm_base->fclken1_core);
  64
  65         writel(readl(&prcm_base->iclken1_core) |
  66                 EN_MMC1 | EN_MMC2 | EN_MMC3,
  67                 &prcm_base->iclken1_core);
  68 #endif
  69
  70 /* TODO add appropriate OMAP4 init - none currently necessary */
  71
  72         return 0;
  73 }
  74
  75 void mmc_init_stream(hsmmc_t *mmc_base)
  76 {
  77         ulong start;
  78
  79         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
  80
  81         writel(MMC_CMD0, &mmc_base->cmd);
  82         start = get_timer(0);
  83         while (!(readl(&mmc_base->stat) & CC_MASK)) {
  84                 if (get_timer(0) - start > MAX_RETRY_MS) {
  85                         printf("%s: timedout waiting for cc!\n", __func__);
  86                         return;
  87                 }
  88         }
  89         writel(CC_MASK, &mmc_base->stat)
  90                 ;
  91         writel(MMC_CMD0, &mmc_base->cmd)
  92                 ;
  93         start = get_timer(0);
  94         while (!(readl(&mmc_base->stat) & CC_MASK)) {
  95                 if (get_timer(0) - start > MAX_RETRY_MS) {
  96                         printf("%s: timedout waiting for cc2!\n", __func__);
  97                         return;
  98                 }
  99         }
 100         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 101 }
 102
 103
 104 static int mmc_init_setup(struct mmc *mmc)
 105 {
 106         hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
 107         unsigned int reg_val;
 108         unsigned int dsor;
 109         ulong start;
 110
 111         mmc_board_init(mmc_base);
 112
 113         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 114                 &mmc_base->sysconfig);
 115         start = get_timer(0);
 116         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 117                 if (get_timer(0) - start > MAX_RETRY_MS) {
 118                         printf("%s: timedout waiting for cc2!\n", __func__);
 119                         return TIMEOUT;
 120                 }
 121         }
 122         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 123         start = get_timer(0);
 124         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 125                 if (get_timer(0) - start > MAX_RETRY_MS) {
 126                         printf("%s: timedout waiting for softresetall!\n",
 127                                 __func__);
 128                         return TIMEOUT;
 129                 }
 130         }
 131         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 132         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 133                 &mmc_base->capa);
 134
 135         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 136
 137         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 138                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 139                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 140
 141         dsor = 240;
 142         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 143                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 144         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 145                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 146         start = get_timer(0);
 147         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 148                 if (get_timer(0) - start > MAX_RETRY_MS) {
 149                         printf("%s: timedout waiting for ics!\n", __func__);
 150                         return TIMEOUT;
 151                 }
 152         }
 153         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 154
 155         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 156
 157         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 158                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 159                 &mmc_base->ie);
 160
 161         mmc_init_stream(mmc_base);
 162
 163         return 0;
 164 }
 165
 166
 167 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 168                         struct mmc_data *data)
 169 {
 170         hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
 171         unsigned int flags, mmc_stat;
 172         ulong start;
 173
 174         start = get_timer(0);
 175         while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
 176                 if (get_timer(0) - start > MAX_RETRY_MS) {
 177                         printf("%s: timedout waiting for cmddis!\n", __func__);
 178                         return TIMEOUT;
 179                 }
 180         }
 181         writel(0xFFFFFFFF, &mmc_base->stat);
 182         start = get_timer(0);
 183         while (readl(&mmc_base->stat)) {
 184                 if (get_timer(0) - start > MAX_RETRY_MS) {
 185                         printf("%s: timedout waiting for stat!\n", __func__);
 186                         return TIMEOUT;
 187                 }
 188         }
 189         /*
 190          * CMDREG
 191          * CMDIDX[13:8] : Command index
 192          * DATAPRNT[5]  : Data Present Select
 193          * ENCMDIDX[4]  : Command Index Check Enable
 194          * ENCMDCRC[3]  : Command CRC Check Enable
 195          * RSPTYP[1:0]
 196          *      00 = No Response
 197          *      01 = Length 136
 198          *      10 = Length 48
 199          *      11 = Length 48 Check busy after response
 200          */
 201         /* Delay added before checking the status of frq change
 202          * retry not supported by mmc.c(core file)
 203          */
 204         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 205                 udelay(50000); /* wait 50 ms */
 206
 207         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 208                 flags = 0;
 209         else if (cmd->resp_type & MMC_RSP_136)
 210                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 211         else if (cmd->resp_type & MMC_RSP_BUSY)
 212                 flags = RSP_TYPE_LGHT48B;
 213         else
 214                 flags = RSP_TYPE_LGHT48;
 215
 216         /* enable default flags */
 217         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 218                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 219
 220         if (cmd->resp_type & MMC_RSP_CRC)
 221                 flags |= CCCE_CHECK;
 222         if (cmd->resp_type & MMC_RSP_OPCODE)
 223                 flags |= CICE_CHECK;
 224
 225         if (data) {
 226                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 227                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 228                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 229                         data->blocksize = 512;
 230                         writel(data->blocksize | (data->blocks << 16),
 231                                                         &mmc_base->blk);
 232                 } else
 233                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 234
 235                 if (data->flags & MMC_DATA_READ)
 236                         flags |= (DP_DATA | DDIR_READ);
 237                 else
 238                         flags |= (DP_DATA | DDIR_WRITE);
 239         }
 240
 241         writel(cmd->cmdarg, &mmc_base->arg);
 242         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 243
 244         start = get_timer(0);
 245         do {
 246                 mmc_stat = readl(&mmc_base->stat);
 247                 if (get_timer(0) - start > MAX_RETRY_MS) {
 248                         printf("%s : timeout: No status update\n", __func__);
 249                         return TIMEOUT;
 250                 }
 251         } while (!mmc_stat);
 252
 253         if ((mmc_stat & IE_CTO) != 0)
 254                 return TIMEOUT;
 255         else if ((mmc_stat & ERRI_MASK) != 0)
 256                 return -1;
 257
 258         if (mmc_stat & CC_MASK) {
 259                 writel(CC_MASK, &mmc_base->stat);
 260                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 261                         if (cmd->resp_type & MMC_RSP_136) {
 262                                 /* response type 2 */
 263                                 cmd->response[3] = readl(&mmc_base->rsp10);
 264                                 cmd->response[2] = readl(&mmc_base->rsp32);
 265                                 cmd->response[1] = readl(&mmc_base->rsp54);
 266                                 cmd->response[0] = readl(&mmc_base->rsp76);
 267                         } else
 268                                 /* response types 1, 1b, 3, 4, 5, 6 */
 269                                 cmd->response[0] = readl(&mmc_base->rsp10);
 270                 }
 271         }
 272
 273         if (data && (data->flags & MMC_DATA_READ)) {
 274                 mmc_read_data(mmc_base, data->dest,
 275                                 data->blocksize * data->blocks);
 276         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 277                 mmc_write_data(mmc_base, data->src,
 278                                 data->blocksize * data->blocks);
 279         }
 280         return 0;
 281 }
 282
 283 static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size)
 284 {
 285         unsigned int *output_buf = (unsigned int *)buf;
 286         unsigned int mmc_stat;
 287         unsigned int count;
 288
 289         /*
 290          * Start Polled Read
 291          */
 292         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 293         count /= 4;
 294
 295         while (size) {
 296                 ulong start = get_timer(0);
 297                 do {
 298                         mmc_stat = readl(&mmc_base->stat);
 299                         if (get_timer(0) - start > MAX_RETRY_MS) {
 300                                 printf("%s: timedout waiting for status!\n",
 301                                                 __func__);
 302                                 return TIMEOUT;
 303                         }
 304                 } while (mmc_stat == 0);
 305
 306                 if ((mmc_stat & ERRI_MASK) != 0)
 307                         return 1;
 308
 309                 if (mmc_stat & BRR_MASK) {
 310                         unsigned int k;
 311
 312                         writel(readl(&mmc_base->stat) | BRR_MASK,
 313                                 &mmc_base->stat);
 314                         for (k = 0; k < count; k++) {
 315                                 *output_buf = readl(&mmc_base->data);
 316                                 output_buf++;
 317                         }
 318                         size -= (count*4);
 319                 }
 320
 321                 if (mmc_stat & BWR_MASK)
 322                         writel(readl(&mmc_base->stat) | BWR_MASK,
 323                                 &mmc_base->stat);
 324
 325                 if (mmc_stat & TC_MASK) {
 326                         writel(readl(&mmc_base->stat) | TC_MASK,
 327                                 &mmc_base->stat);
 328                         break;
 329                 }
 330         }
 331         return 0;
 332 }
 333
 334 static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size)
 335 {
 336         unsigned int *input_buf = (unsigned int *)buf;
 337         unsigned int mmc_stat;
 338         unsigned int count;
 339
 340         /*
 341          * Start Polled Read
 342          */
 343         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 344         count /= 4;
 345
 346         while (size) {
 347                 ulong start = get_timer(0);
 348                 do {
 349                         mmc_stat = readl(&mmc_base->stat);
 350                         if (get_timer(0) - start > MAX_RETRY_MS) {
 351                                 printf("%s: timedout waiting for status!\n",
 352                                                 __func__);
 353                                 return TIMEOUT;
 354                         }
 355                 } while (mmc_stat == 0);
 356
 357                 if ((mmc_stat & ERRI_MASK) != 0)
 358                         return 1;
 359
 360                 if (mmc_stat & BWR_MASK) {
 361                         unsigned int k;
 362
 363                         writel(readl(&mmc_base->stat) | BWR_MASK,
 364                                         &mmc_base->stat);
 365                         for (k = 0; k < count; k++) {
 366                                 writel(*input_buf, &mmc_base->data);
 367                                 input_buf++;
 368                         }
 369                         size -= (count*4);
 370                 }
 371
 372                 if (mmc_stat & BRR_MASK)
 373                         writel(readl(&mmc_base->stat) | BRR_MASK,
 374                                 &mmc_base->stat);
 375
 376                 if (mmc_stat & TC_MASK) {
 377                         writel(readl(&mmc_base->stat) | TC_MASK,
 378                                 &mmc_base->stat);
 379                         break;
 380                 }
 381         }
 382         return 0;
 383 }
 384
 385 static void mmc_set_ios(struct mmc *mmc)
 386 {
 387         hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
 388         unsigned int dsor = 0;
 389         ulong start;
 390
 391         /* configue bus width */
 392         switch (mmc->bus_width) {
 393         case 8:
 394                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 395                         &mmc_base->con);
 396                 break;
 397
 398         case 4:
 399                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 400                         &mmc_base->con);
 401                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 402                         &mmc_base->hctl);
 403                 break;
 404
 405         case 1:
 406         default:
 407                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 408                         &mmc_base->con);
 409                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 410                         &mmc_base->hctl);
 411                 break;
 412         }
 413
 414         /* configure clock with 96Mhz system clock.
 415          */
 416         if (mmc->clock != 0) {
 417                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 418                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 419                         dsor++;
 420         }
 421
 422         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 423                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 424
 425         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 426                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 427
 428         start = get_timer(0);
 429         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 430                 if (get_timer(0) - start > MAX_RETRY_MS) {
 431                         printf("%s: timedout waiting for ics!\n", __func__);
 432                         return;
 433                 }
 434         }
 435         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 436 }
 437
 438 int omap_mmc_init(int dev_index)
 439 {
 440         struct mmc *mmc;
 441
 442         mmc = &hsmmc_dev[dev_index];
 443
 444         sprintf(mmc->name, "OMAP SD/MMC");
 445         mmc->send_cmd = mmc_send_cmd;
 446         mmc->set_ios = mmc_set_ios;
 447         mmc->init = mmc_init_setup;
 448
 449         switch (dev_index) {
 450         case 0:
 451                 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
 452                 break;
 453         case 1:
 454                 mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
 455                 break;
 456         case 2:
 457                 mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
 458                 break;
 459         default:
 460                 mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
 461                 return 1;
 462         }
 463         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 464         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 465
 466         mmc->f_min = 400000;
 467         mmc->f_max = 52000000;
 468
 469         mmc->b_max = 0;
 470
 471 #if defined(CONFIG_OMAP34XX)
 472         /*
 473          * Silicon revs 2.1 and older do not support multiblock transfers.
 474          */
 475         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 476                 mmc->b_max = 1;
 477 #endif
 478
 479         mmc_register(mmc);
 480
 481         return 0;
 482 }