drivers/mmc/sdhci.c

   1 /*
   2  * Copyright 2011, Marvell Semiconductor Inc.
   3  * Lei Wen <leiwen@marvell.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Back ported to the 8xx platform (from the 8260 platform) by
  24  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  25  */
  26
  27 #include <common.h>
  28 #include <malloc.h>
  29 #include <mmc.h>
  30 #include <sdhci.h>
  31
  32 void *aligned_buffer;
  33
  34 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  35 {
  36         unsigned long timeout;
  37
  38         /* Wait max 100 ms */
  39         timeout = 100;
  40         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  41         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  42                 if (timeout == 0) {
  43                         printf("Reset 0x%x never completed.\n", (int)mask);
  44                         return;
  45                 }
  46                 timeout--;
  47                 udelay(1000);
  48         }
  49 }
  50
  51 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  52 {
  53         int i;
  54         if (cmd->resp_type & MMC_RSP_136) {
  55                 /* CRC is stripped so we need to do some shifting. */
  56                 for (i = 0; i < 4; i++) {
  57                         cmd->response[i] = sdhci_readl(host,
  58                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  59                         if (i != 3)
  60                                 cmd->response[i] |= sdhci_readb(host,
  61                                                 SDHCI_RESPONSE + (3-i)*4-1);
  62                 }
  63         } else {
  64                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  65         }
  66 }
  67
  68 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  69 {
  70         int i;
  71         char *offs;
  72         for (i = 0; i < data->blocksize; i += 4) {
  73                 offs = data->dest + i;
  74                 if (data->flags == MMC_DATA_READ)
  75                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  76                 else
  77                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  78         }
  79 }
  80
  81 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  82                                 unsigned int start_addr)
  83 {
  84         unsigned int stat, rdy, mask, timeout, block = 0;
  85 #ifdef CONFIG_MMC_SDMA
  86         unsigned char ctrl;
  87         ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
  88         ctrl &= ~SDHCI_CTRL_DMA_MASK;
  89         ctrl |= SDHCI_CTRL_SDMA;
  90         sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
  91 #endif
  92
  93         timeout = 1000000;
  94         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  95         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  96         do {
  97                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
  98                 if (stat & SDHCI_INT_ERROR) {
  99                         printf("Error detected in status(0x%X)!\n", stat);
 100                         return -1;
 101                 }
 102                 if (stat & rdy) {
 103                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 104                                 continue;
 105                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 106                         sdhci_transfer_pio(host, data);
 107                         data->dest += data->blocksize;
 108                         if (++block >= data->blocks)
 109                                 break;
 110                 }
 111 #ifdef CONFIG_MMC_SDMA
 112                 if (stat & SDHCI_INT_DMA_END) {
 113                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 114                         start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 115                         start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 116                         sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 117                 }
 118 #endif
 119                 if (timeout-- > 0)
 120                         udelay(10);
 121                 else {
 122                         printf("Transfer data timeout\n");
 123                         return -1;
 124                 }
 125         } while (!(stat & SDHCI_INT_DATA_END));
 126         return 0;
 127 }
 128
 129 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 130                        struct mmc_data *data)
 131 {
 132         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 133         unsigned int stat = 0;
 134         int ret = 0;
 135         int trans_bytes = 0, is_aligned = 1;
 136         u32 mask, flags, mode;
 137         unsigned int timeout, start_addr = 0;
 138         unsigned int retry = 10000;
 139
 140         /* Wait max 10 ms */
 141         timeout = 10;
 142
 143         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 144         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 145
 146         /* We shouldn't wait for data inihibit for stop commands, even
 147            though they might use busy signaling */
 148         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 149                 mask &= ~SDHCI_DATA_INHIBIT;
 150
 151         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 152                 if (timeout == 0) {
 153                         printf("Controller never released inhibit bit(s).\n");
 154                         return COMM_ERR;
 155                 }
 156                 timeout--;
 157                 udelay(1000);
 158         }
 159
 160         mask = SDHCI_INT_RESPONSE;
 161         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 162                 flags = SDHCI_CMD_RESP_NONE;
 163         else if (cmd->resp_type & MMC_RSP_136)
 164                 flags = SDHCI_CMD_RESP_LONG;
 165         else if (cmd->resp_type & MMC_RSP_BUSY) {
 166                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 167                 mask |= SDHCI_INT_DATA_END;
 168         } else
 169                 flags = SDHCI_CMD_RESP_SHORT;
 170
 171         if (cmd->resp_type & MMC_RSP_CRC)
 172                 flags |= SDHCI_CMD_CRC;
 173         if (cmd->resp_type & MMC_RSP_OPCODE)
 174                 flags |= SDHCI_CMD_INDEX;
 175         if (data)
 176                 flags |= SDHCI_CMD_DATA;
 177
 178         /*Set Transfer mode regarding to data flag*/
 179         if (data != 0) {
 180                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 181                 mode = SDHCI_TRNS_BLK_CNT_EN;
 182                 trans_bytes = data->blocks * data->blocksize;
 183                 if (data->blocks > 1)
 184                         mode |= SDHCI_TRNS_MULTI;
 185
 186                 if (data->flags == MMC_DATA_READ)
 187                         mode |= SDHCI_TRNS_READ;
 188
 189 #ifdef CONFIG_MMC_SDMA
 190                 if (data->flags == MMC_DATA_READ)
 191                         start_addr = (unsigned int)data->dest;
 192                 else
 193                         start_addr = (unsigned int)data->src;
 194                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 195                                 (start_addr & 0x7) != 0x0) {
 196                         is_aligned = 0;
 197                         start_addr = (unsigned int)aligned_buffer;
 198                         if (data->flags != MMC_DATA_READ)
 199                                 memcpy(aligned_buffer, data->src, trans_bytes);
 200                 }
 201
 202                 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 203                 mode |= SDHCI_TRNS_DMA;
 204 #endif
 205                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 206                                 data->blocksize),
 207                                 SDHCI_BLOCK_SIZE);
 208                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 209                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 210         }
 211
 212         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 213 #ifdef CONFIG_MMC_SDMA
 214         flush_cache(start_addr, trans_bytes);
 215 #endif
 216         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 217         do {
 218                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 219                 if (stat & SDHCI_INT_ERROR)
 220                         break;
 221                 if (--retry == 0)
 222                         break;
 223         } while ((stat & mask) != mask);
 224
 225         if (retry == 0) {
 226                 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
 227                         return 0;
 228                 else {
 229                         printf("Timeout for status update!\n");
 230                         return TIMEOUT;
 231                 }
 232         }
 233
 234         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 235                 sdhci_cmd_done(host, cmd);
 236                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 237         } else
 238                 ret = -1;
 239
 240         if (!ret && data)
 241                 ret = sdhci_transfer_data(host, data, start_addr);
 242
 243         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 244                 udelay(1000);
 245
 246         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 247         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 248         if (!ret) {
 249                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 250                                 !is_aligned && (data->flags == MMC_DATA_READ))
 251                         memcpy(data->dest, aligned_buffer, trans_bytes);
 252                 return 0;
 253         }
 254
 255         sdhci_reset(host, SDHCI_RESET_CMD);
 256         sdhci_reset(host, SDHCI_RESET_DATA);
 257         if (stat & SDHCI_INT_TIMEOUT)
 258                 return TIMEOUT;
 259         else
 260                 return COMM_ERR;
 261 }
 262
 263 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 264 {
 265         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 266         unsigned int div, clk, timeout;
 267
 268         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 269
 270         if (clock == 0)
 271                 return 0;
 272
 273         if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
 274                 /* Version 3.00 divisors must be a multiple of 2. */
 275                 if (mmc->f_max <= clock)
 276                         div = 1;
 277                 else {
 278                         for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
 279                                 if ((mmc->f_max / div) <= clock)
 280                                         break;
 281                         }
 282                 }
 283         } else {
 284                 /* Version 2.00 divisors must be a power of 2. */
 285                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 286                         if ((mmc->f_max / div) <= clock)
 287                                 break;
 288                 }
 289         }
 290         div >>= 1;
 291
 292         if (host->set_clock)
 293                 host->set_clock(host->index, div);
 294
 295         clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 296         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 297                 << SDHCI_DIVIDER_HI_SHIFT;
 298         clk |= SDHCI_CLOCK_INT_EN;
 299         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 300
 301         /* Wait max 20 ms */
 302         timeout = 20;
 303         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 304                 & SDHCI_CLOCK_INT_STABLE)) {
 305                 if (timeout == 0) {
 306                         printf("Internal clock never stabilised.\n");
 307                         return -1;
 308                 }
 309                 timeout--;
 310                 udelay(1000);
 311         }
 312
 313         clk |= SDHCI_CLOCK_CARD_EN;
 314         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 315         return 0;
 316 }
 317
 318 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 319 {
 320         u8 pwr = 0;
 321
 322         if (power != (unsigned short)-1) {
 323                 switch (1 << power) {
 324                 case MMC_VDD_165_195:
 325                         pwr = SDHCI_POWER_180;
 326                         break;
 327                 case MMC_VDD_29_30:
 328                 case MMC_VDD_30_31:
 329                         pwr = SDHCI_POWER_300;
 330                         break;
 331                 case MMC_VDD_32_33:
 332                 case MMC_VDD_33_34:
 333                         pwr = SDHCI_POWER_330;
 334                         break;
 335                 }
 336         }
 337
 338         if (pwr == 0) {
 339                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 340                 return;
 341         }
 342
 343         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
 344                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 345
 346         pwr |= SDHCI_POWER_ON;
 347
 348         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 349 }
 350
 351 void sdhci_set_ios(struct mmc *mmc)
 352 {
 353         u32 ctrl;
 354         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 355
 356         if (host->set_control_reg)
 357                 host->set_control_reg(host);
 358
 359         if (mmc->clock != host->clock)
 360                 sdhci_set_clock(mmc, mmc->clock);
 361
 362         /* Set bus width */
 363         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 364         if (mmc->bus_width == 8) {
 365                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 366                 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
 367                         ctrl |= SDHCI_CTRL_8BITBUS;
 368         } else {
 369                 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
 370                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 371                 if (mmc->bus_width == 4)
 372                         ctrl |= SDHCI_CTRL_4BITBUS;
 373                 else
 374                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 375         }
 376
 377         if (mmc->clock > 26000000)
 378                 ctrl |= SDHCI_CTRL_HISPD;
 379         else
 380                 ctrl &= ~SDHCI_CTRL_HISPD;
 381
 382         if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
 383                 ctrl &= ~SDHCI_CTRL_HISPD;
 384
 385         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 386 }
 387
 388 int sdhci_init(struct mmc *mmc)
 389 {
 390         struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 391
 392         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 393                 aligned_buffer = memalign(8, 512*1024);
 394                 if (!aligned_buffer) {
 395                         printf("Aligned buffer alloc failed!!!");
 396                         return -1;
 397                 }
 398         }
 399
 400         sdhci_set_power(host, fls(mmc->voltages) - 1);
 401
 402         if (host->quirks & SDHCI_QUIRK_NO_CD) {
 403                 unsigned int status;
 404
 405                 sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
 406                         SDHCI_HOST_CONTROL);
 407
 408                 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
 409                 while ((!(status & SDHCI_CARD_PRESENT)) ||
 410                     (!(status & SDHCI_CARD_STATE_STABLE)) ||
 411                     (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
 412                         status = sdhci_readl(host, SDHCI_PRESENT_STATE);
 413         }
 414
 415         /* Enable only interrupts served by the SD controller */
 416         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK
 417                      , SDHCI_INT_ENABLE);
 418         /* Mask all sdhci interrupt sources */
 419         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 420
 421         return 0;
 422 }
 423
 424 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 425 {
 426         struct mmc *mmc;
 427         unsigned int caps;
 428
 429         mmc = malloc(sizeof(struct mmc));
 430         if (!mmc) {
 431                 printf("mmc malloc fail!\n");
 432                 return -1;
 433         }
 434
 435         mmc->priv = host;
 436         host->mmc = mmc;
 437
 438         sprintf(mmc->name, "%s", host->name);
 439         mmc->send_cmd = sdhci_send_command;
 440         mmc->set_ios = sdhci_set_ios;
 441         mmc->init = sdhci_init;
 442         mmc->getcd = NULL;
 443         mmc->getwp = NULL;
 444
 445         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 446 #ifdef CONFIG_MMC_SDMA
 447         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 448                 printf("Your controller don't support sdma!!\n");
 449                 return -1;
 450         }
 451 #endif
 452
 453         if (max_clk)
 454                 mmc->f_max = max_clk;
 455         else {
 456                 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
 457                         mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
 458                                 >> SDHCI_CLOCK_BASE_SHIFT;
 459                 else
 460                         mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
 461                                 >> SDHCI_CLOCK_BASE_SHIFT;
 462                 mmc->f_max *= 1000000;
 463         }
 464         if (mmc->f_max == 0) {
 465                 printf("Hardware doesn't specify base clock frequency\n");
 466                 return -1;
 467         }
 468         if (min_clk)
 469                 mmc->f_min = min_clk;
 470         else {
 471                 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
 472                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
 473                 else
 474                         mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
 475         }
 476
 477         mmc->voltages = 0;
 478         if (caps & SDHCI_CAN_VDD_330)
 479                 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 480         if (caps & SDHCI_CAN_VDD_300)
 481                 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 482         if (caps & SDHCI_CAN_VDD_180)
 483                 mmc->voltages |= MMC_VDD_165_195;
 484
 485         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 486                 mmc->voltages |= host->voltages;
 487
 488         mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 489         if (caps & SDHCI_CAN_DO_8BIT)
 490                 mmc->host_caps |= MMC_MODE_8BIT;
 491         if (host->host_caps)
 492                 mmc->host_caps |= host->host_caps;
 493
 494         sdhci_reset(host, SDHCI_RESET_ALL);
 495         mmc_register(mmc);
 496
 497         return 0;
 498 }