drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms of the GNU General Public License as published by the Free
  14   Software Foundation; either version 2 of the License, or (at your option)
  15   any later version.
  16
  17   This program is distributed in the hope that it will be useful, but WITHOUT
  18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20   more details.
  21
  22   You should have received a copy of the GNU General Public License along with
  23   this program; if not, write to the Free Software Foundation, Inc., 59
  24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25
  26   The full GNU General Public License is included in this distribution in the
  27   file called LICENSE.
  28
  29   Contact Information:
  30   Linux NICS <linux.nics@intel.com>
  31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32
  33 *******************************************************************************/
  34 /*
  35  *  Copyright (C) Archway Digital Solutions.
  36  *
  37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  38  *  2/9/2002
  39  *
  40  *  Copyright (C) Linux Networx.
  41  *  Massive upgrade to work with the new intel gigabit NICs.
  42  *  <ebiederman at lnxi dot com>
  43  *
  44  *  Copyright 2011 Freescale Semiconductor, Inc.
  45  */
  46
  47 #include "e1000.h"
  48
  49 #define TOUT_LOOP   100000
  50
  51 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  52 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  53
  54 #define E1000_DEFAULT_PCI_PBA   0x00000030
  55 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  56
  57 /* NIC specific static variables go here */
  58
  59 static char tx_pool[128 + 16];
  60 static char rx_pool[128 + 16];
  61 static char packet[2096];
  62
  63 static struct e1000_tx_desc *tx_base;
  64 static struct e1000_rx_desc *rx_base;
  65
  66 static int tx_tail;
  67 static int rx_tail, rx_last;
  68
  69 static struct pci_device_id e1000_supported[] = {
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  72         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  87         /* E1000 PCIe card */
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
 103         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
 104         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
 105         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
 106         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
 107         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
 108         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
 109         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
 110         {}
 111 };
 112
 113 /* Function forward declarations */
 114 static int e1000_setup_link(struct eth_device *nic);
 115 static int e1000_setup_fiber_link(struct eth_device *nic);
 116 static int e1000_setup_copper_link(struct eth_device *nic);
 117 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 118 static void e1000_config_collision_dist(struct e1000_hw *hw);
 119 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 120 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 121 static int e1000_check_for_link(struct eth_device *nic);
 122 static int e1000_wait_autoneg(struct e1000_hw *hw);
 123 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 124                                        uint16_t * duplex);
 125 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 126                               uint16_t * phy_data);
 127 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 128                                uint16_t phy_data);
 129 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 130 static int e1000_phy_reset(struct e1000_hw *hw);
 131 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 132 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 133 static void e1000_set_media_type(struct e1000_hw *hw);
 134
 135 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 136 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 137 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
 138 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
 139 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
 140                         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
 141 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
 142         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
 143 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
 144
 145 #ifndef CONFIG_AP1000 /* remove for warnings */
 146 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 147                 uint16_t words,
 148                 uint16_t *data);
 149 /******************************************************************************
 150  * Raises the EEPROM's clock input.
 151  *
 152  * hw - Struct containing variables accessed by shared code
 153  * eecd - EECD's current value
 154  *****************************************************************************/
 155 static void
 156 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 157 {
 158         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 159          * wait 50 microseconds.
 160          */
 161         *eecd = *eecd | E1000_EECD_SK;
 162         E1000_WRITE_REG(hw, EECD, *eecd);
 163         E1000_WRITE_FLUSH(hw);
 164         udelay(50);
 165 }
 166
 167 /******************************************************************************
 168  * Lowers the EEPROM's clock input.
 169  *
 170  * hw - Struct containing variables accessed by shared code
 171  * eecd - EECD's current value
 172  *****************************************************************************/
 173 static void
 174 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 175 {
 176         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 177          * wait 50 microseconds.
 178          */
 179         *eecd = *eecd & ~E1000_EECD_SK;
 180         E1000_WRITE_REG(hw, EECD, *eecd);
 181         E1000_WRITE_FLUSH(hw);
 182         udelay(50);
 183 }
 184
 185 /******************************************************************************
 186  * Shift data bits out to the EEPROM.
 187  *
 188  * hw - Struct containing variables accessed by shared code
 189  * data - data to send to the EEPROM
 190  * count - number of bits to shift out
 191  *****************************************************************************/
 192 static void
 193 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 194 {
 195         uint32_t eecd;
 196         uint32_t mask;
 197
 198         /* We need to shift "count" bits out to the EEPROM. So, value in the
 199          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 200          * In order to do this, "data" must be broken down into bits.
 201          */
 202         mask = 0x01 << (count - 1);
 203         eecd = E1000_READ_REG(hw, EECD);
 204         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 205         do {
 206                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 207                  * and then raising and then lowering the clock (the SK bit controls
 208                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 209                  * by setting "DI" to "0" and then raising and then lowering the clock.
 210                  */
 211                 eecd &= ~E1000_EECD_DI;
 212
 213                 if (data & mask)
 214                         eecd |= E1000_EECD_DI;
 215
 216                 E1000_WRITE_REG(hw, EECD, eecd);
 217                 E1000_WRITE_FLUSH(hw);
 218
 219                 udelay(50);
 220
 221                 e1000_raise_ee_clk(hw, &eecd);
 222                 e1000_lower_ee_clk(hw, &eecd);
 223
 224                 mask = mask >> 1;
 225
 226         } while (mask);
 227
 228         /* We leave the "DI" bit set to "0" when we leave this routine. */
 229         eecd &= ~E1000_EECD_DI;
 230         E1000_WRITE_REG(hw, EECD, eecd);
 231 }
 232
 233 /******************************************************************************
 234  * Shift data bits in from the EEPROM
 235  *
 236  * hw - Struct containing variables accessed by shared code
 237  *****************************************************************************/
 238 static uint16_t
 239 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 240 {
 241         uint32_t eecd;
 242         uint32_t i;
 243         uint16_t data;
 244
 245         /* In order to read a register from the EEPROM, we need to shift 'count'
 246          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 247          * input to the EEPROM (setting the SK bit), and then reading the
 248          * value of the "DO" bit.  During this "shifting in" process the
 249          * "DI" bit should always be clear.
 250          */
 251
 252         eecd = E1000_READ_REG(hw, EECD);
 253
 254         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 255         data = 0;
 256
 257         for (i = 0; i < count; i++) {
 258                 data = data << 1;
 259                 e1000_raise_ee_clk(hw, &eecd);
 260
 261                 eecd = E1000_READ_REG(hw, EECD);
 262
 263                 eecd &= ~(E1000_EECD_DI);
 264                 if (eecd & E1000_EECD_DO)
 265                         data |= 1;
 266
 267                 e1000_lower_ee_clk(hw, &eecd);
 268         }
 269
 270         return data;
 271 }
 272
 273 /******************************************************************************
 274  * Returns EEPROM to a "standby" state
 275  *
 276  * hw - Struct containing variables accessed by shared code
 277  *****************************************************************************/
 278 static void
 279 e1000_standby_eeprom(struct e1000_hw *hw)
 280 {
 281         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 282         uint32_t eecd;
 283
 284         eecd = E1000_READ_REG(hw, EECD);
 285
 286         if (eeprom->type == e1000_eeprom_microwire) {
 287                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 288                 E1000_WRITE_REG(hw, EECD, eecd);
 289                 E1000_WRITE_FLUSH(hw);
 290                 udelay(eeprom->delay_usec);
 291
 292                 /* Clock high */
 293                 eecd |= E1000_EECD_SK;
 294                 E1000_WRITE_REG(hw, EECD, eecd);
 295                 E1000_WRITE_FLUSH(hw);
 296                 udelay(eeprom->delay_usec);
 297
 298                 /* Select EEPROM */
 299                 eecd |= E1000_EECD_CS;
 300                 E1000_WRITE_REG(hw, EECD, eecd);
 301                 E1000_WRITE_FLUSH(hw);
 302                 udelay(eeprom->delay_usec);
 303
 304                 /* Clock low */
 305                 eecd &= ~E1000_EECD_SK;
 306                 E1000_WRITE_REG(hw, EECD, eecd);
 307                 E1000_WRITE_FLUSH(hw);
 308                 udelay(eeprom->delay_usec);
 309         } else if (eeprom->type == e1000_eeprom_spi) {
 310                 /* Toggle CS to flush commands */
 311                 eecd |= E1000_EECD_CS;
 312                 E1000_WRITE_REG(hw, EECD, eecd);
 313                 E1000_WRITE_FLUSH(hw);
 314                 udelay(eeprom->delay_usec);
 315                 eecd &= ~E1000_EECD_CS;
 316                 E1000_WRITE_REG(hw, EECD, eecd);
 317                 E1000_WRITE_FLUSH(hw);
 318                 udelay(eeprom->delay_usec);
 319         }
 320 }
 321
 322 /***************************************************************************
 323 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 324 *
 325 * hw - Struct containing variables accessed by shared code
 326 ****************************************************************************/
 327 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 328 {
 329         uint32_t eecd = 0;
 330
 331         DEBUGFUNC();
 332
 333         if (hw->mac_type == e1000_ich8lan)
 334                 return FALSE;
 335
 336         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 337                 eecd = E1000_READ_REG(hw, EECD);
 338
 339                 /* Isolate bits 15 & 16 */
 340                 eecd = ((eecd >> 15) & 0x03);
 341
 342                 /* If both bits are set, device is Flash type */
 343                 if (eecd == 0x03)
 344                         return FALSE;
 345         }
 346         return TRUE;
 347 }
 348
 349 /******************************************************************************
 350  * Prepares EEPROM for access
 351  *
 352  * hw - Struct containing variables accessed by shared code
 353  *
 354  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 355  * function should be called before issuing a command to the EEPROM.
 356  *****************************************************************************/
 357 static int32_t
 358 e1000_acquire_eeprom(struct e1000_hw *hw)
 359 {
 360         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 361         uint32_t eecd, i = 0;
 362
 363         DEBUGFUNC();
 364
 365         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 366                 return -E1000_ERR_SWFW_SYNC;
 367         eecd = E1000_READ_REG(hw, EECD);
 368
 369         if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
 370                 /* Request EEPROM Access */
 371                 if (hw->mac_type > e1000_82544) {
 372                         eecd |= E1000_EECD_REQ;
 373                         E1000_WRITE_REG(hw, EECD, eecd);
 374                         eecd = E1000_READ_REG(hw, EECD);
 375                         while ((!(eecd & E1000_EECD_GNT)) &&
 376                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 377                                 i++;
 378                                 udelay(5);
 379                                 eecd = E1000_READ_REG(hw, EECD);
 380                         }
 381                         if (!(eecd & E1000_EECD_GNT)) {
 382                                 eecd &= ~E1000_EECD_REQ;
 383                                 E1000_WRITE_REG(hw, EECD, eecd);
 384                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 385                                 return -E1000_ERR_EEPROM;
 386                         }
 387                 }
 388         }
 389
 390         /* Setup EEPROM for Read/Write */
 391
 392         if (eeprom->type == e1000_eeprom_microwire) {
 393                 /* Clear SK and DI */
 394                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 395                 E1000_WRITE_REG(hw, EECD, eecd);
 396
 397                 /* Set CS */
 398                 eecd |= E1000_EECD_CS;
 399                 E1000_WRITE_REG(hw, EECD, eecd);
 400         } else if (eeprom->type == e1000_eeprom_spi) {
 401                 /* Clear SK and CS */
 402                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 403                 E1000_WRITE_REG(hw, EECD, eecd);
 404                 udelay(1);
 405         }
 406
 407         return E1000_SUCCESS;
 408 }
 409
 410 /******************************************************************************
 411  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 412  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 413  * registers must be mapped, or this will crash.
 414  *
 415  * hw - Struct containing variables accessed by shared code
 416  *****************************************************************************/
 417 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 418 {
 419         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 420         uint32_t eecd = E1000_READ_REG(hw, EECD);
 421         int32_t ret_val = E1000_SUCCESS;
 422         uint16_t eeprom_size;
 423
 424         DEBUGFUNC();
 425
 426         switch (hw->mac_type) {
 427         case e1000_82542_rev2_0:
 428         case e1000_82542_rev2_1:
 429         case e1000_82543:
 430         case e1000_82544:
 431                 eeprom->type = e1000_eeprom_microwire;
 432                 eeprom->word_size = 64;
 433                 eeprom->opcode_bits = 3;
 434                 eeprom->address_bits = 6;
 435                 eeprom->delay_usec = 50;
 436                 eeprom->use_eerd = FALSE;
 437                 eeprom->use_eewr = FALSE;
 438         break;
 439         case e1000_82540:
 440         case e1000_82545:
 441         case e1000_82545_rev_3:
 442         case e1000_82546:
 443         case e1000_82546_rev_3:
 444                 eeprom->type = e1000_eeprom_microwire;
 445                 eeprom->opcode_bits = 3;
 446                 eeprom->delay_usec = 50;
 447                 if (eecd & E1000_EECD_SIZE) {
 448                         eeprom->word_size = 256;
 449                         eeprom->address_bits = 8;
 450                 } else {
 451                         eeprom->word_size = 64;
 452                         eeprom->address_bits = 6;
 453                 }
 454                 eeprom->use_eerd = FALSE;
 455                 eeprom->use_eewr = FALSE;
 456                 break;
 457         case e1000_82541:
 458         case e1000_82541_rev_2:
 459         case e1000_82547:
 460         case e1000_82547_rev_2:
 461                 if (eecd & E1000_EECD_TYPE) {
 462                         eeprom->type = e1000_eeprom_spi;
 463                         eeprom->opcode_bits = 8;
 464                         eeprom->delay_usec = 1;
 465                         if (eecd & E1000_EECD_ADDR_BITS) {
 466                                 eeprom->page_size = 32;
 467                                 eeprom->address_bits = 16;
 468                         } else {
 469                                 eeprom->page_size = 8;
 470                                 eeprom->address_bits = 8;
 471                         }
 472                 } else {
 473                         eeprom->type = e1000_eeprom_microwire;
 474                         eeprom->opcode_bits = 3;
 475                         eeprom->delay_usec = 50;
 476                         if (eecd & E1000_EECD_ADDR_BITS) {
 477                                 eeprom->word_size = 256;
 478                                 eeprom->address_bits = 8;
 479                         } else {
 480                                 eeprom->word_size = 64;
 481                                 eeprom->address_bits = 6;
 482                         }
 483                 }
 484                 eeprom->use_eerd = FALSE;
 485                 eeprom->use_eewr = FALSE;
 486                 break;
 487         case e1000_82571:
 488         case e1000_82572:
 489                 eeprom->type = e1000_eeprom_spi;
 490                 eeprom->opcode_bits = 8;
 491                 eeprom->delay_usec = 1;
 492                 if (eecd & E1000_EECD_ADDR_BITS) {
 493                         eeprom->page_size = 32;
 494                         eeprom->address_bits = 16;
 495                 } else {
 496                         eeprom->page_size = 8;
 497                         eeprom->address_bits = 8;
 498                 }
 499                 eeprom->use_eerd = FALSE;
 500                 eeprom->use_eewr = FALSE;
 501                 break;
 502         case e1000_82573:
 503         case e1000_82574:
 504                 eeprom->type = e1000_eeprom_spi;
 505                 eeprom->opcode_bits = 8;
 506                 eeprom->delay_usec = 1;
 507                 if (eecd & E1000_EECD_ADDR_BITS) {
 508                         eeprom->page_size = 32;
 509                         eeprom->address_bits = 16;
 510                 } else {
 511                         eeprom->page_size = 8;
 512                         eeprom->address_bits = 8;
 513                 }
 514                 eeprom->use_eerd = TRUE;
 515                 eeprom->use_eewr = TRUE;
 516                 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
 517                         eeprom->type = e1000_eeprom_flash;
 518                         eeprom->word_size = 2048;
 519
 520                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 521                  * Flash update issue on parts which use a FLASH for NVM. */
 522                         eecd &= ~E1000_EECD_AUPDEN;
 523                         E1000_WRITE_REG(hw, EECD, eecd);
 524                 }
 525                 break;
 526         case e1000_80003es2lan:
 527                 eeprom->type = e1000_eeprom_spi;
 528                 eeprom->opcode_bits = 8;
 529                 eeprom->delay_usec = 1;
 530                 if (eecd & E1000_EECD_ADDR_BITS) {
 531                         eeprom->page_size = 32;
 532                         eeprom->address_bits = 16;
 533                 } else {
 534                         eeprom->page_size = 8;
 535                         eeprom->address_bits = 8;
 536                 }
 537                 eeprom->use_eerd = TRUE;
 538                 eeprom->use_eewr = FALSE;
 539                 break;
 540
 541         /* ich8lan does not support currently. if needed, please
 542          * add corresponding code and functions.
 543          */
 544 #if 0
 545         case e1000_ich8lan:
 546                 {
 547                 int32_t  i = 0;
 548
 549                 eeprom->type = e1000_eeprom_ich8;
 550                 eeprom->use_eerd = FALSE;
 551                 eeprom->use_eewr = FALSE;
 552                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 553                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 554                                 ICH_FLASH_GFPREG);
 555                 /* Zero the shadow RAM structure. But don't load it from NVM
 556                  * so as to save time for driver init */
 557                 if (hw->eeprom_shadow_ram != NULL) {
 558                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 559                                 hw->eeprom_shadow_ram[i].modified = FALSE;
 560                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 561                         }
 562                 }
 563
 564                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 565                                 ICH_FLASH_SECTOR_SIZE;
 566
 567                 hw->flash_bank_size = ((flash_size >> 16)
 568                                 & ICH_GFPREG_BASE_MASK) + 1;
 569                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 570
 571                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 572
 573                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 574                 break;
 575                 }
 576 #endif
 577         default:
 578                 break;
 579         }
 580
 581         if (eeprom->type == e1000_eeprom_spi) {
 582                 /* eeprom_size will be an enum [0..8] that maps
 583                  * to eeprom sizes 128B to
 584                  * 32KB (incremented by powers of 2).
 585                  */
 586                 if (hw->mac_type <= e1000_82547_rev_2) {
 587                         /* Set to default value for initial eeprom read. */
 588                         eeprom->word_size = 64;
 589                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 590                                         &eeprom_size);
 591                         if (ret_val)
 592                                 return ret_val;
 593                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 594                                 >> EEPROM_SIZE_SHIFT;
 595                         /* 256B eeprom size was not supported in earlier
 596                          * hardware, so we bump eeprom_size up one to
 597                          * ensure that "1" (which maps to 256B) is never
 598                          * the result used in the shifting logic below. */
 599                         if (eeprom_size)
 600                                 eeprom_size++;
 601                 } else {
 602                         eeprom_size = (uint16_t)((eecd &
 603                                 E1000_EECD_SIZE_EX_MASK) >>
 604                                 E1000_EECD_SIZE_EX_SHIFT);
 605                 }
 606
 607                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 608         }
 609         return ret_val;
 610 }
 611
 612 /******************************************************************************
 613  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 614  *
 615  * hw - Struct containing variables accessed by shared code
 616  *****************************************************************************/
 617 static int32_t
 618 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 619 {
 620         uint32_t attempts = 100000;
 621         uint32_t i, reg = 0;
 622         int32_t done = E1000_ERR_EEPROM;
 623
 624         for (i = 0; i < attempts; i++) {
 625                 if (eerd == E1000_EEPROM_POLL_READ)
 626                         reg = E1000_READ_REG(hw, EERD);
 627                 else
 628                         reg = E1000_READ_REG(hw, EEWR);
 629
 630                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 631                         done = E1000_SUCCESS;
 632                         break;
 633                 }
 634                 udelay(5);
 635         }
 636
 637         return done;
 638 }
 639
 640 /******************************************************************************
 641  * Reads a 16 bit word from the EEPROM using the EERD register.
 642  *
 643  * hw - Struct containing variables accessed by shared code
 644  * offset - offset of  word in the EEPROM to read
 645  * data - word read from the EEPROM
 646  * words - number of words to read
 647  *****************************************************************************/
 648 static int32_t
 649 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 650                         uint16_t offset,
 651                         uint16_t words,
 652                         uint16_t *data)
 653 {
 654         uint32_t i, eerd = 0;
 655         int32_t error = 0;
 656
 657         for (i = 0; i < words; i++) {
 658                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 659                         E1000_EEPROM_RW_REG_START;
 660
 661                 E1000_WRITE_REG(hw, EERD, eerd);
 662                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 663
 664                 if (error)
 665                         break;
 666                 data[i] = (E1000_READ_REG(hw, EERD) >>
 667                                 E1000_EEPROM_RW_REG_DATA);
 668
 669         }
 670
 671         return error;
 672 }
 673
 674 static void
 675 e1000_release_eeprom(struct e1000_hw *hw)
 676 {
 677         uint32_t eecd;
 678
 679         DEBUGFUNC();
 680
 681         eecd = E1000_READ_REG(hw, EECD);
 682
 683         if (hw->eeprom.type == e1000_eeprom_spi) {
 684                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 685                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 686
 687                 E1000_WRITE_REG(hw, EECD, eecd);
 688
 689                 udelay(hw->eeprom.delay_usec);
 690         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 691                 /* cleanup eeprom */
 692
 693                 /* CS on Microwire is active-high */
 694                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 695
 696                 E1000_WRITE_REG(hw, EECD, eecd);
 697
 698                 /* Rising edge of clock */
 699                 eecd |= E1000_EECD_SK;
 700                 E1000_WRITE_REG(hw, EECD, eecd);
 701                 E1000_WRITE_FLUSH(hw);
 702                 udelay(hw->eeprom.delay_usec);
 703
 704                 /* Falling edge of clock */
 705                 eecd &= ~E1000_EECD_SK;
 706                 E1000_WRITE_REG(hw, EECD, eecd);
 707                 E1000_WRITE_FLUSH(hw);
 708                 udelay(hw->eeprom.delay_usec);
 709         }
 710
 711         /* Stop requesting EEPROM access */
 712         if (hw->mac_type > e1000_82544) {
 713                 eecd &= ~E1000_EECD_REQ;
 714                 E1000_WRITE_REG(hw, EECD, eecd);
 715         }
 716 }
 717 /******************************************************************************
 718  * Reads a 16 bit word from the EEPROM.
 719  *
 720  * hw - Struct containing variables accessed by shared code
 721  *****************************************************************************/
 722 static int32_t
 723 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 724 {
 725         uint16_t retry_count = 0;
 726         uint8_t spi_stat_reg;
 727
 728         DEBUGFUNC();
 729
 730         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 731          * EEPROM will signal that the command has been completed by clearing
 732          * bit 0 of the internal status register.  If it's not cleared within
 733          * 5 milliseconds, then error out.
 734          */
 735         retry_count = 0;
 736         do {
 737                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 738                         hw->eeprom.opcode_bits);
 739                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 740                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 741                         break;
 742
 743                 udelay(5);
 744                 retry_count += 5;
 745
 746                 e1000_standby_eeprom(hw);
 747         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 748
 749         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 750          * only 0-5mSec on 5V devices)
 751          */
 752         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 753                 DEBUGOUT("SPI EEPROM Status error\n");
 754                 return -E1000_ERR_EEPROM;
 755         }
 756
 757         return E1000_SUCCESS;
 758 }
 759
 760 /******************************************************************************
 761  * Reads a 16 bit word from the EEPROM.
 762  *
 763  * hw - Struct containing variables accessed by shared code
 764  * offset - offset of  word in the EEPROM to read
 765  * data - word read from the EEPROM
 766  *****************************************************************************/
 767 static int32_t
 768 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 769                 uint16_t words, uint16_t *data)
 770 {
 771         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 772         uint32_t i = 0;
 773
 774         DEBUGFUNC();
 775
 776         /* If eeprom is not yet detected, do so now */
 777         if (eeprom->word_size == 0)
 778                 e1000_init_eeprom_params(hw);
 779
 780         /* A check for invalid values:  offset too large, too many words,
 781          * and not enough words.
 782          */
 783         if ((offset >= eeprom->word_size) ||
 784                 (words > eeprom->word_size - offset) ||
 785                 (words == 0)) {
 786                 DEBUGOUT("\"words\" parameter out of bounds."
 787                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 788                 return -E1000_ERR_EEPROM;
 789         }
 790
 791         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 792          * directly. In this case, we need to acquire the EEPROM so that
 793          * FW or other port software does not interrupt.
 794          */
 795         if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
 796                 hw->eeprom.use_eerd == FALSE) {
 797
 798                 /* Prepare the EEPROM for bit-bang reading */
 799                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 800                         return -E1000_ERR_EEPROM;
 801         }
 802
 803         /* Eerd register EEPROM access requires no eeprom aquire/release */
 804         if (eeprom->use_eerd == TRUE)
 805                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 806
 807         /* ich8lan does not support currently. if needed, please
 808          * add corresponding code and functions.
 809          */
 810 #if 0
 811         /* ICH EEPROM access is done via the ICH flash controller */
 812         if (eeprom->type == e1000_eeprom_ich8)
 813                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 814 #endif
 815         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 816          * acquired the EEPROM at this point, so any returns should relase it */
 817         if (eeprom->type == e1000_eeprom_spi) {
 818                 uint16_t word_in;
 819                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 820
 821                 if (e1000_spi_eeprom_ready(hw)) {
 822                         e1000_release_eeprom(hw);
 823                         return -E1000_ERR_EEPROM;
 824                 }
 825
 826                 e1000_standby_eeprom(hw);
 827
 828                 /* Some SPI eeproms use the 8th address bit embedded in
 829                  * the opcode */
 830                 if ((eeprom->address_bits == 8) && (offset >= 128))
 831                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 832
 833                 /* Send the READ command (opcode + addr)  */
 834                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 835                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 836                                 eeprom->address_bits);
 837
 838                 /* Read the data.  The address of the eeprom internally
 839                  * increments with each byte (spi) being read, saving on the
 840                  * overhead of eeprom setup and tear-down.  The address
 841                  * counter will roll over if reading beyond the size of
 842                  * the eeprom, thus allowing the entire memory to be read
 843                  * starting from any offset. */
 844                 for (i = 0; i < words; i++) {
 845                         word_in = e1000_shift_in_ee_bits(hw, 16);
 846                         data[i] = (word_in >> 8) | (word_in << 8);
 847                 }
 848         } else if (eeprom->type == e1000_eeprom_microwire) {
 849                 for (i = 0; i < words; i++) {
 850                         /* Send the READ command (opcode + addr)  */
 851                         e1000_shift_out_ee_bits(hw,
 852                                 EEPROM_READ_OPCODE_MICROWIRE,
 853                                 eeprom->opcode_bits);
 854                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 855                                 eeprom->address_bits);
 856
 857                         /* Read the data.  For microwire, each word requires
 858                          * the overhead of eeprom setup and tear-down. */
 859                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 860                         e1000_standby_eeprom(hw);
 861                 }
 862         }
 863
 864         /* End this read operation */
 865         e1000_release_eeprom(hw);
 866
 867         return E1000_SUCCESS;
 868 }
 869
 870 /******************************************************************************
 871  * Verifies that the EEPROM has a valid checksum
 872  *
 873  * hw - Struct containing variables accessed by shared code
 874  *
 875  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 876  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 877  * valid.
 878  *****************************************************************************/
 879 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 880 {
 881         uint16_t i, checksum, checksum_reg, *buf;
 882
 883         DEBUGFUNC();
 884
 885         /* Allocate a temporary buffer */
 886         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
 887         if (!buf) {
 888                 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
 889                 return -E1000_ERR_EEPROM;
 890         }
 891
 892         /* Read the EEPROM */
 893         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
 894                 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
 895                 return -E1000_ERR_EEPROM;
 896         }
 897
 898         /* Compute the checksum */
 899         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
 900                 checksum += buf[i];
 901         checksum = ((uint16_t)EEPROM_SUM) - checksum;
 902         checksum_reg = buf[i];
 903
 904         /* Verify it! */
 905         if (checksum == checksum_reg)
 906                 return 0;
 907
 908         /* Hrm, verification failed, print an error */
 909         E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
 910         E1000_ERR(hw->nic, "  ...register was 0x%04hx, calculated 0x%04hx\n",
 911                         checksum_reg, checksum);
 912
 913         return -E1000_ERR_EEPROM;
 914 }
 915
 916 /*****************************************************************************
 917  * Set PHY to class A mode
 918  * Assumes the following operations will follow to enable the new class mode.
 919  *  1. Do a PHY soft reset
 920  *  2. Restart auto-negotiation or force link.
 921  *
 922  * hw - Struct containing variables accessed by shared code
 923  ****************************************************************************/
 924 static int32_t
 925 e1000_set_phy_mode(struct e1000_hw *hw)
 926 {
 927         int32_t ret_val;
 928         uint16_t eeprom_data;
 929
 930         DEBUGFUNC();
 931
 932         if ((hw->mac_type == e1000_82545_rev_3) &&
 933                 (hw->media_type == e1000_media_type_copper)) {
 934                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 935                                 1, &eeprom_data);
 936                 if (ret_val)
 937                         return ret_val;
 938
 939                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 940                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 941                         ret_val = e1000_write_phy_reg(hw,
 942                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 943                         if (ret_val)
 944                                 return ret_val;
 945                         ret_val = e1000_write_phy_reg(hw,
 946                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 947                         if (ret_val)
 948                                 return ret_val;
 949
 950                         hw->phy_reset_disable = FALSE;
 951                 }
 952         }
 953
 954         return E1000_SUCCESS;
 955 }
 956 #endif /* #ifndef CONFIG_AP1000 */
 957
 958 /***************************************************************************
 959  *
 960  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 961  *
 962  * hw: Struct containing variables accessed by shared code
 963  *
 964  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 965  *            E1000_SUCCESS at any other case.
 966  *
 967  ***************************************************************************/
 968 static int32_t
 969 e1000_get_software_semaphore(struct e1000_hw *hw)
 970 {
 971          int32_t timeout = hw->eeprom.word_size + 1;
 972          uint32_t swsm;
 973
 974         DEBUGFUNC();
 975
 976         if (hw->mac_type != e1000_80003es2lan)
 977                 return E1000_SUCCESS;
 978
 979         while (timeout) {
 980                 swsm = E1000_READ_REG(hw, SWSM);
 981                 /* If SMBI bit cleared, it is now set and we hold
 982                  * the semaphore */
 983                 if (!(swsm & E1000_SWSM_SMBI))
 984                         break;
 985                 mdelay(1);
 986                 timeout--;
 987         }
 988
 989         if (!timeout) {
 990                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 991                 return -E1000_ERR_RESET;
 992         }
 993
 994         return E1000_SUCCESS;
 995 }
 996
 997 /***************************************************************************
 998  * This function clears HW semaphore bits.
 999  *
1000  * hw: Struct containing variables accessed by shared code
1001  *
1002  * returns: - None.
1003  *
1004  ***************************************************************************/
1005 static void
1006 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1007 {
1008          uint32_t swsm;
1009
1010         DEBUGFUNC();
1011
1012         if (!hw->eeprom_semaphore_present)
1013                 return;
1014
1015         swsm = E1000_READ_REG(hw, SWSM);
1016         if (hw->mac_type == e1000_80003es2lan) {
1017                 /* Release both semaphores. */
1018                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1019         } else
1020                 swsm &= ~(E1000_SWSM_SWESMBI);
1021         E1000_WRITE_REG(hw, SWSM, swsm);
1022 }
1023
1024 /***************************************************************************
1025  *
1026  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1027  * adapter or Eeprom access.
1028  *
1029  * hw: Struct containing variables accessed by shared code
1030  *
1031  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1032  *            E1000_SUCCESS at any other case.
1033  *
1034  ***************************************************************************/
1035 static int32_t
1036 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1037 {
1038         int32_t timeout;
1039         uint32_t swsm;
1040
1041         DEBUGFUNC();
1042
1043         if (!hw->eeprom_semaphore_present)
1044                 return E1000_SUCCESS;
1045
1046         if (hw->mac_type == e1000_80003es2lan) {
1047                 /* Get the SW semaphore. */
1048                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1049                         return -E1000_ERR_EEPROM;
1050         }
1051
1052         /* Get the FW semaphore. */
1053         timeout = hw->eeprom.word_size + 1;
1054         while (timeout) {
1055                 swsm = E1000_READ_REG(hw, SWSM);
1056                 swsm |= E1000_SWSM_SWESMBI;
1057                 E1000_WRITE_REG(hw, SWSM, swsm);
1058                 /* if we managed to set the bit we got the semaphore. */
1059                 swsm = E1000_READ_REG(hw, SWSM);
1060                 if (swsm & E1000_SWSM_SWESMBI)
1061                         break;
1062
1063                 udelay(50);
1064                 timeout--;
1065         }
1066
1067         if (!timeout) {
1068                 /* Release semaphores */
1069                 e1000_put_hw_eeprom_semaphore(hw);
1070                 DEBUGOUT("Driver can't access the Eeprom - "
1071                                 "SWESMBI bit is set.\n");
1072                 return -E1000_ERR_EEPROM;
1073         }
1074
1075         return E1000_SUCCESS;
1076 }
1077
1078 static int32_t
1079 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1080 {
1081         uint32_t swfw_sync = 0;
1082         uint32_t swmask = mask;
1083         uint32_t fwmask = mask << 16;
1084         int32_t timeout = 200;
1085
1086         DEBUGFUNC();
1087         while (timeout) {
1088                 if (e1000_get_hw_eeprom_semaphore(hw))
1089                         return -E1000_ERR_SWFW_SYNC;
1090
1091                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1092                 if (!(swfw_sync & (fwmask | swmask)))
1093                         break;
1094
1095                 /* firmware currently using resource (fwmask) */
1096                 /* or other software thread currently using resource (swmask) */
1097                 e1000_put_hw_eeprom_semaphore(hw);
1098                 mdelay(5);
1099                 timeout--;
1100         }
1101
1102         if (!timeout) {
1103                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1104                 return -E1000_ERR_SWFW_SYNC;
1105         }
1106
1107         swfw_sync |= swmask;
1108         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1109
1110         e1000_put_hw_eeprom_semaphore(hw);
1111         return E1000_SUCCESS;
1112 }
1113
1114 static boolean_t e1000_is_second_port(struct e1000_hw *hw)
1115 {
1116         switch (hw->mac_type) {
1117         case e1000_80003es2lan:
1118         case e1000_82546:
1119         case e1000_82571:
1120                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1121                         return TRUE;
1122                 /* Fallthrough */
1123         default:
1124                 return FALSE;
1125         }
1126 }
1127
1128 /******************************************************************************
1129  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1130  * second function of dual function devices
1131  *
1132  * nic - Struct containing variables accessed by shared code
1133  *****************************************************************************/
1134 static int
1135 e1000_read_mac_addr(struct eth_device *nic)
1136 {
1137 #ifndef CONFIG_AP1000
1138         struct e1000_hw *hw = nic->priv;
1139         uint16_t offset;
1140         uint16_t eeprom_data;
1141         int i;
1142
1143         DEBUGFUNC();
1144
1145         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1146                 offset = i >> 1;
1147                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1148                         DEBUGOUT("EEPROM Read Error\n");
1149                         return -E1000_ERR_EEPROM;
1150                 }
1151                 nic->enetaddr[i] = eeprom_data & 0xff;
1152                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1153         }
1154
1155         /* Invert the last bit if this is the second device */
1156         if (e1000_is_second_port(hw))
1157                 nic->enetaddr[5] ^= 1;
1158
1159 #ifdef CONFIG_E1000_FALLBACK_MAC
1160         if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
1161                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1162
1163                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1164         }
1165 #endif
1166 #else
1167         /*
1168          * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1169          * environment variables.  Currently this does not support the addition
1170          * of a PMC e1000 card, which is certainly a possibility, so this should
1171          * be updated to properly use the env variable only for the onboard e1000
1172          */
1173
1174         int ii;
1175         char *s, *e;
1176
1177         DEBUGFUNC();
1178
1179         s = getenv ("ethaddr");
1180         if (s == NULL) {
1181                 return -E1000_ERR_EEPROM;
1182         } else {
1183                 for(ii = 0; ii < 6; ii++) {
1184                         nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1185                         if (s){
1186                                 s = (*e) ? e + 1 : e;
1187                         }
1188                 }
1189         }
1190 #endif
1191         return 0;
1192 }
1193
1194 /******************************************************************************
1195  * Initializes receive address filters.
1196  *
1197  * hw - Struct containing variables accessed by shared code
1198  *
1199  * Places the MAC address in receive address register 0 and clears the rest
1200  * of the receive addresss registers. Clears the multicast table. Assumes
1201  * the receiver is in reset when the routine is called.
1202  *****************************************************************************/
1203 static void
1204 e1000_init_rx_addrs(struct eth_device *nic)
1205 {
1206         struct e1000_hw *hw = nic->priv;
1207         uint32_t i;
1208         uint32_t addr_low;
1209         uint32_t addr_high;
1210
1211         DEBUGFUNC();
1212
1213         /* Setup the receive address. */
1214         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1215         addr_low = (nic->enetaddr[0] |
1216                     (nic->enetaddr[1] << 8) |
1217                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1218
1219         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1220
1221         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1222         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1223
1224         /* Zero out the other 15 receive addresses. */
1225         DEBUGOUT("Clearing RAR[1-15]\n");
1226         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1227                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1228                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1229         }
1230 }
1231
1232 /******************************************************************************
1233  * Clears the VLAN filer table
1234  *
1235  * hw - Struct containing variables accessed by shared code
1236  *****************************************************************************/
1237 static void
1238 e1000_clear_vfta(struct e1000_hw *hw)
1239 {
1240         uint32_t offset;
1241
1242         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1243                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1244 }
1245
1246 /******************************************************************************
1247  * Set the mac type member in the hw struct.
1248  *
1249  * hw - Struct containing variables accessed by shared code
1250  *****************************************************************************/
1251 int32_t
1252 e1000_set_mac_type(struct e1000_hw *hw)
1253 {
1254         DEBUGFUNC();
1255
1256         switch (hw->device_id) {
1257         case E1000_DEV_ID_82542:
1258                 switch (hw->revision_id) {
1259                 case E1000_82542_2_0_REV_ID:
1260                         hw->mac_type = e1000_82542_rev2_0;
1261                         break;
1262                 case E1000_82542_2_1_REV_ID:
1263                         hw->mac_type = e1000_82542_rev2_1;
1264                         break;
1265                 default:
1266                         /* Invalid 82542 revision ID */
1267                         return -E1000_ERR_MAC_TYPE;
1268                 }
1269                 break;
1270         case E1000_DEV_ID_82543GC_FIBER:
1271         case E1000_DEV_ID_82543GC_COPPER:
1272                 hw->mac_type = e1000_82543;
1273                 break;
1274         case E1000_DEV_ID_82544EI_COPPER:
1275         case E1000_DEV_ID_82544EI_FIBER:
1276         case E1000_DEV_ID_82544GC_COPPER:
1277         case E1000_DEV_ID_82544GC_LOM:
1278                 hw->mac_type = e1000_82544;
1279                 break;
1280         case E1000_DEV_ID_82540EM:
1281         case E1000_DEV_ID_82540EM_LOM:
1282         case E1000_DEV_ID_82540EP:
1283         case E1000_DEV_ID_82540EP_LOM:
1284         case E1000_DEV_ID_82540EP_LP:
1285                 hw->mac_type = e1000_82540;
1286                 break;
1287         case E1000_DEV_ID_82545EM_COPPER:
1288         case E1000_DEV_ID_82545EM_FIBER:
1289                 hw->mac_type = e1000_82545;
1290                 break;
1291         case E1000_DEV_ID_82545GM_COPPER:
1292         case E1000_DEV_ID_82545GM_FIBER:
1293         case E1000_DEV_ID_82545GM_SERDES:
1294                 hw->mac_type = e1000_82545_rev_3;
1295                 break;
1296         case E1000_DEV_ID_82546EB_COPPER:
1297         case E1000_DEV_ID_82546EB_FIBER:
1298         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1299                 hw->mac_type = e1000_82546;
1300                 break;
1301         case E1000_DEV_ID_82546GB_COPPER:
1302         case E1000_DEV_ID_82546GB_FIBER:
1303         case E1000_DEV_ID_82546GB_SERDES:
1304         case E1000_DEV_ID_82546GB_PCIE:
1305         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1306         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1307                 hw->mac_type = e1000_82546_rev_3;
1308                 break;
1309         case E1000_DEV_ID_82541EI:
1310         case E1000_DEV_ID_82541EI_MOBILE:
1311         case E1000_DEV_ID_82541ER_LOM:
1312                 hw->mac_type = e1000_82541;
1313                 break;
1314         case E1000_DEV_ID_82541ER:
1315         case E1000_DEV_ID_82541GI:
1316         case E1000_DEV_ID_82541GI_LF:
1317         case E1000_DEV_ID_82541GI_MOBILE:
1318                 hw->mac_type = e1000_82541_rev_2;
1319                 break;
1320         case E1000_DEV_ID_82547EI:
1321         case E1000_DEV_ID_82547EI_MOBILE:
1322                 hw->mac_type = e1000_82547;
1323                 break;
1324         case E1000_DEV_ID_82547GI:
1325                 hw->mac_type = e1000_82547_rev_2;
1326                 break;
1327         case E1000_DEV_ID_82571EB_COPPER:
1328         case E1000_DEV_ID_82571EB_FIBER:
1329         case E1000_DEV_ID_82571EB_SERDES:
1330         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1331         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1332         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1333         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1334         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1335         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1336                 hw->mac_type = e1000_82571;
1337                 break;
1338         case E1000_DEV_ID_82572EI_COPPER:
1339         case E1000_DEV_ID_82572EI_FIBER:
1340         case E1000_DEV_ID_82572EI_SERDES:
1341         case E1000_DEV_ID_82572EI:
1342                 hw->mac_type = e1000_82572;
1343                 break;
1344         case E1000_DEV_ID_82573E:
1345         case E1000_DEV_ID_82573E_IAMT:
1346         case E1000_DEV_ID_82573L:
1347                 hw->mac_type = e1000_82573;
1348                 break;
1349         case E1000_DEV_ID_82574L:
1350                 hw->mac_type = e1000_82574;
1351                 break;
1352         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1353         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1354         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1355         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1356                 hw->mac_type = e1000_80003es2lan;
1357                 break;
1358         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1359         case E1000_DEV_ID_ICH8_IGP_AMT:
1360         case E1000_DEV_ID_ICH8_IGP_C:
1361         case E1000_DEV_ID_ICH8_IFE:
1362         case E1000_DEV_ID_ICH8_IFE_GT:
1363         case E1000_DEV_ID_ICH8_IFE_G:
1364         case E1000_DEV_ID_ICH8_IGP_M:
1365                 hw->mac_type = e1000_ich8lan;
1366                 break;
1367         default:
1368                 /* Should never have loaded on this device */
1369                 return -E1000_ERR_MAC_TYPE;
1370         }
1371         return E1000_SUCCESS;
1372 }
1373
1374 /******************************************************************************
1375  * Reset the transmit and receive units; mask and clear all interrupts.
1376  *
1377  * hw - Struct containing variables accessed by shared code
1378  *****************************************************************************/
1379 void
1380 e1000_reset_hw(struct e1000_hw *hw)
1381 {
1382         uint32_t ctrl;
1383         uint32_t ctrl_ext;
1384         uint32_t icr;
1385         uint32_t manc;
1386         uint32_t pba = 0;
1387
1388         DEBUGFUNC();
1389
1390         /* get the correct pba value for both PCI and PCIe*/
1391         if (hw->mac_type <  e1000_82571)
1392                 pba = E1000_DEFAULT_PCI_PBA;
1393         else
1394                 pba = E1000_DEFAULT_PCIE_PBA;
1395
1396         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1397         if (hw->mac_type == e1000_82542_rev2_0) {
1398                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1399                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1400                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1401         }
1402
1403         /* Clear interrupt mask to stop board from generating interrupts */
1404         DEBUGOUT("Masking off all interrupts\n");
1405         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1406
1407         /* Disable the Transmit and Receive units.  Then delay to allow
1408          * any pending transactions to complete before we hit the MAC with
1409          * the global reset.
1410          */
1411         E1000_WRITE_REG(hw, RCTL, 0);
1412         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1413         E1000_WRITE_FLUSH(hw);
1414
1415         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1416         hw->tbi_compatibility_on = FALSE;
1417
1418         /* Delay to allow any outstanding PCI transactions to complete before
1419          * resetting the device
1420          */
1421         mdelay(10);
1422
1423         /* Issue a global reset to the MAC.  This will reset the chip's
1424          * transmit, receive, DMA, and link units.  It will not effect
1425          * the current PCI configuration.  The global reset bit is self-
1426          * clearing, and should clear within a microsecond.
1427          */
1428         DEBUGOUT("Issuing a global reset to MAC\n");
1429         ctrl = E1000_READ_REG(hw, CTRL);
1430
1431         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1432
1433         /* Force a reload from the EEPROM if necessary */
1434         if (hw->mac_type < e1000_82540) {
1435                 /* Wait for reset to complete */
1436                 udelay(10);
1437                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1438                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1439                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1440                 E1000_WRITE_FLUSH(hw);
1441                 /* Wait for EEPROM reload */
1442                 mdelay(2);
1443         } else {
1444                 /* Wait for EEPROM reload (it happens automatically) */
1445                 mdelay(4);
1446                 /* Dissable HW ARPs on ASF enabled adapters */
1447                 manc = E1000_READ_REG(hw, MANC);
1448                 manc &= ~(E1000_MANC_ARP_EN);
1449                 E1000_WRITE_REG(hw, MANC, manc);
1450         }
1451
1452         /* Clear interrupt mask to stop board from generating interrupts */
1453         DEBUGOUT("Masking off all interrupts\n");
1454         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1455
1456         /* Clear any pending interrupt events. */
1457         icr = E1000_READ_REG(hw, ICR);
1458
1459         /* If MWI was previously enabled, reenable it. */
1460         if (hw->mac_type == e1000_82542_rev2_0) {
1461                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1462         }
1463         E1000_WRITE_REG(hw, PBA, pba);
1464 }
1465
1466 /******************************************************************************
1467  *
1468  * Initialize a number of hardware-dependent bits
1469  *
1470  * hw: Struct containing variables accessed by shared code
1471  *
1472  * This function contains hardware limitation workarounds for PCI-E adapters
1473  *
1474  *****************************************************************************/
1475 static void
1476 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1477 {
1478         if ((hw->mac_type >= e1000_82571) &&
1479                         (!hw->initialize_hw_bits_disable)) {
1480                 /* Settings common to all PCI-express silicon */
1481                 uint32_t reg_ctrl, reg_ctrl_ext;
1482                 uint32_t reg_tarc0, reg_tarc1;
1483                 uint32_t reg_tctl;
1484                 uint32_t reg_txdctl, reg_txdctl1;
1485
1486                 /* link autonegotiation/sync workarounds */
1487                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1488                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1489
1490                 /* Enable not-done TX descriptor counting */
1491                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1492                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1493                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1494
1495                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1496                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1497                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1498
1499                 switch (hw->mac_type) {
1500                 case e1000_82571:
1501                 case e1000_82572:
1502                         /* Clear PHY TX compatible mode bits */
1503                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1504                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1505
1506                         /* link autonegotiation/sync workarounds */
1507                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1508
1509                         /* TX ring control fixes */
1510                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1511
1512                         /* Multiple read bit is reversed polarity */
1513                         reg_tctl = E1000_READ_REG(hw, TCTL);
1514                         if (reg_tctl & E1000_TCTL_MULR)
1515                                 reg_tarc1 &= ~(1 << 28);
1516                         else
1517                                 reg_tarc1 |= (1 << 28);
1518
1519                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1520                         break;
1521                 case e1000_82573:
1522                 case e1000_82574:
1523                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1524                         reg_ctrl_ext &= ~(1 << 23);
1525                         reg_ctrl_ext |= (1 << 22);
1526
1527                         /* TX byte count fix */
1528                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1529                         reg_ctrl &= ~(1 << 29);
1530
1531                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1532                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1533                         break;
1534                 case e1000_80003es2lan:
1535         /* improve small packet performace for fiber/serdes */
1536                         if ((hw->media_type == e1000_media_type_fiber)
1537                         || (hw->media_type ==
1538                                 e1000_media_type_internal_serdes)) {
1539                                 reg_tarc0 &= ~(1 << 20);
1540                         }
1541
1542                 /* Multiple read bit is reversed polarity */
1543                         reg_tctl = E1000_READ_REG(hw, TCTL);
1544                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1545                         if (reg_tctl & E1000_TCTL_MULR)
1546                                 reg_tarc1 &= ~(1 << 28);
1547                         else
1548                                 reg_tarc1 |= (1 << 28);
1549
1550                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1551                         break;
1552                 case e1000_ich8lan:
1553                         /* Reduce concurrent DMA requests to 3 from 4 */
1554                         if ((hw->revision_id < 3) ||
1555                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1556                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1557                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1558
1559                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1560                         reg_ctrl_ext |= (1 << 22);
1561                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1562
1563                         /* workaround TX hang with TSO=on */
1564                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1565
1566                         /* Multiple read bit is reversed polarity */
1567                         reg_tctl = E1000_READ_REG(hw, TCTL);
1568                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1569                         if (reg_tctl & E1000_TCTL_MULR)
1570                                 reg_tarc1 &= ~(1 << 28);
1571                         else
1572                                 reg_tarc1 |= (1 << 28);
1573
1574                         /* workaround TX hang with TSO=on */
1575                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1576
1577                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1578                         break;
1579                 default:
1580                         break;
1581                 }
1582
1583                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1584         }
1585 }
1586
1587 /******************************************************************************
1588  * Performs basic configuration of the adapter.
1589  *
1590  * hw - Struct containing variables accessed by shared code
1591  *
1592  * Assumes that the controller has previously been reset and is in a
1593  * post-reset uninitialized state. Initializes the receive address registers,
1594  * multicast table, and VLAN filter table. Calls routines to setup link
1595  * configuration and flow control settings. Clears all on-chip counters. Leaves
1596  * the transmit and receive units disabled and uninitialized.
1597  *****************************************************************************/
1598 static int
1599 e1000_init_hw(struct eth_device *nic)
1600 {
1601         struct e1000_hw *hw = nic->priv;
1602         uint32_t ctrl;
1603         uint32_t i;
1604         int32_t ret_val;
1605         uint16_t pcix_cmd_word;
1606         uint16_t pcix_stat_hi_word;
1607         uint16_t cmd_mmrbc;
1608         uint16_t stat_mmrbc;
1609         uint32_t mta_size;
1610         uint32_t reg_data;
1611         uint32_t ctrl_ext;
1612         DEBUGFUNC();
1613         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1614         if ((hw->mac_type == e1000_ich8lan) &&
1615                 ((hw->revision_id < 3) ||
1616                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1617                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1618                         reg_data = E1000_READ_REG(hw, STATUS);
1619                         reg_data &= ~0x80000000;
1620                         E1000_WRITE_REG(hw, STATUS, reg_data);
1621         }
1622         /* Do not need initialize Identification LED */
1623
1624         /* Set the media type and TBI compatibility */
1625         e1000_set_media_type(hw);
1626
1627         /* Must be called after e1000_set_media_type
1628          * because media_type is used */
1629         e1000_initialize_hardware_bits(hw);
1630
1631         /* Disabling VLAN filtering. */
1632         DEBUGOUT("Initializing the IEEE VLAN\n");
1633         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1634         if (hw->mac_type != e1000_ich8lan) {
1635                 if (hw->mac_type < e1000_82545_rev_3)
1636                         E1000_WRITE_REG(hw, VET, 0);
1637                 e1000_clear_vfta(hw);
1638         }
1639
1640         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1641         if (hw->mac_type == e1000_82542_rev2_0) {
1642                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1643                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1644                                       hw->
1645                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1646                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1647                 E1000_WRITE_FLUSH(hw);
1648                 mdelay(5);
1649         }
1650
1651         /* Setup the receive address. This involves initializing all of the Receive
1652          * Address Registers (RARs 0 - 15).
1653          */
1654         e1000_init_rx_addrs(nic);
1655
1656         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1657         if (hw->mac_type == e1000_82542_rev2_0) {
1658                 E1000_WRITE_REG(hw, RCTL, 0);
1659                 E1000_WRITE_FLUSH(hw);
1660                 mdelay(1);
1661                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1662         }
1663
1664         /* Zero out the Multicast HASH table */
1665         DEBUGOUT("Zeroing the MTA\n");
1666         mta_size = E1000_MC_TBL_SIZE;
1667         if (hw->mac_type == e1000_ich8lan)
1668                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1669         for (i = 0; i < mta_size; i++) {
1670                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1671                 /* use write flush to prevent Memory Write Block (MWB) from
1672                  * occuring when accessing our register space */
1673                 E1000_WRITE_FLUSH(hw);
1674         }
1675 #if 0
1676         /* Set the PCI priority bit correctly in the CTRL register.  This
1677          * determines if the adapter gives priority to receives, or if it
1678          * gives equal priority to transmits and receives.  Valid only on
1679          * 82542 and 82543 silicon.
1680          */
1681         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1682                 ctrl = E1000_READ_REG(hw, CTRL);
1683                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1684         }
1685 #endif
1686         switch (hw->mac_type) {
1687         case e1000_82545_rev_3:
1688         case e1000_82546_rev_3:
1689                 break;
1690         default:
1691         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1692         if (hw->bus_type == e1000_bus_type_pcix) {
1693                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1694                                      &pcix_cmd_word);
1695                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1696                                      &pcix_stat_hi_word);
1697                 cmd_mmrbc =
1698                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1699                     PCIX_COMMAND_MMRBC_SHIFT;
1700                 stat_mmrbc =
1701                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1702                     PCIX_STATUS_HI_MMRBC_SHIFT;
1703                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1704                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1705                 if (cmd_mmrbc > stat_mmrbc) {
1706                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1707                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1708                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1709                                               pcix_cmd_word);
1710                 }
1711         }
1712                 break;
1713         }
1714
1715         /* More time needed for PHY to initialize */
1716         if (hw->mac_type == e1000_ich8lan)
1717                 mdelay(15);
1718
1719         /* Call a subroutine to configure the link and setup flow control. */
1720         ret_val = e1000_setup_link(nic);
1721
1722         /* Set the transmit descriptor write-back policy */
1723         if (hw->mac_type > e1000_82544) {
1724                 ctrl = E1000_READ_REG(hw, TXDCTL);
1725                 ctrl =
1726                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1727                     E1000_TXDCTL_FULL_TX_DESC_WB;
1728                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1729         }
1730
1731         switch (hw->mac_type) {
1732         default:
1733                 break;
1734         case e1000_80003es2lan:
1735                 /* Enable retransmit on late collisions */
1736                 reg_data = E1000_READ_REG(hw, TCTL);
1737                 reg_data |= E1000_TCTL_RTLC;
1738                 E1000_WRITE_REG(hw, TCTL, reg_data);
1739
1740                 /* Configure Gigabit Carry Extend Padding */
1741                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1742                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1743                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1744                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1745
1746                 /* Configure Transmit Inter-Packet Gap */
1747                 reg_data = E1000_READ_REG(hw, TIPG);
1748                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1749                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1750                 E1000_WRITE_REG(hw, TIPG, reg_data);
1751
1752                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1753                 reg_data &= ~0x00100000;
1754                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1755                 /* Fall through */
1756         case e1000_82571:
1757         case e1000_82572:
1758         case e1000_ich8lan:
1759                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1760                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1761                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1762                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1763                 break;
1764         case e1000_82573:
1765         case e1000_82574:
1766                 reg_data = E1000_READ_REG(hw, GCR);
1767                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1768                 E1000_WRITE_REG(hw, GCR, reg_data);
1769         }
1770
1771 #if 0
1772         /* Clear all of the statistics registers (clear on read).  It is
1773          * important that we do this after we have tried to establish link
1774          * because the symbol error count will increment wildly if there
1775          * is no link.
1776          */
1777         e1000_clear_hw_cntrs(hw);
1778
1779         /* ICH8 No-snoop bits are opposite polarity.
1780          * Set to snoop by default after reset. */
1781         if (hw->mac_type == e1000_ich8lan)
1782                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1783 #endif
1784
1785         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1786                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1787                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1788                 /* Relaxed ordering must be disabled to avoid a parity
1789                  * error crash in a PCI slot. */
1790                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1791                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1792         }
1793
1794         return ret_val;
1795 }
1796
1797 /******************************************************************************
1798  * Configures flow control and link settings.
1799  *
1800  * hw - Struct containing variables accessed by shared code
1801  *
1802  * Determines which flow control settings to use. Calls the apropriate media-
1803  * specific link configuration function. Configures the flow control settings.
1804  * Assuming the adapter has a valid link partner, a valid link should be
1805  * established. Assumes the hardware has previously been reset and the
1806  * transmitter and receiver are not enabled.
1807  *****************************************************************************/
1808 static int
1809 e1000_setup_link(struct eth_device *nic)
1810 {
1811         struct e1000_hw *hw = nic->priv;
1812         uint32_t ctrl_ext;
1813         int32_t ret_val;
1814         uint16_t eeprom_data;
1815
1816         DEBUGFUNC();
1817
1818         /* In the case of the phy reset being blocked, we already have a link.
1819          * We do not have to set it up again. */
1820         if (e1000_check_phy_reset_block(hw))
1821                 return E1000_SUCCESS;
1822
1823 #ifndef CONFIG_AP1000
1824         /* Read and store word 0x0F of the EEPROM. This word contains bits
1825          * that determine the hardware's default PAUSE (flow control) mode,
1826          * a bit that determines whether the HW defaults to enabling or
1827          * disabling auto-negotiation, and the direction of the
1828          * SW defined pins. If there is no SW over-ride of the flow
1829          * control setting, then the variable hw->fc will
1830          * be initialized based on a value in the EEPROM.
1831          */
1832         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1833                                 &eeprom_data) < 0) {
1834                 DEBUGOUT("EEPROM Read Error\n");
1835                 return -E1000_ERR_EEPROM;
1836         }
1837 #else
1838         /* we have to hardcode the proper value for our hardware. */
1839         /* this value is for the 82540EM pci card used for prototyping, and it works. */
1840         eeprom_data = 0xb220;
1841 #endif
1842
1843         if (hw->fc == e1000_fc_default) {
1844                 switch (hw->mac_type) {
1845                 case e1000_ich8lan:
1846                 case e1000_82573:
1847                 case e1000_82574:
1848                         hw->fc = e1000_fc_full;
1849                         break;
1850                 default:
1851 #ifndef CONFIG_AP1000
1852                         ret_val = e1000_read_eeprom(hw,
1853                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1854                         if (ret_val) {
1855                                 DEBUGOUT("EEPROM Read Error\n");
1856                                 return -E1000_ERR_EEPROM;
1857                         }
1858 #else
1859                         eeprom_data = 0xb220;
1860 #endif
1861                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1862                                 hw->fc = e1000_fc_none;
1863                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1864                                     EEPROM_WORD0F_ASM_DIR)
1865                                 hw->fc = e1000_fc_tx_pause;
1866                         else
1867                                 hw->fc = e1000_fc_full;
1868                         break;
1869                 }
1870         }
1871
1872         /* We want to save off the original Flow Control configuration just
1873          * in case we get disconnected and then reconnected into a different
1874          * hub or switch with different Flow Control capabilities.
1875          */
1876         if (hw->mac_type == e1000_82542_rev2_0)
1877                 hw->fc &= (~e1000_fc_tx_pause);
1878
1879         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1880                 hw->fc &= (~e1000_fc_rx_pause);
1881
1882         hw->original_fc = hw->fc;
1883
1884         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1885
1886         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1887          * polarity value for the SW controlled pins, and setup the
1888          * Extended Device Control reg with that info.
1889          * This is needed because one of the SW controlled pins is used for
1890          * signal detection.  So this should be done before e1000_setup_pcs_link()
1891          * or e1000_phy_setup() is called.
1892          */
1893         if (hw->mac_type == e1000_82543) {
1894                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1895                             SWDPIO__EXT_SHIFT);
1896                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1897         }
1898
1899         /* Call the necessary subroutine to configure the link. */
1900         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1901             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1902         if (ret_val < 0) {
1903                 return ret_val;
1904         }
1905
1906         /* Initialize the flow control address, type, and PAUSE timer
1907          * registers to their default values.  This is done even if flow
1908          * control is disabled, because it does not hurt anything to
1909          * initialize these registers.
1910          */
1911         DEBUGOUT("Initializing the Flow Control address, type"
1912                         "and timer regs\n");
1913
1914         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1915         if (hw->mac_type != e1000_ich8lan) {
1916                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1917                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1918                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1919         }
1920
1921         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1922
1923         /* Set the flow control receive threshold registers.  Normally,
1924          * these registers will be set to a default threshold that may be
1925          * adjusted later by the driver's runtime code.  However, if the
1926          * ability to transmit pause frames in not enabled, then these
1927          * registers will be set to 0.
1928          */
1929         if (!(hw->fc & e1000_fc_tx_pause)) {
1930                 E1000_WRITE_REG(hw, FCRTL, 0);
1931                 E1000_WRITE_REG(hw, FCRTH, 0);
1932         } else {
1933                 /* We need to set up the Receive Threshold high and low water marks
1934                  * as well as (optionally) enabling the transmission of XON frames.
1935                  */
1936                 if (hw->fc_send_xon) {
1937                         E1000_WRITE_REG(hw, FCRTL,
1938                                         (hw->fc_low_water | E1000_FCRTL_XONE));
1939                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1940                 } else {
1941                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1942                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1943                 }
1944         }
1945         return ret_val;
1946 }
1947
1948 /******************************************************************************
1949  * Sets up link for a fiber based adapter
1950  *
1951  * hw - Struct containing variables accessed by shared code
1952  *
1953  * Manipulates Physical Coding Sublayer functions in order to configure
1954  * link. Assumes the hardware has been previously reset and the transmitter
1955  * and receiver are not enabled.
1956  *****************************************************************************/
1957 static int
1958 e1000_setup_fiber_link(struct eth_device *nic)
1959 {
1960         struct e1000_hw *hw = nic->priv;
1961         uint32_t ctrl;
1962         uint32_t status;
1963         uint32_t txcw = 0;
1964         uint32_t i;
1965         uint32_t signal;
1966         int32_t ret_val;
1967
1968         DEBUGFUNC();
1969         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1970          * set when the optics detect a signal. On older adapters, it will be
1971          * cleared when there is a signal
1972          */
1973         ctrl = E1000_READ_REG(hw, CTRL);
1974         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1975                 signal = E1000_CTRL_SWDPIN1;
1976         else
1977                 signal = 0;
1978
1979         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1980                ctrl);
1981         /* Take the link out of reset */
1982         ctrl &= ~(E1000_CTRL_LRST);
1983
1984         e1000_config_collision_dist(hw);
1985
1986         /* Check for a software override of the flow control settings, and setup
1987          * the device accordingly.  If auto-negotiation is enabled, then software
1988          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1989          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1990          * auto-negotiation is disabled, then software will have to manually
1991          * configure the two flow control enable bits in the CTRL register.
1992          *
1993          * The possible values of the "fc" parameter are:
1994          *      0:  Flow control is completely disabled
1995          *      1:  Rx flow control is enabled (we can receive pause frames, but
1996          *          not send pause frames).
1997          *      2:  Tx flow control is enabled (we can send pause frames but we do
1998          *          not support receiving pause frames).
1999          *      3:  Both Rx and TX flow control (symmetric) are enabled.
2000          */
2001         switch (hw->fc) {
2002         case e1000_fc_none:
2003                 /* Flow control is completely disabled by a software over-ride. */
2004                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2005                 break;
2006         case e1000_fc_rx_pause:
2007                 /* RX Flow control is enabled and TX Flow control is disabled by a
2008                  * software over-ride. Since there really isn't a way to advertise
2009                  * that we are capable of RX Pause ONLY, we will advertise that we
2010                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2011                  *  disable the adapter's ability to send PAUSE frames.
2012                  */
2013                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2014                 break;
2015         case e1000_fc_tx_pause:
2016                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2017                  * software over-ride.
2018                  */
2019                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2020                 break;
2021         case e1000_fc_full:
2022                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2023                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2024                 break;
2025         default:
2026                 DEBUGOUT("Flow control param set incorrectly\n");
2027                 return -E1000_ERR_CONFIG;
2028                 break;
2029         }
2030
2031         /* Since auto-negotiation is enabled, take the link out of reset (the link
2032          * will be in reset, because we previously reset the chip). This will
2033          * restart auto-negotiation.  If auto-neogtiation is successful then the
2034          * link-up status bit will be set and the flow control enable bits (RFCE
2035          * and TFCE) will be set according to their negotiated value.
2036          */
2037         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2038
2039         E1000_WRITE_REG(hw, TXCW, txcw);
2040         E1000_WRITE_REG(hw, CTRL, ctrl);
2041         E1000_WRITE_FLUSH(hw);
2042
2043         hw->txcw = txcw;
2044         mdelay(1);
2045
2046         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2047          * indication in the Device Status Register.  Time-out if a link isn't
2048          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2049          * less than 500 milliseconds even if the other end is doing it in SW).
2050          */
2051         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2052                 DEBUGOUT("Looking for Link\n");
2053                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2054                         mdelay(10);
2055                         status = E1000_READ_REG(hw, STATUS);
2056                         if (status & E1000_STATUS_LU)
2057                                 break;
2058                 }
2059                 if (i == (LINK_UP_TIMEOUT / 10)) {
2060                         /* AutoNeg failed to achieve a link, so we'll call
2061                          * e1000_check_for_link. This routine will force the link up if we
2062                          * detect a signal. This will allow us to communicate with
2063                          * non-autonegotiating link partners.
2064                          */
2065                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2066                         hw->autoneg_failed = 1;
2067                         ret_val = e1000_check_for_link(nic);
2068                         if (ret_val < 0) {
2069                                 DEBUGOUT("Error while checking for link\n");
2070                                 return ret_val;
2071                         }
2072                         hw->autoneg_failed = 0;
2073                 } else {
2074                         hw->autoneg_failed = 0;
2075                         DEBUGOUT("Valid Link Found\n");
2076                 }
2077         } else {
2078                 DEBUGOUT("No Signal Detected\n");
2079                 return -E1000_ERR_NOLINK;
2080         }
2081         return 0;
2082 }
2083
2084 /******************************************************************************
2085 * Make sure we have a valid PHY and change PHY mode before link setup.
2086 *
2087 * hw - Struct containing variables accessed by shared code
2088 ******************************************************************************/
2089 static int32_t
2090 e1000_copper_link_preconfig(struct e1000_hw *hw)
2091 {
2092         uint32_t ctrl;
2093         int32_t ret_val;
2094         uint16_t phy_data;
2095
2096         DEBUGFUNC();
2097
2098         ctrl = E1000_READ_REG(hw, CTRL);
2099         /* With 82543, we need to force speed and duplex on the MAC equal to what
2100          * the PHY speed and duplex configuration is. In addition, we need to
2101          * perform a hardware reset on the PHY to take it out of reset.
2102          */
2103         if (hw->mac_type > e1000_82543) {
2104                 ctrl |= E1000_CTRL_SLU;
2105                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2106                 E1000_WRITE_REG(hw, CTRL, ctrl);
2107         } else {
2108                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2109                                 | E1000_CTRL_SLU);
2110                 E1000_WRITE_REG(hw, CTRL, ctrl);
2111                 ret_val = e1000_phy_hw_reset(hw);
2112                 if (ret_val)
2113                         return ret_val;
2114         }
2115
2116         /* Make sure we have a valid PHY */
2117         ret_val = e1000_detect_gig_phy(hw);
2118         if (ret_val) {
2119                 DEBUGOUT("Error, did not detect valid phy.\n");
2120                 return ret_val;
2121         }
2122         DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2123
2124 #ifndef CONFIG_AP1000
2125         /* Set PHY to class A mode (if necessary) */
2126         ret_val = e1000_set_phy_mode(hw);
2127         if (ret_val)
2128                 return ret_val;
2129 #endif
2130         if ((hw->mac_type == e1000_82545_rev_3) ||
2131                 (hw->mac_type == e1000_82546_rev_3)) {
2132                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2133                                 &phy_data);
2134                 phy_data |= 0x00000008;
2135                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2136                                 phy_data);
2137         }
2138
2139         if (hw->mac_type <= e1000_82543 ||
2140                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2141                 hw->mac_type == e1000_82541_rev_2
2142                 || hw->mac_type == e1000_82547_rev_2)
2143                         hw->phy_reset_disable = FALSE;
2144
2145         return E1000_SUCCESS;
2146 }
2147
2148 /*****************************************************************************
2149  *
2150  * This function sets the lplu state according to the active flag.  When
2151  * activating lplu this function also disables smart speed and vise versa.
2152  * lplu will not be activated unless the device autonegotiation advertisment
2153  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2154  * hw: Struct containing variables accessed by shared code
2155  * active - true to enable lplu false to disable lplu.
2156  *
2157  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2158  *            E1000_SUCCESS at any other case.
2159  *
2160  ****************************************************************************/
2161
2162 static int32_t
2163 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2164 {
2165         uint32_t phy_ctrl = 0;
2166         int32_t ret_val;
2167         uint16_t phy_data;
2168         DEBUGFUNC();
2169
2170         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2171             && hw->phy_type != e1000_phy_igp_3)
2172                 return E1000_SUCCESS;
2173
2174         /* During driver activity LPLU should not be used or it will attain link
2175          * from the lowest speeds starting from 10Mbps. The capability is used
2176          * for Dx transitions and states */
2177         if (hw->mac_type == e1000_82541_rev_2
2178                         || hw->mac_type == e1000_82547_rev_2) {
2179                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2180                                 &phy_data);
2181                 if (ret_val)
2182                         return ret_val;
2183         } else if (hw->mac_type == e1000_ich8lan) {
2184                 /* MAC writes into PHY register based on the state transition
2185                  * and start auto-negotiation. SW driver can overwrite the
2186                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2187                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2188         } else {
2189                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2190                                 &phy_data);
2191                 if (ret_val)
2192                         return ret_val;
2193         }
2194
2195         if (!active) {
2196                 if (hw->mac_type == e1000_82541_rev_2 ||
2197                         hw->mac_type == e1000_82547_rev_2) {
2198                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2199                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2200                                         phy_data);
2201                         if (ret_val)
2202                                 return ret_val;
2203                 } else {
2204                         if (hw->mac_type == e1000_ich8lan) {
2205                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2206                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2207                         } else {
2208                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2209                                 ret_val = e1000_write_phy_reg(hw,
2210                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2211                                 if (ret_val)
2212                                         return ret_val;
2213                         }
2214                 }
2215
2216         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2217          * Dx states where the power conservation is most important.  During
2218          * driver activity we should enable SmartSpeed, so performance is
2219          * maintained. */
2220                 if (hw->smart_speed == e1000_smart_speed_on) {
2221                         ret_val = e1000_read_phy_reg(hw,
2222                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2223                         if (ret_val)
2224                                 return ret_val;
2225
2226                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2227                         ret_val = e1000_write_phy_reg(hw,
2228                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2229                         if (ret_val)
2230                                 return ret_val;
2231                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2232                         ret_val = e1000_read_phy_reg(hw,
2233                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2234                         if (ret_val)
2235                                 return ret_val;
2236
2237                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2238                         ret_val = e1000_write_phy_reg(hw,
2239                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2240                         if (ret_val)
2241                                 return ret_val;
2242                 }
2243
2244         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2245                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2246                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2247
2248                 if (hw->mac_type == e1000_82541_rev_2 ||
2249                     hw->mac_type == e1000_82547_rev_2) {
2250                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2251                         ret_val = e1000_write_phy_reg(hw,
2252                                         IGP01E1000_GMII_FIFO, phy_data);
2253                         if (ret_val)
2254                                 return ret_val;
2255                 } else {
2256                         if (hw->mac_type == e1000_ich8lan) {
2257                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2258                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2259                         } else {
2260                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2261                                 ret_val = e1000_write_phy_reg(hw,
2262                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2263                                 if (ret_val)
2264                                         return ret_val;
2265                         }
2266                 }
2267
2268                 /* When LPLU is enabled we should disable SmartSpeed */
2269                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2270                                 &phy_data);
2271                 if (ret_val)
2272                         return ret_val;
2273
2274                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2275                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2276                                 phy_data);
2277                 if (ret_val)
2278                         return ret_val;
2279         }
2280         return E1000_SUCCESS;
2281 }
2282
2283 /*****************************************************************************
2284  *
2285  * This function sets the lplu d0 state according to the active flag.  When
2286  * activating lplu this function also disables smart speed and vise versa.
2287  * lplu will not be activated unless the device autonegotiation advertisment
2288  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2289  * hw: Struct containing variables accessed by shared code
2290  * active - true to enable lplu false to disable lplu.
2291  *
2292  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2293  *            E1000_SUCCESS at any other case.
2294  *
2295  ****************************************************************************/
2296
2297 static int32_t
2298 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2299 {
2300         uint32_t phy_ctrl = 0;
2301         int32_t ret_val;
2302         uint16_t phy_data;
2303         DEBUGFUNC();
2304
2305         if (hw->mac_type <= e1000_82547_rev_2)
2306                 return E1000_SUCCESS;
2307
2308         if (hw->mac_type == e1000_ich8lan) {
2309                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2310         } else {
2311                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2312                                 &phy_data);
2313                 if (ret_val)
2314                         return ret_val;
2315         }
2316
2317         if (!active) {
2318                 if (hw->mac_type == e1000_ich8lan) {
2319                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2320                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2321                 } else {
2322                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2323                         ret_val = e1000_write_phy_reg(hw,
2324                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2325                         if (ret_val)
2326                                 return ret_val;
2327                 }
2328
2329         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2330          * Dx states where the power conservation is most important.  During
2331          * driver activity we should enable SmartSpeed, so performance is
2332          * maintained. */
2333                 if (hw->smart_speed == e1000_smart_speed_on) {
2334                         ret_val = e1000_read_phy_reg(hw,
2335                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2336                         if (ret_val)
2337                                 return ret_val;
2338
2339                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2340                         ret_val = e1000_write_phy_reg(hw,
2341                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2342                         if (ret_val)
2343                                 return ret_val;
2344                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2345                         ret_val = e1000_read_phy_reg(hw,
2346                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2347                         if (ret_val)
2348                                 return ret_val;
2349
2350                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2351                         ret_val = e1000_write_phy_reg(hw,
2352                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2353                         if (ret_val)
2354                                 return ret_val;
2355                 }
2356
2357
2358         } else {
2359
2360                 if (hw->mac_type == e1000_ich8lan) {
2361                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2362                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2363                 } else {
2364                         phy_data |= IGP02E1000_PM_D0_LPLU;
2365                         ret_val = e1000_write_phy_reg(hw,
2366                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2367                         if (ret_val)
2368                                 return ret_val;
2369                 }
2370
2371                 /* When LPLU is enabled we should disable SmartSpeed */
2372                 ret_val = e1000_read_phy_reg(hw,
2373                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2374                 if (ret_val)
2375                         return ret_val;
2376
2377                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2378                 ret_val = e1000_write_phy_reg(hw,
2379                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2380                 if (ret_val)
2381                         return ret_val;
2382
2383         }
2384         return E1000_SUCCESS;
2385 }
2386
2387 /********************************************************************
2388 * Copper link setup for e1000_phy_igp series.
2389 *
2390 * hw - Struct containing variables accessed by shared code
2391 *********************************************************************/
2392 static int32_t
2393 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2394 {
2395         uint32_t led_ctrl;
2396         int32_t ret_val;
2397         uint16_t phy_data;
2398
2399         DEBUGFUNC();
2400
2401         if (hw->phy_reset_disable)
2402                 return E1000_SUCCESS;
2403
2404         ret_val = e1000_phy_reset(hw);
2405         if (ret_val) {
2406                 DEBUGOUT("Error Resetting the PHY\n");
2407                 return ret_val;
2408         }
2409
2410         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2411         mdelay(15);
2412         if (hw->mac_type != e1000_ich8lan) {
2413                 /* Configure activity LED after PHY reset */
2414                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2415                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2416                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2417                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2418         }
2419
2420         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2421         if (hw->phy_type == e1000_phy_igp) {
2422                 /* disable lplu d3 during driver init */
2423                 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2424                 if (ret_val) {
2425                         DEBUGOUT("Error Disabling LPLU D3\n");
2426                         return ret_val;
2427                 }
2428         }
2429
2430         /* disable lplu d0 during driver init */
2431         ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2432         if (ret_val) {
2433                 DEBUGOUT("Error Disabling LPLU D0\n");
2434                 return ret_val;
2435         }
2436         /* Configure mdi-mdix settings */
2437         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2438         if (ret_val)
2439                 return ret_val;
2440
2441         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2442                 hw->dsp_config_state = e1000_dsp_config_disabled;
2443                 /* Force MDI for earlier revs of the IGP PHY */
2444                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2445                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2446                 hw->mdix = 1;
2447
2448         } else {
2449                 hw->dsp_config_state = e1000_dsp_config_enabled;
2450                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2451
2452                 switch (hw->mdix) {
2453                 case 1:
2454                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2455                         break;
2456                 case 2:
2457                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2458                         break;
2459                 case 0:
2460                 default:
2461                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2462                         break;
2463                 }
2464         }
2465         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2466         if (ret_val)
2467                 return ret_val;
2468
2469         /* set auto-master slave resolution settings */
2470         if (hw->autoneg) {
2471                 e1000_ms_type phy_ms_setting = hw->master_slave;
2472
2473                 if (hw->ffe_config_state == e1000_ffe_config_active)
2474                         hw->ffe_config_state = e1000_ffe_config_enabled;
2475
2476                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2477                         hw->dsp_config_state = e1000_dsp_config_enabled;
2478
2479                 /* when autonegotiation advertisment is only 1000Mbps then we
2480                   * should disable SmartSpeed and enable Auto MasterSlave
2481                   * resolution as hardware default. */
2482                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2483                         /* Disable SmartSpeed */
2484                         ret_val = e1000_read_phy_reg(hw,
2485                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2486                         if (ret_val)
2487                                 return ret_val;
2488                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2489                         ret_val = e1000_write_phy_reg(hw,
2490                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2491                         if (ret_val)
2492                                 return ret_val;
2493                         /* Set auto Master/Slave resolution process */
2494                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2495                                         &phy_data);
2496                         if (ret_val)
2497                                 return ret_val;
2498                         phy_data &= ~CR_1000T_MS_ENABLE;
2499                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2500                                         phy_data);
2501                         if (ret_val)
2502                                 return ret_val;
2503                 }
2504
2505                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2506                 if (ret_val)
2507                         return ret_val;
2508
2509                 /* load defaults for future use */
2510                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2511                                 ((phy_data & CR_1000T_MS_VALUE) ?
2512                                 e1000_ms_force_master :
2513                                 e1000_ms_force_slave) :
2514                                 e1000_ms_auto;
2515
2516                 switch (phy_ms_setting) {
2517                 case e1000_ms_force_master:
2518                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2519                         break;
2520                 case e1000_ms_force_slave:
2521                         phy_data |= CR_1000T_MS_ENABLE;
2522                         phy_data &= ~(CR_1000T_MS_VALUE);
2523                         break;
2524                 case e1000_ms_auto:
2525                         phy_data &= ~CR_1000T_MS_ENABLE;
2526                 default:
2527                         break;
2528                 }
2529                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2530                 if (ret_val)
2531                         return ret_val;
2532         }
2533
2534         return E1000_SUCCESS;
2535 }
2536
2537 /*****************************************************************************
2538  * This function checks the mode of the firmware.
2539  *
2540  * returns  - TRUE when the mode is IAMT or FALSE.
2541  ****************************************************************************/
2542 boolean_t
2543 e1000_check_mng_mode(struct e1000_hw *hw)
2544 {
2545         uint32_t fwsm;
2546         DEBUGFUNC();
2547
2548         fwsm = E1000_READ_REG(hw, FWSM);
2549
2550         if (hw->mac_type == e1000_ich8lan) {
2551                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2552                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2553                         return TRUE;
2554         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2555                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2556                         return TRUE;
2557
2558         return FALSE;
2559 }
2560
2561 static int32_t
2562 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2563 {
2564         uint16_t swfw = E1000_SWFW_PHY0_SM;
2565         uint32_t reg_val;
2566         DEBUGFUNC();
2567
2568         if (e1000_is_second_port(hw))
2569                 swfw = E1000_SWFW_PHY1_SM;
2570
2571         if (e1000_swfw_sync_acquire(hw, swfw))
2572                 return -E1000_ERR_SWFW_SYNC;
2573
2574         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2575                         & E1000_KUMCTRLSTA_OFFSET) | data;
2576         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2577         udelay(2);
2578
2579         return E1000_SUCCESS;
2580 }
2581
2582 static int32_t
2583 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2584 {
2585         uint16_t swfw = E1000_SWFW_PHY0_SM;
2586         uint32_t reg_val;
2587         DEBUGFUNC();
2588
2589         if (e1000_is_second_port(hw))
2590                 swfw = E1000_SWFW_PHY1_SM;
2591
2592         if (e1000_swfw_sync_acquire(hw, swfw))
2593                 return -E1000_ERR_SWFW_SYNC;
2594
2595         /* Write register address */
2596         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2597                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2598         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2599         udelay(2);
2600
2601         /* Read the data returned */
2602         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2603         *data = (uint16_t)reg_val;
2604
2605         return E1000_SUCCESS;
2606 }
2607
2608 /********************************************************************
2609 * Copper link setup for e1000_phy_gg82563 series.
2610 *
2611 * hw - Struct containing variables accessed by shared code
2612 *********************************************************************/
2613 static int32_t
2614 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2615 {
2616         int32_t ret_val;
2617         uint16_t phy_data;
2618         uint32_t reg_data;
2619
2620         DEBUGFUNC();
2621
2622         if (!hw->phy_reset_disable) {
2623                 /* Enable CRS on TX for half-duplex operation. */
2624                 ret_val = e1000_read_phy_reg(hw,
2625                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2626                 if (ret_val)
2627                         return ret_val;
2628
2629                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2630                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2631                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2632
2633                 ret_val = e1000_write_phy_reg(hw,
2634                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2635                 if (ret_val)
2636                         return ret_val;
2637
2638                 /* Options:
2639                  *   MDI/MDI-X = 0 (default)
2640                  *   0 - Auto for all speeds
2641                  *   1 - MDI mode
2642                  *   2 - MDI-X mode
2643                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2644                  */
2645                 ret_val = e1000_read_phy_reg(hw,
2646                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2647                 if (ret_val)
2648                         return ret_val;
2649
2650                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2651
2652                 switch (hw->mdix) {
2653                 case 1:
2654                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2655                         break;
2656                 case 2:
2657                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2658                         break;
2659                 case 0:
2660                 default:
2661                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2662                         break;
2663                 }
2664
2665                 /* Options:
2666                  *   disable_polarity_correction = 0 (default)
2667                  *       Automatic Correction for Reversed Cable Polarity
2668                  *   0 - Disabled
2669                  *   1 - Enabled
2670                  */
2671                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2672                 ret_val = e1000_write_phy_reg(hw,
2673                                 GG82563_PHY_SPEC_CTRL, phy_data);
2674
2675                 if (ret_val)
2676                         return ret_val;
2677
2678                 /* SW Reset the PHY so all changes take effect */
2679                 ret_val = e1000_phy_reset(hw);
2680                 if (ret_val) {
2681                         DEBUGOUT("Error Resetting the PHY\n");
2682                         return ret_val;
2683                 }
2684         } /* phy_reset_disable */
2685
2686         if (hw->mac_type == e1000_80003es2lan) {
2687                 /* Bypass RX and TX FIFO's */
2688                 ret_val = e1000_write_kmrn_reg(hw,
2689                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2690                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2691                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2692                 if (ret_val)
2693                         return ret_val;
2694
2695                 ret_val = e1000_read_phy_reg(hw,
2696                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2697                 if (ret_val)
2698                         return ret_val;
2699
2700                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2701                 ret_val = e1000_write_phy_reg(hw,
2702                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2703
2704                 if (ret_val)
2705                         return ret_val;
2706
2707                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2708                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2709                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2710
2711                 ret_val = e1000_read_phy_reg(hw,
2712                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2713                 if (ret_val)
2714                         return ret_val;
2715
2716         /* Do not init these registers when the HW is in IAMT mode, since the
2717          * firmware will have already initialized them.  We only initialize
2718          * them if the HW is not in IAMT mode.
2719          */
2720                 if (e1000_check_mng_mode(hw) == FALSE) {
2721                         /* Enable Electrical Idle on the PHY */
2722                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2723                         ret_val = e1000_write_phy_reg(hw,
2724                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2725                         if (ret_val)
2726                                 return ret_val;
2727
2728                         ret_val = e1000_read_phy_reg(hw,
2729                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2730                         if (ret_val)
2731                                 return ret_val;
2732
2733                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2734                         ret_val = e1000_write_phy_reg(hw,
2735                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2736
2737                         if (ret_val)
2738                                 return ret_val;
2739                 }
2740
2741                 /* Workaround: Disable padding in Kumeran interface in the MAC
2742                  * and in the PHY to avoid CRC errors.
2743                  */
2744                 ret_val = e1000_read_phy_reg(hw,
2745                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2746                 if (ret_val)
2747                         return ret_val;
2748                 phy_data |= GG82563_ICR_DIS_PADDING;
2749                 ret_val = e1000_write_phy_reg(hw,
2750                                 GG82563_PHY_INBAND_CTRL, phy_data);
2751                 if (ret_val)
2752                         return ret_val;
2753         }
2754         return E1000_SUCCESS;
2755 }
2756
2757 /********************************************************************
2758 * Copper link setup for e1000_phy_m88 series.
2759 *
2760 * hw - Struct containing variables accessed by shared code
2761 *********************************************************************/
2762 static int32_t
2763 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2764 {
2765         int32_t ret_val;
2766         uint16_t phy_data;
2767
2768         DEBUGFUNC();
2769
2770         if (hw->phy_reset_disable)
2771                 return E1000_SUCCESS;
2772
2773         /* Enable CRS on TX. This must be set for half-duplex operation. */
2774         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2775         if (ret_val)
2776                 return ret_val;
2777
2778         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2779
2780         /* Options:
2781          *   MDI/MDI-X = 0 (default)
2782          *   0 - Auto for all speeds
2783          *   1 - MDI mode
2784          *   2 - MDI-X mode
2785          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2786          */
2787         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2788
2789         switch (hw->mdix) {
2790         case 1:
2791                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2792                 break;
2793         case 2:
2794                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2795                 break;
2796         case 3:
2797                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2798                 break;
2799         case 0:
2800         default:
2801                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2802                 break;
2803         }
2804
2805         /* Options:
2806          *   disable_polarity_correction = 0 (default)
2807          *       Automatic Correction for Reversed Cable Polarity
2808          *   0 - Disabled
2809          *   1 - Enabled
2810          */
2811         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2812         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2813         if (ret_val)
2814                 return ret_val;
2815
2816         if (hw->phy_revision < M88E1011_I_REV_4) {
2817                 /* Force TX_CLK in the Extended PHY Specific Control Register
2818                  * to 25MHz clock.
2819                  */
2820                 ret_val = e1000_read_phy_reg(hw,
2821                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2822                 if (ret_val)
2823                         return ret_val;
2824
2825                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2826
2827                 if ((hw->phy_revision == E1000_REVISION_2) &&
2828                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2829                         /* Vidalia Phy, set the downshift counter to 5x */
2830                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2831                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2832                         ret_val = e1000_write_phy_reg(hw,
2833                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2834                         if (ret_val)
2835                                 return ret_val;
2836                 } else {
2837                         /* Configure Master and Slave downshift values */
2838                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2839                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2840                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2841                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2842                         ret_val = e1000_write_phy_reg(hw,
2843                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2844                         if (ret_val)
2845                                 return ret_val;
2846                 }
2847         }
2848
2849         /* SW Reset the PHY so all changes take effect */
2850         ret_val = e1000_phy_reset(hw);
2851         if (ret_val) {
2852                 DEBUGOUT("Error Resetting the PHY\n");
2853                 return ret_val;
2854         }
2855
2856         return E1000_SUCCESS;
2857 }
2858
2859 /********************************************************************
2860 * Setup auto-negotiation and flow control advertisements,
2861 * and then perform auto-negotiation.
2862 *
2863 * hw - Struct containing variables accessed by shared code
2864 *********************************************************************/
2865 static int32_t
2866 e1000_copper_link_autoneg(struct e1000_hw *hw)
2867 {
2868         int32_t ret_val;
2869         uint16_t phy_data;
2870
2871         DEBUGFUNC();
2872
2873         /* Perform some bounds checking on the hw->autoneg_advertised
2874          * parameter.  If this variable is zero, then set it to the default.
2875          */
2876         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2877
2878         /* If autoneg_advertised is zero, we assume it was not defaulted
2879          * by the calling code so we set to advertise full capability.
2880          */
2881         if (hw->autoneg_advertised == 0)
2882                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2883
2884         /* IFE phy only supports 10/100 */
2885         if (hw->phy_type == e1000_phy_ife)
2886                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2887
2888         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2889         ret_val = e1000_phy_setup_autoneg(hw);
2890         if (ret_val) {
2891                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2892                 return ret_val;
2893         }
2894         DEBUGOUT("Restarting Auto-Neg\n");
2895
2896         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2897          * the Auto Neg Restart bit in the PHY control register.
2898          */
2899         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2900         if (ret_val)
2901                 return ret_val;
2902
2903         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2904         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2905         if (ret_val)
2906                 return ret_val;
2907
2908         /* Does the user want to wait for Auto-Neg to complete here, or
2909          * check at a later time (for example, callback routine).
2910          */
2911         /* If we do not wait for autonegtation to complete I
2912          * do not see a valid link status.
2913          * wait_autoneg_complete = 1 .
2914          */
2915         if (hw->wait_autoneg_complete) {
2916                 ret_val = e1000_wait_autoneg(hw);
2917                 if (ret_val) {
2918                         DEBUGOUT("Error while waiting for autoneg"
2919                                         "to complete\n");
2920                         return ret_val;
2921                 }
2922         }
2923
2924         hw->get_link_status = TRUE;
2925
2926         return E1000_SUCCESS;
2927 }
2928
2929 /******************************************************************************
2930 * Config the MAC and the PHY after link is up.
2931 *   1) Set up the MAC to the current PHY speed/duplex
2932 *      if we are on 82543.  If we
2933 *      are on newer silicon, we only need to configure
2934 *      collision distance in the Transmit Control Register.
2935 *   2) Set up flow control on the MAC to that established with
2936 *      the link partner.
2937 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
2938 *
2939 * hw - Struct containing variables accessed by shared code
2940 ******************************************************************************/
2941 static int32_t
2942 e1000_copper_link_postconfig(struct e1000_hw *hw)
2943 {
2944         int32_t ret_val;
2945         DEBUGFUNC();
2946
2947         if (hw->mac_type >= e1000_82544) {
2948                 e1000_config_collision_dist(hw);
2949         } else {
2950                 ret_val = e1000_config_mac_to_phy(hw);
2951                 if (ret_val) {
2952                         DEBUGOUT("Error configuring MAC to PHY settings\n");
2953                         return ret_val;
2954                 }
2955         }
2956         ret_val = e1000_config_fc_after_link_up(hw);
2957         if (ret_val) {
2958                 DEBUGOUT("Error Configuring Flow Control\n");
2959                 return ret_val;
2960         }
2961         return E1000_SUCCESS;
2962 }
2963
2964 /******************************************************************************
2965 * Detects which PHY is present and setup the speed and duplex
2966 *
2967 * hw - Struct containing variables accessed by shared code
2968 ******************************************************************************/
2969 static int
2970 e1000_setup_copper_link(struct eth_device *nic)
2971 {
2972         struct e1000_hw *hw = nic->priv;
2973         int32_t ret_val;
2974         uint16_t i;
2975         uint16_t phy_data;
2976         uint16_t reg_data;
2977
2978         DEBUGFUNC();
2979
2980         switch (hw->mac_type) {
2981         case e1000_80003es2lan:
2982         case e1000_ich8lan:
2983                 /* Set the mac to wait the maximum time between each
2984                  * iteration and increase the max iterations when
2985                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2986                 ret_val = e1000_write_kmrn_reg(hw,
2987                                 GG82563_REG(0x34, 4), 0xFFFF);
2988                 if (ret_val)
2989                         return ret_val;
2990                 ret_val = e1000_read_kmrn_reg(hw,
2991                                 GG82563_REG(0x34, 9), &reg_data);
2992                 if (ret_val)
2993                         return ret_val;
2994                 reg_data |= 0x3F;
2995                 ret_val = e1000_write_kmrn_reg(hw,
2996                                 GG82563_REG(0x34, 9), reg_data);
2997                 if (ret_val)
2998                         return ret_val;
2999         default:
3000                 break;
3001         }
3002
3003         /* Check if it is a valid PHY and set PHY mode if necessary. */
3004         ret_val = e1000_copper_link_preconfig(hw);
3005         if (ret_val)
3006                 return ret_val;
3007         switch (hw->mac_type) {
3008         case e1000_80003es2lan:
3009                 /* Kumeran registers are written-only */
3010                 reg_data =
3011                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3012                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3013                 ret_val = e1000_write_kmrn_reg(hw,
3014                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3015                 if (ret_val)
3016                         return ret_val;
3017                 break;
3018         default:
3019                 break;
3020         }
3021
3022         if (hw->phy_type == e1000_phy_igp ||
3023                 hw->phy_type == e1000_phy_igp_3 ||
3024                 hw->phy_type == e1000_phy_igp_2) {
3025                 ret_val = e1000_copper_link_igp_setup(hw);
3026                 if (ret_val)
3027                         return ret_val;
3028         } else if (hw->phy_type == e1000_phy_m88) {
3029                 ret_val = e1000_copper_link_mgp_setup(hw);
3030                 if (ret_val)
3031                         return ret_val;
3032         } else if (hw->phy_type == e1000_phy_gg82563) {
3033                 ret_val = e1000_copper_link_ggp_setup(hw);
3034                 if (ret_val)
3035                         return ret_val;
3036         }
3037
3038         /* always auto */
3039         /* Setup autoneg and flow control advertisement
3040           * and perform autonegotiation */
3041         ret_val = e1000_copper_link_autoneg(hw);
3042         if (ret_val)
3043                 return ret_val;
3044
3045         /* Check link status. Wait up to 100 microseconds for link to become
3046          * valid.
3047          */
3048         for (i = 0; i < 10; i++) {
3049                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3050                 if (ret_val)
3051                         return ret_val;
3052                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3053                 if (ret_val)
3054                         return ret_val;
3055
3056                 if (phy_data & MII_SR_LINK_STATUS) {
3057                         /* Config the MAC and PHY after link is up */
3058                         ret_val = e1000_copper_link_postconfig(hw);
3059                         if (ret_val)
3060                                 return ret_val;
3061
3062                         DEBUGOUT("Valid link established!!!\n");
3063                         return E1000_SUCCESS;
3064                 }
3065                 udelay(10);
3066         }
3067
3068         DEBUGOUT("Unable to establish link!!!\n");
3069         return E1000_SUCCESS;
3070 }
3071
3072 /******************************************************************************
3073 * Configures PHY autoneg and flow control advertisement settings
3074 *
3075 * hw - Struct containing variables accessed by shared code
3076 ******************************************************************************/
3077 int32_t
3078 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3079 {
3080         int32_t ret_val;
3081         uint16_t mii_autoneg_adv_reg;
3082         uint16_t mii_1000t_ctrl_reg;
3083
3084         DEBUGFUNC();
3085
3086         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3087         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3088         if (ret_val)
3089                 return ret_val;
3090
3091         if (hw->phy_type != e1000_phy_ife) {
3092                 /* Read the MII 1000Base-T Control Register (Address 9). */
3093                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3094                                 &mii_1000t_ctrl_reg);
3095                 if (ret_val)
3096                         return ret_val;
3097         } else
3098                 mii_1000t_ctrl_reg = 0;
3099
3100         /* Need to parse both autoneg_advertised and fc and set up
3101          * the appropriate PHY registers.  First we will parse for
3102          * autoneg_advertised software override.  Since we can advertise
3103          * a plethora of combinations, we need to check each bit
3104          * individually.
3105          */
3106
3107         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3108          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3109          * the  1000Base-T Control Register (Address 9).
3110          */
3111         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3112         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3113
3114         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3115
3116         /* Do we want to advertise 10 Mb Half Duplex? */
3117         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3118                 DEBUGOUT("Advertise 10mb Half duplex\n");
3119                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3120         }
3121
3122         /* Do we want to advertise 10 Mb Full Duplex? */
3123         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3124                 DEBUGOUT("Advertise 10mb Full duplex\n");
3125                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3126         }
3127
3128         /* Do we want to advertise 100 Mb Half Duplex? */
3129         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3130                 DEBUGOUT("Advertise 100mb Half duplex\n");
3131                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3132         }
3133
3134         /* Do we want to advertise 100 Mb Full Duplex? */
3135         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3136                 DEBUGOUT("Advertise 100mb Full duplex\n");
3137                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3138         }
3139
3140         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3141         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3142                 DEBUGOUT
3143                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3144         }
3145
3146         /* Do we want to advertise 1000 Mb Full Duplex? */
3147         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3148                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3149                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3150         }
3151
3152         /* Check for a software override of the flow control settings, and
3153          * setup the PHY advertisement registers accordingly.  If
3154          * auto-negotiation is enabled, then software will have to set the
3155          * "PAUSE" bits to the correct value in the Auto-Negotiation
3156          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3157          *
3158          * The possible values of the "fc" parameter are:
3159          *      0:  Flow control is completely disabled
3160          *      1:  Rx flow control is enabled (we can receive pause frames
3161          *          but not send pause frames).
3162          *      2:  Tx flow control is enabled (we can send pause frames
3163          *          but we do not support receiving pause frames).
3164          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3165          *  other:  No software override.  The flow control configuration
3166          *          in the EEPROM is used.
3167          */
3168         switch (hw->fc) {
3169         case e1000_fc_none:     /* 0 */
3170                 /* Flow control (RX & TX) is completely disabled by a
3171                  * software over-ride.
3172                  */
3173                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3174                 break;
3175         case e1000_fc_rx_pause: /* 1 */
3176                 /* RX Flow control is enabled, and TX Flow control is
3177                  * disabled, by a software over-ride.
3178                  */
3179                 /* Since there really isn't a way to advertise that we are
3180                  * capable of RX Pause ONLY, we will advertise that we
3181                  * support both symmetric and asymmetric RX PAUSE.  Later
3182                  * (in e1000_config_fc_after_link_up) we will disable the
3183                  *hw's ability to send PAUSE frames.
3184                  */
3185                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3186                 break;
3187         case e1000_fc_tx_pause: /* 2 */
3188                 /* TX Flow control is enabled, and RX Flow control is
3189                  * disabled, by a software over-ride.
3190                  */
3191                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3192                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3193                 break;
3194         case e1000_fc_full:     /* 3 */
3195                 /* Flow control (both RX and TX) is enabled by a software
3196                  * over-ride.
3197                  */
3198                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3199                 break;
3200         default:
3201                 DEBUGOUT("Flow control param set incorrectly\n");
3202                 return -E1000_ERR_CONFIG;
3203         }
3204
3205         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3206         if (ret_val)
3207                 return ret_val;
3208
3209         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3210
3211         if (hw->phy_type != e1000_phy_ife) {
3212                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3213                                 mii_1000t_ctrl_reg);
3214                 if (ret_val)
3215                         return ret_val;
3216         }
3217
3218         return E1000_SUCCESS;
3219 }
3220
3221 /******************************************************************************
3222 * Sets the collision distance in the Transmit Control register
3223 *
3224 * hw - Struct containing variables accessed by shared code
3225 *
3226 * Link should have been established previously. Reads the speed and duplex
3227 * information from the Device Status register.
3228 ******************************************************************************/
3229 static void
3230 e1000_config_collision_dist(struct e1000_hw *hw)
3231 {
3232         uint32_t tctl, coll_dist;
3233
3234         DEBUGFUNC();
3235
3236         if (hw->mac_type < e1000_82543)
3237                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3238         else
3239                 coll_dist = E1000_COLLISION_DISTANCE;
3240
3241         tctl = E1000_READ_REG(hw, TCTL);
3242
3243         tctl &= ~E1000_TCTL_COLD;
3244         tctl |= coll_dist << E1000_COLD_SHIFT;
3245
3246         E1000_WRITE_REG(hw, TCTL, tctl);
3247         E1000_WRITE_FLUSH(hw);
3248 }
3249
3250 /******************************************************************************
3251 * Sets MAC speed and duplex settings to reflect the those in the PHY
3252 *
3253 * hw - Struct containing variables accessed by shared code
3254 * mii_reg - data to write to the MII control register
3255 *
3256 * The contents of the PHY register containing the needed information need to
3257 * be passed in.
3258 ******************************************************************************/
3259 static int
3260 e1000_config_mac_to_phy(struct e1000_hw *hw)
3261 {
3262         uint32_t ctrl;
3263         uint16_t phy_data;
3264
3265         DEBUGFUNC();
3266
3267         /* Read the Device Control Register and set the bits to Force Speed
3268          * and Duplex.
3269          */
3270         ctrl = E1000_READ_REG(hw, CTRL);
3271         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3272         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3273
3274         /* Set up duplex in the Device Control and Transmit Control
3275          * registers depending on negotiated values.
3276          */
3277         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3278                 DEBUGOUT("PHY Read Error\n");
3279                 return -E1000_ERR_PHY;
3280         }
3281         if (phy_data & M88E1000_PSSR_DPLX)
3282                 ctrl |= E1000_CTRL_FD;
3283         else
3284                 ctrl &= ~E1000_CTRL_FD;
3285
3286         e1000_config_collision_dist(hw);
3287
3288         /* Set up speed in the Device Control register depending on
3289          * negotiated values.
3290          */
3291         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3292                 ctrl |= E1000_CTRL_SPD_1000;
3293         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3294                 ctrl |= E1000_CTRL_SPD_100;
3295         /* Write the configured values back to the Device Control Reg. */
3296         E1000_WRITE_REG(hw, CTRL, ctrl);
3297         return 0;
3298 }
3299
3300 /******************************************************************************
3301  * Forces the MAC's flow control settings.
3302  *
3303  * hw - Struct containing variables accessed by shared code
3304  *
3305  * Sets the TFCE and RFCE bits in the device control register to reflect
3306  * the adapter settings. TFCE and RFCE need to be explicitly set by
3307  * software when a Copper PHY is used because autonegotiation is managed
3308  * by the PHY rather than the MAC. Software must also configure these
3309  * bits when link is forced on a fiber connection.
3310  *****************************************************************************/
3311 static int
3312 e1000_force_mac_fc(struct e1000_hw *hw)
3313 {
3314         uint32_t ctrl;
3315
3316         DEBUGFUNC();
3317
3318         /* Get the current configuration of the Device Control Register */
3319         ctrl = E1000_READ_REG(hw, CTRL);
3320
3321         /* Because we didn't get link via the internal auto-negotiation
3322          * mechanism (we either forced link or we got link via PHY
3323          * auto-neg), we have to manually enable/disable transmit an
3324          * receive flow control.
3325          *
3326          * The "Case" statement below enables/disable flow control
3327          * according to the "hw->fc" parameter.
3328          *
3329          * The possible values of the "fc" parameter are:
3330          *      0:  Flow control is completely disabled
3331          *      1:  Rx flow control is enabled (we can receive pause
3332          *          frames but not send pause frames).
3333          *      2:  Tx flow control is enabled (we can send pause frames
3334          *          frames but we do not receive pause frames).
3335          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3336          *  other:  No other values should be possible at this point.
3337          */
3338
3339         switch (hw->fc) {
3340         case e1000_fc_none:
3341                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3342                 break;
3343         case e1000_fc_rx_pause:
3344                 ctrl &= (~E1000_CTRL_TFCE);
3345                 ctrl |= E1000_CTRL_RFCE;
3346                 break;
3347         case e1000_fc_tx_pause:
3348                 ctrl &= (~E1000_CTRL_RFCE);
3349                 ctrl |= E1000_CTRL_TFCE;
3350                 break;
3351         case e1000_fc_full:
3352                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3353                 break;
3354         default:
3355                 DEBUGOUT("Flow control param set incorrectly\n");
3356                 return -E1000_ERR_CONFIG;
3357         }
3358
3359         /* Disable TX Flow Control for 82542 (rev 2.0) */
3360         if (hw->mac_type == e1000_82542_rev2_0)
3361                 ctrl &= (~E1000_CTRL_TFCE);
3362
3363         E1000_WRITE_REG(hw, CTRL, ctrl);
3364         return 0;
3365 }
3366
3367 /******************************************************************************
3368  * Configures flow control settings after link is established
3369  *
3370  * hw - Struct containing variables accessed by shared code
3371  *
3372  * Should be called immediately after a valid link has been established.
3373  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3374  * and autonegotiation is enabled, the MAC flow control settings will be set
3375  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3376  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3377  *****************************************************************************/
3378 static int32_t
3379 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3380 {
3381         int32_t ret_val;
3382         uint16_t mii_status_reg;
3383         uint16_t mii_nway_adv_reg;
3384         uint16_t mii_nway_lp_ability_reg;
3385         uint16_t speed;
3386         uint16_t duplex;
3387
3388         DEBUGFUNC();
3389
3390         /* Check for the case where we have fiber media and auto-neg failed
3391          * so we had to force link.  In this case, we need to force the
3392          * configuration of the MAC to match the "fc" parameter.
3393          */
3394         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3395                 || ((hw->media_type == e1000_media_type_internal_serdes)
3396                 && (hw->autoneg_failed))
3397                 || ((hw->media_type == e1000_media_type_copper)
3398                 && (!hw->autoneg))) {
3399                 ret_val = e1000_force_mac_fc(hw);
3400                 if (ret_val < 0) {
3401                         DEBUGOUT("Error forcing flow control settings\n");
3402                         return ret_val;
3403                 }
3404         }
3405
3406         /* Check for the case where we have copper media and auto-neg is
3407          * enabled.  In this case, we need to check and see if Auto-Neg
3408          * has completed, and if so, how the PHY and link partner has
3409          * flow control configured.
3410          */
3411         if (hw->media_type == e1000_media_type_copper) {
3412                 /* Read the MII Status Register and check to see if AutoNeg
3413                  * has completed.  We read this twice because this reg has
3414                  * some "sticky" (latched) bits.
3415                  */
3416                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3417                         DEBUGOUT("PHY Read Error \n");
3418                         return -E1000_ERR_PHY;
3419                 }
3420                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3421                         DEBUGOUT("PHY Read Error \n");
3422                         return -E1000_ERR_PHY;
3423                 }
3424
3425                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3426                         /* The AutoNeg process has completed, so we now need to
3427                          * read both the Auto Negotiation Advertisement Register
3428                          * (Address 4) and the Auto_Negotiation Base Page Ability
3429                          * Register (Address 5) to determine how flow control was
3430                          * negotiated.
3431                          */
3432                         if (e1000_read_phy_reg
3433                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3434                                 DEBUGOUT("PHY Read Error\n");
3435                                 return -E1000_ERR_PHY;
3436                         }
3437                         if (e1000_read_phy_reg
3438                             (hw, PHY_LP_ABILITY,
3439                              &mii_nway_lp_ability_reg) < 0) {
3440                                 DEBUGOUT("PHY Read Error\n");
3441                                 return -E1000_ERR_PHY;
3442                         }
3443
3444                         /* Two bits in the Auto Negotiation Advertisement Register
3445                          * (Address 4) and two bits in the Auto Negotiation Base
3446                          * Page Ability Register (Address 5) determine flow control
3447                          * for both the PHY and the link partner.  The following
3448                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3449                          * 1999, describes these PAUSE resolution bits and how flow
3450                          * control is determined based upon these settings.
3451                          * NOTE:  DC = Don't Care
3452                          *
3453                          *   LOCAL DEVICE  |   LINK PARTNER
3454                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3455                          *-------|---------|-------|---------|--------------------
3456                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3457                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3458                          *   0   |    1    |   1   |    0    | e1000_fc_none
3459                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3460                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3461                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3462                          *   1   |    1    |   0   |    0    | e1000_fc_none
3463                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3464                          *
3465                          */
3466                         /* Are both PAUSE bits set to 1?  If so, this implies
3467                          * Symmetric Flow Control is enabled at both ends.  The
3468                          * ASM_DIR bits are irrelevant per the spec.
3469                          *
3470                          * For Symmetric Flow Control:
3471                          *
3472                          *   LOCAL DEVICE  |   LINK PARTNER
3473                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3474                          *-------|---------|-------|---------|--------------------
3475                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3476                          *
3477                          */
3478                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3479                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3480                                 /* Now we need to check if the user selected RX ONLY
3481                                  * of pause frames.  In this case, we had to advertise
3482                                  * FULL flow control because we could not advertise RX
3483                                  * ONLY. Hence, we must now check to see if we need to
3484                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3485                                  */
3486                                 if (hw->original_fc == e1000_fc_full) {
3487                                         hw->fc = e1000_fc_full;
3488                                         DEBUGOUT("Flow Control = FULL.\r\n");
3489                                 } else {
3490                                         hw->fc = e1000_fc_rx_pause;
3491                                         DEBUGOUT
3492                                             ("Flow Control = RX PAUSE frames only.\r\n");
3493                                 }
3494                         }
3495                         /* For receiving PAUSE frames ONLY.
3496                          *
3497                          *   LOCAL DEVICE  |   LINK PARTNER
3498                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3499                          *-------|---------|-------|---------|--------------------
3500                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3501                          *
3502                          */
3503                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3504                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3505                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3506                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3507                         {
3508                                 hw->fc = e1000_fc_tx_pause;
3509                                 DEBUGOUT
3510                                     ("Flow Control = TX PAUSE frames only.\r\n");
3511                         }
3512                         /* For transmitting PAUSE frames ONLY.
3513                          *
3514                          *   LOCAL DEVICE  |   LINK PARTNER
3515                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3516                          *-------|---------|-------|---------|--------------------
3517                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3518                          *
3519                          */
3520                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3521                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3522                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3523                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3524                         {
3525                                 hw->fc = e1000_fc_rx_pause;
3526                                 DEBUGOUT
3527                                     ("Flow Control = RX PAUSE frames only.\r\n");
3528                         }
3529                         /* Per the IEEE spec, at this point flow control should be
3530                          * disabled.  However, we want to consider that we could
3531                          * be connected to a legacy switch that doesn't advertise
3532                          * desired flow control, but can be forced on the link
3533                          * partner.  So if we advertised no flow control, that is
3534                          * what we will resolve to.  If we advertised some kind of
3535                          * receive capability (Rx Pause Only or Full Flow Control)
3536                          * and the link partner advertised none, we will configure
3537                          * ourselves to enable Rx Flow Control only.  We can do
3538                          * this safely for two reasons:  If the link partner really
3539                          * didn't want flow control enabled, and we enable Rx, no
3540                          * harm done since we won't be receiving any PAUSE frames
3541                          * anyway.  If the intent on the link partner was to have
3542                          * flow control enabled, then by us enabling RX only, we
3543                          * can at least receive pause frames and process them.
3544                          * This is a good idea because in most cases, since we are
3545                          * predominantly a server NIC, more times than not we will
3546                          * be asked to delay transmission of packets than asking
3547                          * our link partner to pause transmission of frames.
3548                          */
3549                         else if (hw->original_fc == e1000_fc_none ||
3550                                  hw->original_fc == e1000_fc_tx_pause) {
3551                                 hw->fc = e1000_fc_none;
3552                                 DEBUGOUT("Flow Control = NONE.\r\n");
3553                         } else {
3554                                 hw->fc = e1000_fc_rx_pause;
3555                                 DEBUGOUT
3556                                     ("Flow Control = RX PAUSE frames only.\r\n");
3557                         }
3558
3559                         /* Now we need to do one last check...  If we auto-
3560                          * negotiated to HALF DUPLEX, flow control should not be
3561                          * enabled per IEEE 802.3 spec.
3562                          */
3563                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3564
3565                         if (duplex == HALF_DUPLEX)
3566                                 hw->fc = e1000_fc_none;
3567
3568                         /* Now we call a subroutine to actually force the MAC
3569                          * controller to use the correct flow control settings.
3570                          */
3571                         ret_val = e1000_force_mac_fc(hw);
3572                         if (ret_val < 0) {
3573                                 DEBUGOUT
3574                                     ("Error forcing flow control settings\n");
3575                                 return ret_val;
3576                         }
3577                 } else {
3578                         DEBUGOUT
3579                             ("Copper PHY and Auto Neg has not completed.\r\n");
3580                 }
3581         }
3582         return E1000_SUCCESS;
3583 }
3584
3585 /******************************************************************************
3586  * Checks to see if the link status of the hardware has changed.
3587  *
3588  * hw - Struct containing variables accessed by shared code
3589  *
3590  * Called by any function that needs to check the link status of the adapter.
3591  *****************************************************************************/
3592 static int
3593 e1000_check_for_link(struct eth_device *nic)
3594 {
3595         struct e1000_hw *hw = nic->priv;
3596         uint32_t rxcw;
3597         uint32_t ctrl;
3598         uint32_t status;
3599         uint32_t rctl;
3600         uint32_t signal;
3601         int32_t ret_val;
3602         uint16_t phy_data;
3603         uint16_t lp_capability;
3604
3605         DEBUGFUNC();
3606
3607         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3608          * set when the optics detect a signal. On older adapters, it will be
3609          * cleared when there is a signal
3610          */
3611         ctrl = E1000_READ_REG(hw, CTRL);
3612         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3613                 signal = E1000_CTRL_SWDPIN1;
3614         else
3615                 signal = 0;
3616
3617         status = E1000_READ_REG(hw, STATUS);
3618         rxcw = E1000_READ_REG(hw, RXCW);
3619         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3620
3621         /* If we have a copper PHY then we only want to go out to the PHY
3622          * registers to see if Auto-Neg has completed and/or if our link
3623          * status has changed.  The get_link_status flag will be set if we
3624          * receive a Link Status Change interrupt or we have Rx Sequence
3625          * Errors.
3626          */
3627         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3628                 /* First we want to see if the MII Status Register reports
3629                  * link.  If so, then we want to get the current speed/duplex
3630                  * of the PHY.
3631                  * Read the register twice since the link bit is sticky.
3632                  */
3633                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3634                         DEBUGOUT("PHY Read Error\n");
3635                         return -E1000_ERR_PHY;
3636                 }
3637                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3638                         DEBUGOUT("PHY Read Error\n");
3639                         return -E1000_ERR_PHY;
3640                 }
3641
3642                 if (phy_data & MII_SR_LINK_STATUS) {
3643                         hw->get_link_status = FALSE;
3644                 } else {
3645                         /* No link detected */
3646                         return -E1000_ERR_NOLINK;
3647                 }
3648
3649                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3650                  * have Si on board that is 82544 or newer, Auto
3651                  * Speed Detection takes care of MAC speed/duplex
3652                  * configuration.  So we only need to configure Collision
3653                  * Distance in the MAC.  Otherwise, we need to force
3654                  * speed/duplex on the MAC to the current PHY speed/duplex
3655                  * settings.
3656                  */
3657                 if (hw->mac_type >= e1000_82544)
3658                         e1000_config_collision_dist(hw);
3659                 else {
3660                         ret_val = e1000_config_mac_to_phy(hw);
3661                         if (ret_val < 0) {
3662                                 DEBUGOUT
3663                                     ("Error configuring MAC to PHY settings\n");
3664                                 return ret_val;
3665                         }
3666                 }
3667
3668                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3669                  * need to restore the desired flow control settings because we may
3670                  * have had to re-autoneg with a different link partner.
3671                  */
3672                 ret_val = e1000_config_fc_after_link_up(hw);
3673                 if (ret_val < 0) {
3674                         DEBUGOUT("Error configuring flow control\n");
3675                         return ret_val;
3676                 }
3677
3678                 /* At this point we know that we are on copper and we have
3679                  * auto-negotiated link.  These are conditions for checking the link
3680                  * parter capability register.  We use the link partner capability to
3681                  * determine if TBI Compatibility needs to be turned on or off.  If
3682                  * the link partner advertises any speed in addition to Gigabit, then
3683                  * we assume that they are GMII-based, and TBI compatibility is not
3684                  * needed. If no other speeds are advertised, we assume the link
3685                  * partner is TBI-based, and we turn on TBI Compatibility.
3686                  */
3687                 if (hw->tbi_compatibility_en) {
3688                         if (e1000_read_phy_reg
3689                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3690                                 DEBUGOUT("PHY Read Error\n");
3691                                 return -E1000_ERR_PHY;
3692                         }
3693                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3694                                              NWAY_LPAR_10T_FD_CAPS |
3695                                              NWAY_LPAR_100TX_HD_CAPS |
3696                                              NWAY_LPAR_100TX_FD_CAPS |
3697                                              NWAY_LPAR_100T4_CAPS)) {
3698                                 /* If our link partner advertises anything in addition to
3699                                  * gigabit, we do not need to enable TBI compatibility.
3700                                  */
3701                                 if (hw->tbi_compatibility_on) {
3702                                         /* If we previously were in the mode, turn it off. */
3703                                         rctl = E1000_READ_REG(hw, RCTL);
3704                                         rctl &= ~E1000_RCTL_SBP;
3705                                         E1000_WRITE_REG(hw, RCTL, rctl);
3706                                         hw->tbi_compatibility_on = FALSE;
3707                                 }
3708                         } else {
3709                                 /* If TBI compatibility is was previously off, turn it on. For
3710                                  * compatibility with a TBI link partner, we will store bad
3711                                  * packets. Some frames have an additional byte on the end and
3712                                  * will look like CRC errors to to the hardware.
3713                                  */
3714                                 if (!hw->tbi_compatibility_on) {
3715                                         hw->tbi_compatibility_on = TRUE;
3716                                         rctl = E1000_READ_REG(hw, RCTL);
3717                                         rctl |= E1000_RCTL_SBP;
3718                                         E1000_WRITE_REG(hw, RCTL, rctl);
3719                                 }
3720                         }
3721                 }
3722         }
3723         /* If we don't have link (auto-negotiation failed or link partner cannot
3724          * auto-negotiate), the cable is plugged in (we have signal), and our
3725          * link partner is not trying to auto-negotiate with us (we are receiving
3726          * idles or data), we need to force link up. We also need to give
3727          * auto-negotiation time to complete, in case the cable was just plugged
3728          * in. The autoneg_failed flag does this.
3729          */
3730         else if ((hw->media_type == e1000_media_type_fiber) &&
3731                  (!(status & E1000_STATUS_LU)) &&
3732                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3733                  (!(rxcw & E1000_RXCW_C))) {
3734                 if (hw->autoneg_failed == 0) {
3735                         hw->autoneg_failed = 1;
3736                         return 0;
3737                 }
3738                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3739
3740                 /* Disable auto-negotiation in the TXCW register */
3741                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3742
3743                 /* Force link-up and also force full-duplex. */
3744                 ctrl = E1000_READ_REG(hw, CTRL);
3745                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3746                 E1000_WRITE_REG(hw, CTRL, ctrl);
3747
3748                 /* Configure Flow Control after forcing link up. */
3749                 ret_val = e1000_config_fc_after_link_up(hw);
3750                 if (ret_val < 0) {
3751                         DEBUGOUT("Error configuring flow control\n");
3752                         return ret_val;
3753                 }
3754         }
3755         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3756          * auto-negotiation in the TXCW register and disable forced link in the
3757          * Device Control register in an attempt to auto-negotiate with our link
3758          * partner.
3759          */
3760         else if ((hw->media_type == e1000_media_type_fiber) &&
3761                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3762                 DEBUGOUT
3763                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3764                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3765                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3766         }
3767         return 0;
3768 }
3769
3770 /******************************************************************************
3771 * Configure the MAC-to-PHY interface for 10/100Mbps
3772 *
3773 * hw - Struct containing variables accessed by shared code
3774 ******************************************************************************/
3775 static int32_t
3776 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3777 {
3778         int32_t ret_val = E1000_SUCCESS;
3779         uint32_t tipg;
3780         uint16_t reg_data;
3781
3782         DEBUGFUNC();
3783
3784         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3785         ret_val = e1000_write_kmrn_reg(hw,
3786                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3787         if (ret_val)
3788                 return ret_val;
3789
3790         /* Configure Transmit Inter-Packet Gap */
3791         tipg = E1000_READ_REG(hw, TIPG);
3792         tipg &= ~E1000_TIPG_IPGT_MASK;
3793         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3794         E1000_WRITE_REG(hw, TIPG, tipg);
3795
3796         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3797
3798         if (ret_val)
3799                 return ret_val;
3800
3801         if (duplex == HALF_DUPLEX)
3802                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3803         else
3804                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3805
3806         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3807
3808         return ret_val;
3809 }
3810
3811 static int32_t
3812 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3813 {
3814         int32_t ret_val = E1000_SUCCESS;
3815         uint16_t reg_data;
3816         uint32_t tipg;
3817
3818         DEBUGFUNC();
3819
3820         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3821         ret_val = e1000_write_kmrn_reg(hw,
3822                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3823         if (ret_val)
3824                 return ret_val;
3825
3826         /* Configure Transmit Inter-Packet Gap */
3827         tipg = E1000_READ_REG(hw, TIPG);
3828         tipg &= ~E1000_TIPG_IPGT_MASK;
3829         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3830         E1000_WRITE_REG(hw, TIPG, tipg);
3831
3832         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3833
3834         if (ret_val)
3835                 return ret_val;
3836
3837         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3838         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3839
3840         return ret_val;
3841 }
3842
3843 /******************************************************************************
3844  * Detects the current speed and duplex settings of the hardware.
3845  *
3846  * hw - Struct containing variables accessed by shared code
3847  * speed - Speed of the connection
3848  * duplex - Duplex setting of the connection
3849  *****************************************************************************/
3850 static int
3851 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3852                 uint16_t *duplex)
3853 {
3854         uint32_t status;
3855         int32_t ret_val;
3856         uint16_t phy_data;
3857
3858         DEBUGFUNC();
3859
3860         if (hw->mac_type >= e1000_82543) {
3861                 status = E1000_READ_REG(hw, STATUS);
3862                 if (status & E1000_STATUS_SPEED_1000) {
3863                         *speed = SPEED_1000;
3864                         DEBUGOUT("1000 Mbs, ");
3865                 } else if (status & E1000_STATUS_SPEED_100) {
3866                         *speed = SPEED_100;
3867                         DEBUGOUT("100 Mbs, ");
3868                 } else {
3869                         *speed = SPEED_10;
3870                         DEBUGOUT("10 Mbs, ");
3871                 }
3872
3873                 if (status & E1000_STATUS_FD) {
3874                         *duplex = FULL_DUPLEX;
3875                         DEBUGOUT("Full Duplex\r\n");
3876                 } else {
3877                         *duplex = HALF_DUPLEX;
3878                         DEBUGOUT(" Half Duplex\r\n");
3879                 }
3880         } else {
3881                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3882                 *speed = SPEED_1000;
3883                 *duplex = FULL_DUPLEX;
3884         }
3885
3886         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3887          * even if it is operating at half duplex.  Here we set the duplex
3888          * settings to match the duplex in the link partner's capabilities.
3889          */
3890         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3891                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3892                 if (ret_val)
3893                         return ret_val;
3894
3895                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3896                         *duplex = HALF_DUPLEX;
3897                 else {
3898                         ret_val = e1000_read_phy_reg(hw,
3899                                         PHY_LP_ABILITY, &phy_data);
3900                         if (ret_val)
3901                                 return ret_val;
3902                         if ((*speed == SPEED_100 &&
3903                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3904                                 || (*speed == SPEED_10
3905                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3906                                 *duplex = HALF_DUPLEX;
3907                 }
3908         }
3909
3910         if ((hw->mac_type == e1000_80003es2lan) &&
3911                 (hw->media_type == e1000_media_type_copper)) {
3912                 if (*speed == SPEED_1000)
3913                         ret_val = e1000_configure_kmrn_for_1000(hw);
3914                 else
3915                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3916                 if (ret_val)
3917                         return ret_val;
3918         }
3919         return E1000_SUCCESS;
3920 }
3921
3922 /******************************************************************************
3923 * Blocks until autoneg completes or times out (~4.5 seconds)
3924 *
3925 * hw - Struct containing variables accessed by shared code
3926 ******************************************************************************/
3927 static int
3928 e1000_wait_autoneg(struct e1000_hw *hw)
3929 {
3930         uint16_t i;
3931         uint16_t phy_data;
3932
3933         DEBUGFUNC();
3934         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3935
3936         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3937         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3938                 /* Read the MII Status Register and wait for Auto-Neg
3939                  * Complete bit to be set.
3940                  */
3941                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3942                         DEBUGOUT("PHY Read Error\n");
3943                         return -E1000_ERR_PHY;
3944                 }
3945                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3946                         DEBUGOUT("PHY Read Error\n");
3947                         return -E1000_ERR_PHY;
3948                 }
3949                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3950                         DEBUGOUT("Auto-Neg complete.\n");
3951                         return 0;
3952                 }
3953                 mdelay(100);
3954         }
3955         DEBUGOUT("Auto-Neg timedout.\n");
3956         return -E1000_ERR_TIMEOUT;
3957 }
3958
3959 /******************************************************************************
3960 * Raises the Management Data Clock
3961 *
3962 * hw - Struct containing variables accessed by shared code
3963 * ctrl - Device control register's current value
3964 ******************************************************************************/
3965 static void
3966 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3967 {
3968         /* Raise the clock input to the Management Data Clock (by setting the MDC
3969          * bit), and then delay 2 microseconds.
3970          */
3971         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3972         E1000_WRITE_FLUSH(hw);
3973         udelay(2);
3974 }
3975
3976 /******************************************************************************
3977 * Lowers the Management Data Clock
3978 *
3979 * hw - Struct containing variables accessed by shared code
3980 * ctrl - Device control register's current value
3981 ******************************************************************************/
3982 static void
3983 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3984 {
3985         /* Lower the clock input to the Management Data Clock (by clearing the MDC
3986          * bit), and then delay 2 microseconds.
3987          */
3988         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3989         E1000_WRITE_FLUSH(hw);
3990         udelay(2);
3991 }
3992
3993 /******************************************************************************
3994 * Shifts data bits out to the PHY
3995 *
3996 * hw - Struct containing variables accessed by shared code
3997 * data - Data to send out to the PHY
3998 * count - Number of bits to shift out
3999 *
4000 * Bits are shifted out in MSB to LSB order.
4001 ******************************************************************************/
4002 static void
4003 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4004 {
4005         uint32_t ctrl;
4006         uint32_t mask;
4007
4008         /* We need to shift "count" number of bits out to the PHY. So, the value
4009          * in the "data" parameter will be shifted out to the PHY one bit at a
4010          * time. In order to do this, "data" must be broken down into bits.
4011          */
4012         mask = 0x01;
4013         mask <<= (count - 1);
4014
4015         ctrl = E1000_READ_REG(hw, CTRL);
4016
4017         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4018         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4019
4020         while (mask) {
4021                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4022                  * then raising and lowering the Management Data Clock. A "0" is
4023                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4024                  * raising and lowering the clock.
4025                  */
4026                 if (data & mask)
4027                         ctrl |= E1000_CTRL_MDIO;
4028                 else
4029                         ctrl &= ~E1000_CTRL_MDIO;
4030
4031                 E1000_WRITE_REG(hw, CTRL, ctrl);
4032                 E1000_WRITE_FLUSH(hw);
4033
4034                 udelay(2);
4035
4036                 e1000_raise_mdi_clk(hw, &ctrl);
4037                 e1000_lower_mdi_clk(hw, &ctrl);
4038
4039                 mask = mask >> 1;
4040         }
4041 }
4042
4043 /******************************************************************************
4044 * Shifts data bits in from the PHY
4045 *
4046 * hw - Struct containing variables accessed by shared code
4047 *
4048 * Bits are shifted in in MSB to LSB order.
4049 ******************************************************************************/
4050 static uint16_t
4051 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4052 {
4053         uint32_t ctrl;
4054         uint16_t data = 0;
4055         uint8_t i;
4056
4057         /* In order to read a register from the PHY, we need to shift in a total
4058          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4059          * to avoid contention on the MDIO pin when a read operation is performed.
4060          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4061          * by raising the input to the Management Data Clock (setting the MDC bit),
4062          * and then reading the value of the MDIO bit.
4063          */
4064         ctrl = E1000_READ_REG(hw, CTRL);
4065
4066         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4067         ctrl &= ~E1000_CTRL_MDIO_DIR;
4068         ctrl &= ~E1000_CTRL_MDIO;
4069
4070         E1000_WRITE_REG(hw, CTRL, ctrl);
4071         E1000_WRITE_FLUSH(hw);
4072
4073         /* Raise and Lower the clock before reading in the data. This accounts for
4074          * the turnaround bits. The first clock occurred when we clocked out the
4075          * last bit of the Register Address.
4076          */
4077         e1000_raise_mdi_clk(hw, &ctrl);
4078         e1000_lower_mdi_clk(hw, &ctrl);
4079
4080         for (data = 0, i = 0; i < 16; i++) {
4081                 data = data << 1;
4082                 e1000_raise_mdi_clk(hw, &ctrl);
4083                 ctrl = E1000_READ_REG(hw, CTRL);
4084                 /* Check to see if we shifted in a "1". */
4085                 if (ctrl & E1000_CTRL_MDIO)
4086                         data |= 1;
4087                 e1000_lower_mdi_clk(hw, &ctrl);
4088         }
4089
4090         e1000_raise_mdi_clk(hw, &ctrl);
4091         e1000_lower_mdi_clk(hw, &ctrl);
4092
4093         return data;
4094 }
4095
4096 /*****************************************************************************
4097 * Reads the value from a PHY register
4098 *
4099 * hw - Struct containing variables accessed by shared code
4100 * reg_addr - address of the PHY register to read
4101 ******************************************************************************/
4102 static int
4103 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4104 {
4105         uint32_t i;
4106         uint32_t mdic = 0;
4107         const uint32_t phy_addr = 1;
4108
4109         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4110                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4111                 return -E1000_ERR_PARAM;
4112         }
4113
4114         if (hw->mac_type > e1000_82543) {
4115                 /* Set up Op-code, Phy Address, and register address in the MDI
4116                  * Control register.  The MAC will take care of interfacing with the
4117                  * PHY to retrieve the desired data.
4118                  */
4119                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4120                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4121                         (E1000_MDIC_OP_READ));
4122
4123                 E1000_WRITE_REG(hw, MDIC, mdic);
4124
4125                 /* Poll the ready bit to see if the MDI read completed */
4126                 for (i = 0; i < 64; i++) {
4127                         udelay(10);
4128                         mdic = E1000_READ_REG(hw, MDIC);
4129                         if (mdic & E1000_MDIC_READY)
4130                                 break;
4131                 }
4132                 if (!(mdic & E1000_MDIC_READY)) {
4133                         DEBUGOUT("MDI Read did not complete\n");
4134                         return -E1000_ERR_PHY;
4135                 }
4136                 if (mdic & E1000_MDIC_ERROR) {
4137                         DEBUGOUT("MDI Error\n");
4138                         return -E1000_ERR_PHY;
4139                 }
4140                 *phy_data = (uint16_t) mdic;
4141         } else {
4142                 /* We must first send a preamble through the MDIO pin to signal the
4143                  * beginning of an MII instruction.  This is done by sending 32
4144                  * consecutive "1" bits.
4145                  */
4146                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4147
4148                 /* Now combine the next few fields that are required for a read
4149                  * operation.  We use this method instead of calling the
4150                  * e1000_shift_out_mdi_bits routine five different times. The format of
4151                  * a MII read instruction consists of a shift out of 14 bits and is
4152                  * defined as follows:
4153                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4154                  * followed by a shift in of 18 bits.  This first two bits shifted in
4155                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4156                  * READ operation is performed.  These two bits are thrown away
4157                  * followed by a shift in of 16 bits which contains the desired data.
4158                  */
4159                 mdic = ((reg_addr) | (phy_addr << 5) |
4160                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4161
4162                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4163
4164                 /* Now that we've shifted out the read command to the MII, we need to
4165                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4166                  * register address.
4167                  */
4168                 *phy_data = e1000_shift_in_mdi_bits(hw);
4169         }
4170         return 0;
4171 }
4172
4173 /******************************************************************************
4174 * Writes a value to a PHY register
4175 *
4176 * hw - Struct containing variables accessed by shared code
4177 * reg_addr - address of the PHY register to write
4178 * data - data to write to the PHY
4179 ******************************************************************************/
4180 static int
4181 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4182 {
4183         uint32_t i;
4184         uint32_t mdic = 0;
4185         const uint32_t phy_addr = 1;
4186
4187         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4188                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4189                 return -E1000_ERR_PARAM;
4190         }
4191
4192         if (hw->mac_type > e1000_82543) {
4193                 /* Set up Op-code, Phy Address, register address, and data intended
4194                  * for the PHY register in the MDI Control register.  The MAC will take
4195                  * care of interfacing with the PHY to send the desired data.
4196                  */
4197                 mdic = (((uint32_t) phy_data) |
4198                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4199                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4200                         (E1000_MDIC_OP_WRITE));
4201
4202                 E1000_WRITE_REG(hw, MDIC, mdic);
4203
4204                 /* Poll the ready bit to see if the MDI read completed */
4205                 for (i = 0; i < 64; i++) {
4206                         udelay(10);
4207                         mdic = E1000_READ_REG(hw, MDIC);
4208                         if (mdic & E1000_MDIC_READY)
4209                                 break;
4210                 }
4211                 if (!(mdic & E1000_MDIC_READY)) {
4212                         DEBUGOUT("MDI Write did not complete\n");
4213                         return -E1000_ERR_PHY;
4214                 }
4215         } else {
4216                 /* We'll need to use the SW defined pins to shift the write command
4217                  * out to the PHY. We first send a preamble to the PHY to signal the
4218                  * beginning of the MII instruction.  This is done by sending 32
4219                  * consecutive "1" bits.
4220                  */
4221                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4222
4223                 /* Now combine the remaining required fields that will indicate a
4224                  * write operation. We use this method instead of calling the
4225                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4226                  * format of a MII write instruction is as follows:
4227                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4228                  */
4229                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4230                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4231                 mdic <<= 16;
4232                 mdic |= (uint32_t) phy_data;
4233
4234                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4235         }
4236         return 0;
4237 }
4238
4239 /******************************************************************************
4240  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4241  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4242  * the caller to figure out how to deal with it.
4243  *
4244  * hw - Struct containing variables accessed by shared code
4245  *
4246  * returns: - E1000_BLK_PHY_RESET
4247  *            E1000_SUCCESS
4248  *
4249  *****************************************************************************/
4250 int32_t
4251 e1000_check_phy_reset_block(struct e1000_hw *hw)
4252 {
4253         uint32_t manc = 0;
4254         uint32_t fwsm = 0;
4255
4256         if (hw->mac_type == e1000_ich8lan) {
4257                 fwsm = E1000_READ_REG(hw, FWSM);
4258                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4259                                                 : E1000_BLK_PHY_RESET;
4260         }
4261
4262         if (hw->mac_type > e1000_82547_rev_2)
4263                 manc = E1000_READ_REG(hw, MANC);
4264         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4265                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4266 }
4267
4268 /***************************************************************************
4269  * Checks if the PHY configuration is done
4270  *
4271  * hw: Struct containing variables accessed by shared code
4272  *
4273  * returns: - E1000_ERR_RESET if fail to reset MAC
4274  *            E1000_SUCCESS at any other case.
4275  *
4276  ***************************************************************************/
4277 static int32_t
4278 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4279 {
4280         int32_t timeout = PHY_CFG_TIMEOUT;
4281         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4282
4283         DEBUGFUNC();
4284
4285         switch (hw->mac_type) {
4286         default:
4287                 mdelay(10);
4288                 break;
4289
4290         case e1000_80003es2lan:
4291                 /* Separate *_CFG_DONE_* bit for each port */
4292                 if (e1000_is_second_port(hw))
4293                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4294                 /* Fall Through */
4295
4296         case e1000_82571:
4297         case e1000_82572:
4298                 while (timeout) {
4299                         if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4300                                 break;
4301                         else
4302                                 mdelay(1);
4303                         timeout--;
4304                 }
4305                 if (!timeout) {
4306                         DEBUGOUT("MNG configuration cycle has not "
4307                                         "completed.\n");
4308                         return -E1000_ERR_RESET;
4309                 }
4310                 break;
4311         }
4312
4313         return E1000_SUCCESS;
4314 }
4315
4316 /******************************************************************************
4317 * Returns the PHY to the power-on reset state
4318 *
4319 * hw - Struct containing variables accessed by shared code
4320 ******************************************************************************/
4321 int32_t
4322 e1000_phy_hw_reset(struct e1000_hw *hw)
4323 {
4324         uint16_t swfw = E1000_SWFW_PHY0_SM;
4325         uint32_t ctrl, ctrl_ext;
4326         uint32_t led_ctrl;
4327         int32_t ret_val;
4328
4329         DEBUGFUNC();
4330
4331         /* In the case of the phy reset being blocked, it's not an error, we
4332          * simply return success without performing the reset. */
4333         ret_val = e1000_check_phy_reset_block(hw);
4334         if (ret_val)
4335                 return E1000_SUCCESS;
4336
4337         DEBUGOUT("Resetting Phy...\n");
4338
4339         if (hw->mac_type > e1000_82543) {
4340                 if (e1000_is_second_port(hw))
4341                         swfw = E1000_SWFW_PHY1_SM;
4342
4343                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4344                         DEBUGOUT("Unable to acquire swfw sync\n");
4345                         return -E1000_ERR_SWFW_SYNC;
4346                 }
4347
4348                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4349                  * bit. Then, take it out of reset.
4350                  */
4351                 ctrl = E1000_READ_REG(hw, CTRL);
4352                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4353                 E1000_WRITE_FLUSH(hw);
4354
4355                 if (hw->mac_type < e1000_82571)
4356                         udelay(10);
4357                 else
4358                         udelay(100);
4359
4360                 E1000_WRITE_REG(hw, CTRL, ctrl);
4361                 E1000_WRITE_FLUSH(hw);
4362
4363                 if (hw->mac_type >= e1000_82571)
4364                         mdelay(10);
4365
4366         } else {
4367                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4368                  * bit to put the PHY into reset. Then, take it out of reset.
4369                  */
4370                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4371                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4372                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4373                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4374                 E1000_WRITE_FLUSH(hw);
4375                 mdelay(10);
4376                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4377                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4378                 E1000_WRITE_FLUSH(hw);
4379         }
4380         udelay(150);
4381
4382         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4383                 /* Configure activity LED after PHY reset */
4384                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4385                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4386                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4387                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4388         }
4389
4390         /* Wait for FW to finish PHY configuration. */
4391         ret_val = e1000_get_phy_cfg_done(hw);
4392         if (ret_val != E1000_SUCCESS)
4393                 return ret_val;
4394
4395         return ret_val;
4396 }
4397
4398 /******************************************************************************
4399  * IGP phy init script - initializes the GbE PHY
4400  *
4401  * hw - Struct containing variables accessed by shared code
4402  *****************************************************************************/
4403 static void
4404 e1000_phy_init_script(struct e1000_hw *hw)
4405 {
4406         uint32_t ret_val;
4407         uint16_t phy_saved_data;
4408         DEBUGFUNC();
4409
4410         if (hw->phy_init_script) {
4411                 mdelay(20);
4412
4413                 /* Save off the current value of register 0x2F5B to be
4414                  * restored at the end of this routine. */
4415                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4416
4417                 /* Disabled the PHY transmitter */
4418                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4419
4420                 mdelay(20);
4421
4422                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4423
4424                 mdelay(5);
4425
4426                 switch (hw->mac_type) {
4427                 case e1000_82541:
4428                 case e1000_82547:
4429                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4430
4431                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4432
4433                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4434
4435                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4436
4437                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4438
4439                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4440
4441                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4442
4443                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4444
4445                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4446                         break;
4447
4448                 case e1000_82541_rev_2:
4449                 case e1000_82547_rev_2:
4450                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4451                         break;
4452                 default:
4453                         break;
4454                 }
4455
4456                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4457
4458                 mdelay(20);
4459
4460                 /* Now enable the transmitter */
4461                 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4462
4463                 if (hw->mac_type == e1000_82547) {
4464                         uint16_t fused, fine, coarse;
4465
4466                         /* Move to analog registers page */
4467                         e1000_read_phy_reg(hw,
4468                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4469
4470                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4471                                 e1000_read_phy_reg(hw,
4472                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4473
4474                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4475                                 coarse = fused
4476                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4477
4478                                 if (coarse >
4479                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4480                                         coarse -=
4481                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4482                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4483                                 } else if (coarse
4484                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4485                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4486
4487                                 fused = (fused
4488                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4489                                         (fine
4490                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4491                                         (coarse
4492                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4493
4494                                 e1000_write_phy_reg(hw,
4495                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4496                                 e1000_write_phy_reg(hw,
4497                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4498                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4499                         }
4500                 }
4501         }
4502 }
4503
4504 /******************************************************************************
4505 * Resets the PHY
4506 *
4507 * hw - Struct containing variables accessed by shared code
4508 *
4509 * Sets bit 15 of the MII Control register
4510 ******************************************************************************/
4511 int32_t
4512 e1000_phy_reset(struct e1000_hw *hw)
4513 {
4514         int32_t ret_val;
4515         uint16_t phy_data;
4516
4517         DEBUGFUNC();
4518
4519         /* In the case of the phy reset being blocked, it's not an error, we
4520          * simply return success without performing the reset. */
4521         ret_val = e1000_check_phy_reset_block(hw);
4522         if (ret_val)
4523                 return E1000_SUCCESS;
4524
4525         switch (hw->phy_type) {
4526         case e1000_phy_igp:
4527         case e1000_phy_igp_2:
4528         case e1000_phy_igp_3:
4529         case e1000_phy_ife:
4530                 ret_val = e1000_phy_hw_reset(hw);
4531                 if (ret_val)
4532                         return ret_val;
4533                 break;
4534         default:
4535                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4536                 if (ret_val)
4537                         return ret_val;
4538
4539                 phy_data |= MII_CR_RESET;
4540                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4541                 if (ret_val)
4542                         return ret_val;
4543
4544                 udelay(1);
4545                 break;
4546         }
4547
4548         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4549                 e1000_phy_init_script(hw);
4550
4551         return E1000_SUCCESS;
4552 }
4553
4554 static int e1000_set_phy_type (struct e1000_hw *hw)
4555 {
4556         DEBUGFUNC ();
4557
4558         if (hw->mac_type == e1000_undefined)
4559                 return -E1000_ERR_PHY_TYPE;
4560
4561         switch (hw->phy_id) {
4562         case M88E1000_E_PHY_ID:
4563         case M88E1000_I_PHY_ID:
4564         case M88E1011_I_PHY_ID:
4565         case M88E1111_I_PHY_ID:
4566                 hw->phy_type = e1000_phy_m88;
4567                 break;
4568         case IGP01E1000_I_PHY_ID:
4569                 if (hw->mac_type == e1000_82541 ||
4570                         hw->mac_type == e1000_82541_rev_2 ||
4571                         hw->mac_type == e1000_82547 ||
4572                         hw->mac_type == e1000_82547_rev_2) {
4573                         hw->phy_type = e1000_phy_igp;
4574                         hw->phy_type = e1000_phy_igp;
4575                         break;
4576                 }
4577         case IGP03E1000_E_PHY_ID:
4578                 hw->phy_type = e1000_phy_igp_3;
4579                 break;
4580         case IFE_E_PHY_ID:
4581         case IFE_PLUS_E_PHY_ID:
4582         case IFE_C_E_PHY_ID:
4583                 hw->phy_type = e1000_phy_ife;
4584                 break;
4585         case GG82563_E_PHY_ID:
4586                 if (hw->mac_type == e1000_80003es2lan) {
4587                         hw->phy_type = e1000_phy_gg82563;
4588                         break;
4589                 }
4590         case BME1000_E_PHY_ID:
4591                 hw->phy_type = e1000_phy_bm;
4592                 break;
4593                 /* Fall Through */
4594         default:
4595                 /* Should never have loaded on this device */
4596                 hw->phy_type = e1000_phy_undefined;
4597                 return -E1000_ERR_PHY_TYPE;
4598         }
4599
4600         return E1000_SUCCESS;
4601 }
4602
4603 /******************************************************************************
4604 * Probes the expected PHY address for known PHY IDs
4605 *
4606 * hw - Struct containing variables accessed by shared code
4607 ******************************************************************************/
4608 static int32_t
4609 e1000_detect_gig_phy(struct e1000_hw *hw)
4610 {
4611         int32_t phy_init_status, ret_val;
4612         uint16_t phy_id_high, phy_id_low;
4613         boolean_t match = FALSE;
4614
4615         DEBUGFUNC();
4616
4617         /* The 82571 firmware may still be configuring the PHY.  In this
4618          * case, we cannot access the PHY until the configuration is done.  So
4619          * we explicitly set the PHY values. */
4620         if (hw->mac_type == e1000_82571 ||
4621                 hw->mac_type == e1000_82572) {
4622                 hw->phy_id = IGP01E1000_I_PHY_ID;
4623                 hw->phy_type = e1000_phy_igp_2;
4624                 return E1000_SUCCESS;
4625         }
4626
4627         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4628          * work- around that forces PHY page 0 to be set or the reads fail.
4629          * The rest of the code in this routine uses e1000_read_phy_reg to
4630          * read the PHY ID.  So for ESB-2 we need to have this set so our
4631          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4632          * the routines below will figure this out as well. */
4633         if (hw->mac_type == e1000_80003es2lan)
4634                 hw->phy_type = e1000_phy_gg82563;
4635
4636         /* Read the PHY ID Registers to identify which PHY is onboard. */
4637         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4638         if (ret_val)
4639                 return ret_val;
4640
4641         hw->phy_id = (uint32_t) (phy_id_high << 16);
4642         udelay(20);
4643         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4644         if (ret_val)
4645                 return ret_val;
4646
4647         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4648         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4649
4650         switch (hw->mac_type) {
4651         case e1000_82543:
4652                 if (hw->phy_id == M88E1000_E_PHY_ID)
4653                         match = TRUE;
4654                 break;
4655         case e1000_82544:
4656                 if (hw->phy_id == M88E1000_I_PHY_ID)
4657                         match = TRUE;
4658                 break;
4659         case e1000_82540:
4660         case e1000_82545:
4661         case e1000_82545_rev_3:
4662         case e1000_82546:
4663         case e1000_82546_rev_3:
4664                 if (hw->phy_id == M88E1011_I_PHY_ID)
4665                         match = TRUE;
4666                 break;
4667         case e1000_82541:
4668         case e1000_82541_rev_2:
4669         case e1000_82547:
4670         case e1000_82547_rev_2:
4671                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4672                         match = TRUE;
4673
4674                 break;
4675         case e1000_82573:
4676                 if (hw->phy_id == M88E1111_I_PHY_ID)
4677                         match = TRUE;
4678                 break;
4679         case e1000_82574:
4680                 if (hw->phy_id == BME1000_E_PHY_ID)
4681                         match = TRUE;
4682                 break;
4683         case e1000_80003es2lan:
4684                 if (hw->phy_id == GG82563_E_PHY_ID)
4685                         match = TRUE;
4686                 break;
4687         case e1000_ich8lan:
4688                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4689                         match = TRUE;
4690                 if (hw->phy_id == IFE_E_PHY_ID)
4691                         match = TRUE;
4692                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4693                         match = TRUE;
4694                 if (hw->phy_id == IFE_C_E_PHY_ID)
4695                         match = TRUE;
4696                 break;
4697         default:
4698                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4699                 return -E1000_ERR_CONFIG;
4700         }
4701
4702         phy_init_status = e1000_set_phy_type(hw);
4703
4704         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4705                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4706                 return 0;
4707         }
4708         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4709         return -E1000_ERR_PHY;
4710 }
4711
4712 /*****************************************************************************
4713  * Set media type and TBI compatibility.
4714  *
4715  * hw - Struct containing variables accessed by shared code
4716  * **************************************************************************/
4717 void
4718 e1000_set_media_type(struct e1000_hw *hw)
4719 {
4720         uint32_t status;
4721
4722         DEBUGFUNC();
4723
4724         if (hw->mac_type != e1000_82543) {
4725                 /* tbi_compatibility is only valid on 82543 */
4726                 hw->tbi_compatibility_en = FALSE;
4727         }
4728
4729         switch (hw->device_id) {
4730         case E1000_DEV_ID_82545GM_SERDES:
4731         case E1000_DEV_ID_82546GB_SERDES:
4732         case E1000_DEV_ID_82571EB_SERDES:
4733         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4734         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4735         case E1000_DEV_ID_82572EI_SERDES:
4736         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4737                 hw->media_type = e1000_media_type_internal_serdes;
4738                 break;
4739         default:
4740                 switch (hw->mac_type) {
4741                 case e1000_82542_rev2_0:
4742                 case e1000_82542_rev2_1:
4743                         hw->media_type = e1000_media_type_fiber;
4744                         break;
4745                 case e1000_ich8lan:
4746                 case e1000_82573:
4747                 case e1000_82574:
4748                         /* The STATUS_TBIMODE bit is reserved or reused
4749                          * for the this device.
4750                          */
4751                         hw->media_type = e1000_media_type_copper;
4752                         break;
4753                 default:
4754                         status = E1000_READ_REG(hw, STATUS);
4755                         if (status & E1000_STATUS_TBIMODE) {
4756                                 hw->media_type = e1000_media_type_fiber;
4757                                 /* tbi_compatibility not valid on fiber */
4758                                 hw->tbi_compatibility_en = FALSE;
4759                         } else {
4760                                 hw->media_type = e1000_media_type_copper;
4761                         }
4762                         break;
4763                 }
4764         }
4765 }
4766
4767 /**
4768  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4769  *
4770  * e1000_sw_init initializes the Adapter private data structure.
4771  * Fields are initialized based on PCI device information and
4772  * OS network device settings (MTU size).
4773  **/
4774
4775 static int
4776 e1000_sw_init(struct eth_device *nic)
4777 {
4778         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4779         int result;
4780
4781         /* PCI config space info */
4782         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4783         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4784         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4785                              &hw->subsystem_vendor_id);
4786         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4787
4788         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4789         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4790
4791         /* identify the MAC */
4792         result = e1000_set_mac_type(hw);
4793         if (result) {
4794                 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4795                 return result;
4796         }
4797
4798         switch (hw->mac_type) {
4799         default:
4800                 break;
4801         case e1000_82541:
4802         case e1000_82547:
4803         case e1000_82541_rev_2:
4804         case e1000_82547_rev_2:
4805                 hw->phy_init_script = 1;
4806                 break;
4807         }
4808
4809         /* flow control settings */
4810         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4811         hw->fc_low_water = E1000_FC_LOW_THRESH;
4812         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4813         hw->fc_send_xon = 1;
4814
4815         /* Media type - copper or fiber */
4816         e1000_set_media_type(hw);
4817
4818         if (hw->mac_type >= e1000_82543) {
4819                 uint32_t status = E1000_READ_REG(hw, STATUS);
4820
4821                 if (status & E1000_STATUS_TBIMODE) {
4822                         DEBUGOUT("fiber interface\n");
4823                         hw->media_type = e1000_media_type_fiber;
4824                 } else {
4825                         DEBUGOUT("copper interface\n");
4826                         hw->media_type = e1000_media_type_copper;
4827                 }
4828         } else {
4829                 hw->media_type = e1000_media_type_fiber;
4830         }
4831
4832         hw->tbi_compatibility_en = TRUE;
4833         hw->wait_autoneg_complete = TRUE;
4834         if (hw->mac_type < e1000_82543)
4835                 hw->report_tx_early = 0;
4836         else
4837                 hw->report_tx_early = 1;
4838
4839         return E1000_SUCCESS;
4840 }
4841
4842 void
4843 fill_rx(struct e1000_hw *hw)
4844 {
4845         struct e1000_rx_desc *rd;
4846
4847         rx_last = rx_tail;
4848         rd = rx_base + rx_tail;
4849         rx_tail = (rx_tail + 1) % 8;
4850         memset(rd, 0, 16);
4851         rd->buffer_addr = cpu_to_le64((u32) & packet);
4852         E1000_WRITE_REG(hw, RDT, rx_tail);
4853 }
4854
4855 /**
4856  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4857  * @adapter: board private structure
4858  *
4859  * Configure the Tx unit of the MAC after a reset.
4860  **/
4861
4862 static void
4863 e1000_configure_tx(struct e1000_hw *hw)
4864 {
4865         unsigned long ptr;
4866         unsigned long tctl;
4867         unsigned long tipg, tarc;
4868         uint32_t ipgr1, ipgr2;
4869
4870         ptr = (u32) tx_pool;
4871         if (ptr & 0xf)
4872                 ptr = (ptr + 0x10) & (~0xf);
4873
4874         tx_base = (typeof(tx_base)) ptr;
4875
4876         E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4877         E1000_WRITE_REG(hw, TDBAH, 0);
4878
4879         E1000_WRITE_REG(hw, TDLEN, 128);
4880
4881         /* Setup the HW Tx Head and Tail descriptor pointers */
4882         E1000_WRITE_REG(hw, TDH, 0);
4883         E1000_WRITE_REG(hw, TDT, 0);
4884         tx_tail = 0;
4885
4886         /* Set the default values for the Tx Inter Packet Gap timer */
4887         if (hw->mac_type <= e1000_82547_rev_2 &&
4888             (hw->media_type == e1000_media_type_fiber ||
4889              hw->media_type == e1000_media_type_internal_serdes))
4890                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4891         else
4892                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4893
4894         /* Set the default values for the Tx Inter Packet Gap timer */
4895         switch (hw->mac_type) {
4896         case e1000_82542_rev2_0:
4897         case e1000_82542_rev2_1:
4898                 tipg = DEFAULT_82542_TIPG_IPGT;
4899                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4900                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4901                 break;
4902         case e1000_80003es2lan:
4903                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4904                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4905                 break;
4906         default:
4907                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4908                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4909                 break;
4910         }
4911         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4912         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4913         E1000_WRITE_REG(hw, TIPG, tipg);
4914         /* Program the Transmit Control Register */
4915         tctl = E1000_READ_REG(hw, TCTL);
4916         tctl &= ~E1000_TCTL_CT;
4917         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4918             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4919
4920         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4921                 tarc = E1000_READ_REG(hw, TARC0);
4922                 /* set the speed mode bit, we'll clear it if we're not at
4923                  * gigabit link later */
4924                 /* git bit can be set to 1*/
4925         } else if (hw->mac_type == e1000_80003es2lan) {
4926                 tarc = E1000_READ_REG(hw, TARC0);
4927                 tarc |= 1;
4928                 E1000_WRITE_REG(hw, TARC0, tarc);
4929                 tarc = E1000_READ_REG(hw, TARC1);
4930                 tarc |= 1;
4931                 E1000_WRITE_REG(hw, TARC1, tarc);
4932         }
4933
4934
4935         e1000_config_collision_dist(hw);
4936         /* Setup Transmit Descriptor Settings for eop descriptor */
4937         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4938
4939         /* Need to set up RS bit */
4940         if (hw->mac_type < e1000_82543)
4941                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4942         else
4943                 hw->txd_cmd |= E1000_TXD_CMD_RS;
4944         E1000_WRITE_REG(hw, TCTL, tctl);
4945 }
4946
4947 /**
4948  * e1000_setup_rctl - configure the receive control register
4949  * @adapter: Board private structure
4950  **/
4951 static void
4952 e1000_setup_rctl(struct e1000_hw *hw)
4953 {
4954         uint32_t rctl;
4955
4956         rctl = E1000_READ_REG(hw, RCTL);
4957
4958         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4959
4960         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4961                 | E1000_RCTL_RDMTS_HALF;        /* |
4962                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4963
4964         if (hw->tbi_compatibility_on == 1)
4965                 rctl |= E1000_RCTL_SBP;
4966         else
4967                 rctl &= ~E1000_RCTL_SBP;
4968
4969         rctl &= ~(E1000_RCTL_SZ_4096);
4970                 rctl |= E1000_RCTL_SZ_2048;
4971                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4972         E1000_WRITE_REG(hw, RCTL, rctl);
4973 }
4974
4975 /**
4976  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4977  * @adapter: board private structure
4978  *
4979  * Configure the Rx unit of the MAC after a reset.
4980  **/
4981 static void
4982 e1000_configure_rx(struct e1000_hw *hw)
4983 {
4984         unsigned long ptr;
4985         unsigned long rctl, ctrl_ext;
4986         rx_tail = 0;
4987         /* make sure receives are disabled while setting up the descriptors */
4988         rctl = E1000_READ_REG(hw, RCTL);
4989         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4990         if (hw->mac_type >= e1000_82540) {
4991                 /* Set the interrupt throttling rate.  Value is calculated
4992                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4993 #define MAX_INTS_PER_SEC        8000
4994 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
4995                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4996         }
4997
4998         if (hw->mac_type >= e1000_82571) {
4999                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5000                 /* Reset delay timers after every interrupt */
5001                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5002                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5003                 E1000_WRITE_FLUSH(hw);
5004         }
5005         /* Setup the Base and Length of the Rx Descriptor Ring */
5006         ptr = (u32) rx_pool;
5007         if (ptr & 0xf)
5008                 ptr = (ptr + 0x10) & (~0xf);
5009         rx_base = (typeof(rx_base)) ptr;
5010         E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
5011         E1000_WRITE_REG(hw, RDBAH, 0);
5012
5013         E1000_WRITE_REG(hw, RDLEN, 128);
5014
5015         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5016         E1000_WRITE_REG(hw, RDH, 0);
5017         E1000_WRITE_REG(hw, RDT, 0);
5018         /* Enable Receives */
5019
5020         E1000_WRITE_REG(hw, RCTL, rctl);
5021         fill_rx(hw);
5022 }
5023
5024 /**************************************************************************
5025 POLL - Wait for a frame
5026 ***************************************************************************/
5027 static int
5028 e1000_poll(struct eth_device *nic)
5029 {
5030         struct e1000_hw *hw = nic->priv;
5031         struct e1000_rx_desc *rd;
5032         /* return true if there's an ethernet packet ready to read */
5033         rd = rx_base + rx_last;
5034         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5035                 return 0;
5036         /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5037         NetReceive((uchar *)packet, le32_to_cpu(rd->length));
5038         fill_rx(hw);
5039         return 1;
5040 }
5041
5042 /**************************************************************************
5043 TRANSMIT - Transmit a frame
5044 ***************************************************************************/
5045 static int
5046 e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
5047 {
5048         void * nv_packet = (void *)packet;
5049         struct e1000_hw *hw = nic->priv;
5050         struct e1000_tx_desc *txp;
5051         int i = 0;
5052
5053         txp = tx_base + tx_tail;
5054         tx_tail = (tx_tail + 1) % 8;
5055
5056         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5057         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5058         txp->upper.data = 0;
5059         E1000_WRITE_REG(hw, TDT, tx_tail);
5060
5061         E1000_WRITE_FLUSH(hw);
5062         while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5063                 if (i++ > TOUT_LOOP) {
5064                         DEBUGOUT("e1000: tx timeout\n");
5065                         return 0;
5066                 }
5067                 udelay(10);     /* give the nic a chance to write to the register */
5068         }
5069         return 1;
5070 }
5071
5072 /*reset function*/
5073 static inline int
5074 e1000_reset(struct eth_device *nic)
5075 {
5076         struct e1000_hw *hw = nic->priv;
5077
5078         e1000_reset_hw(hw);
5079         if (hw->mac_type >= e1000_82544) {
5080                 E1000_WRITE_REG(hw, WUC, 0);
5081         }
5082         return e1000_init_hw(nic);
5083 }
5084
5085 /**************************************************************************
5086 DISABLE - Turn off ethernet interface
5087 ***************************************************************************/
5088 static void
5089 e1000_disable(struct eth_device *nic)
5090 {
5091         struct e1000_hw *hw = nic->priv;
5092
5093         /* Turn off the ethernet interface */
5094         E1000_WRITE_REG(hw, RCTL, 0);
5095         E1000_WRITE_REG(hw, TCTL, 0);
5096
5097         /* Clear the transmit ring */
5098         E1000_WRITE_REG(hw, TDH, 0);
5099         E1000_WRITE_REG(hw, TDT, 0);
5100
5101         /* Clear the receive ring */
5102         E1000_WRITE_REG(hw, RDH, 0);
5103         E1000_WRITE_REG(hw, RDT, 0);
5104
5105         /* put the card in its initial state */
5106 #if 0
5107         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5108 #endif
5109         mdelay(10);
5110
5111 }
5112
5113 /**************************************************************************
5114 INIT - set up ethernet interface(s)
5115 ***************************************************************************/
5116 static int
5117 e1000_init(struct eth_device *nic, bd_t * bis)
5118 {
5119         struct e1000_hw *hw = nic->priv;
5120         int ret_val = 0;
5121
5122         ret_val = e1000_reset(nic);
5123         if (ret_val < 0) {
5124                 if ((ret_val == -E1000_ERR_NOLINK) ||
5125                     (ret_val == -E1000_ERR_TIMEOUT)) {
5126                         E1000_ERR(hw->nic, "Valid Link not detected\n");
5127                 } else {
5128                         E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5129                 }
5130                 return 0;
5131         }
5132         e1000_configure_tx(hw);
5133         e1000_setup_rctl(hw);
5134         e1000_configure_rx(hw);
5135         return 1;
5136 }
5137
5138 /******************************************************************************
5139  * Gets the current PCI bus type of hardware
5140  *
5141  * hw - Struct containing variables accessed by shared code
5142  *****************************************************************************/
5143 void e1000_get_bus_type(struct e1000_hw *hw)
5144 {
5145         uint32_t status;
5146
5147         switch (hw->mac_type) {
5148         case e1000_82542_rev2_0:
5149         case e1000_82542_rev2_1:
5150                 hw->bus_type = e1000_bus_type_pci;
5151                 break;
5152         case e1000_82571:
5153         case e1000_82572:
5154         case e1000_82573:
5155         case e1000_82574:
5156         case e1000_80003es2lan:
5157                 hw->bus_type = e1000_bus_type_pci_express;
5158                 break;
5159         case e1000_ich8lan:
5160                 hw->bus_type = e1000_bus_type_pci_express;
5161                 break;
5162         default:
5163                 status = E1000_READ_REG(hw, STATUS);
5164                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5165                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5166                 break;
5167         }
5168 }
5169
5170 /**************************************************************************
5171 PROBE - Look for an adapter, this routine's visible to the outside
5172 You should omit the last argument struct pci_device * for a non-PCI NIC
5173 ***************************************************************************/
5174 int
5175 e1000_initialize(bd_t * bis)
5176 {
5177         unsigned int i;
5178         pci_dev_t devno;
5179
5180         DEBUGFUNC();
5181
5182         /* Find and probe all the matching PCI devices */
5183         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5184                 u32 val;
5185
5186                 /*
5187                  * These will never get freed due to errors, this allows us to
5188                  * perform SPI EEPROM programming from U-boot, for example.
5189                  */
5190                 struct eth_device *nic = malloc(sizeof(*nic));
5191                 struct e1000_hw *hw = malloc(sizeof(*hw));
5192                 if (!nic || !hw) {
5193                         printf("e1000#%u: Out of Memory!\n", i);
5194                         free(nic);
5195                         free(hw);
5196                         continue;
5197                 }
5198
5199                 /* Make sure all of the fields are initially zeroed */
5200                 memset(nic, 0, sizeof(*nic));
5201                 memset(hw, 0, sizeof(*hw));
5202
5203                 /* Assign the passed-in values */
5204                 hw->cardnum = i;
5205                 hw->pdev = devno;
5206                 hw->nic = nic;
5207                 nic->priv = hw;
5208
5209                 /* Generate a card name */
5210                 sprintf(nic->name, "e1000#%u", hw->cardnum);
5211
5212                 /* Print a debug message with the IO base address */
5213                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5214                 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5215
5216                 /* Try to enable I/O accesses and bus-mastering */
5217                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5218                 pci_write_config_dword(devno, PCI_COMMAND, val);
5219
5220                 /* Make sure it worked */
5221                 pci_read_config_dword(devno, PCI_COMMAND, &val);
5222                 if (!(val & PCI_COMMAND_MEMORY)) {
5223                         E1000_ERR(nic, "Can't enable I/O memory\n");
5224                         continue;
5225                 }
5226                 if (!(val & PCI_COMMAND_MASTER)) {
5227                         E1000_ERR(nic, "Can't enable bus-mastering\n");
5228                         continue;
5229                 }
5230
5231                 /* Are these variables needed? */
5232                 hw->fc = e1000_fc_default;
5233                 hw->original_fc = e1000_fc_default;
5234                 hw->autoneg_failed = 0;
5235                 hw->autoneg = 1;
5236                 hw->get_link_status = TRUE;
5237                 hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5238                                                         PCI_REGION_MEM);
5239                 hw->mac_type = e1000_undefined;
5240
5241                 /* MAC and Phy settings */
5242                 if (e1000_sw_init(nic) < 0) {
5243                         E1000_ERR(nic, "Software init failed\n");
5244                         continue;
5245                 }
5246                 if (e1000_check_phy_reset_block(hw))
5247                         E1000_ERR(nic, "PHY Reset is blocked!\n");
5248
5249                 /* Basic init was OK, reset the hardware */
5250                 e1000_reset_hw(hw);
5251
5252                 /* Validate the EEPROM and get chipset information */
5253 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
5254                 if (e1000_init_eeprom_params(hw)) {
5255                         E1000_ERR(nic, "EEPROM is invalid!\n");
5256                         continue;
5257                 }
5258                 if (e1000_validate_eeprom_checksum(hw))
5259                         continue;
5260 #endif
5261                 e1000_read_mac_addr(nic);
5262                 e1000_get_bus_type(hw);
5263
5264                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5265                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5266                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5267
5268                 /* Set up the function pointers and register the device */
5269                 nic->init = e1000_init;
5270                 nic->recv = e1000_poll;
5271                 nic->send = e1000_transmit;
5272                 nic->halt = e1000_disable;
5273                 eth_register(nic);
5274         }
5275
5276         return i;
5277 }