2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
22 #define PCI_HOSE_OP(rw, size, type) \
23 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
25 int offset, type value) \
27 return hose->rw##_##size(hose, dev, offset, value); \
30 PCI_HOSE_OP(read, byte, u8 *)
31 PCI_HOSE_OP(read, word, u16 *)
32 PCI_HOSE_OP(read, dword, u32 *)
33 PCI_HOSE_OP(write, byte, u8)
34 PCI_HOSE_OP(write, word, u16)
35 PCI_HOSE_OP(write, dword, u32)
37 #define PCI_OP(rw, size, type, error_code) \
38 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
40 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
48 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
51 PCI_OP(read, byte, u8 *, *value = 0xff)
52 PCI_OP(read, word, u16 *, *value = 0xffff)
53 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
54 PCI_OP(write, byte, u8, )
55 PCI_OP(write, word, u16, )
56 PCI_OP(write, dword, u32, )
58 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
59 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
61 int offset, type val) \
65 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
70 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
75 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
76 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
78 int offset, type val) \
80 u32 val32, mask, ldata, shift; \
82 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
85 shift = ((offset & (int)off_mask) * 8); \
86 ldata = (((unsigned long)val) & val_mask) << shift; \
87 mask = val_mask << shift; \
88 val32 = (val32 & ~mask) | ldata; \
90 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
96 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
97 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
98 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
99 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
101 /* Get a virtual address associated with a BAR region */
102 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
104 pci_addr_t pci_bus_addr;
107 /* read BAR address */
108 pci_read_config_dword(pdev, bar, &bar_response);
109 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
112 * Pass "0" as the length argument to pci_bus_to_virt. The arg
113 * isn't actualy used on any platform because u-boot assumes a static
114 * linear mapping. In the future, this could read the BAR size
115 * and pass that as the size if needed.
117 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
124 static struct pci_controller* hose_head;
126 void pci_register_hose(struct pci_controller* hose)
128 struct pci_controller **phose = &hose_head;
131 phose = &(*phose)->next;
138 struct pci_controller *pci_bus_to_hose(int bus)
140 struct pci_controller *hose;
142 for (hose = hose_head; hose; hose = hose->next) {
143 if (bus >= hose->first_busno && bus <= hose->last_busno)
147 printf("pci_bus_to_hose() failed\n");
151 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
153 struct pci_controller *hose;
155 for (hose = hose_head; hose; hose = hose->next) {
156 if (hose->cfg_addr == cfg_addr)
163 int pci_last_busno(void)
165 struct pci_controller *hose = hose_head;
173 return hose->last_busno;
176 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
178 struct pci_controller * hose;
182 int i, bus, found_multi = 0;
184 for (hose = hose_head; hose; hose = hose->next) {
185 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
186 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
188 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
190 for (bdf = PCI_BDF(bus, 0, 0);
191 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
192 bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
193 PCI_MAX_PCI_FUNCTIONS - 1);
195 bdf < PCI_BDF(bus + 1, 0, 0);
197 bdf += PCI_BDF(0, 0, 1)) {
198 if (pci_skip_dev(hose, bdf))
201 if (!PCI_FUNC(bdf)) {
202 pci_read_config_byte(bdf,
206 found_multi = header_type & 0x80;
212 pci_read_config_word(bdf,
215 pci_read_config_word(bdf,
219 for (i = 0; ids[i].vendor != 0; i++) {
220 if (vendor == ids[i].vendor &&
221 device == ids[i].device) {
234 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
236 static struct pci_device_id ids[2] = {{}, {0, 0}};
238 ids[0].vendor = vendor;
239 ids[0].device = device;
241 return pci_find_devices(ids, index);
248 int __pci_hose_phys_to_bus(struct pci_controller *hose,
249 phys_addr_t phys_addr,
251 unsigned long skip_mask,
254 struct pci_region *res;
258 for (i = 0; i < hose->region_count; i++) {
259 res = &hose->regions[i];
261 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
264 if (res->flags & skip_mask)
267 bus_addr = phys_addr - res->phys_start + res->bus_start;
269 if (bus_addr >= res->bus_start &&
270 bus_addr < res->bus_start + res->size) {
279 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
280 phys_addr_t phys_addr,
283 pci_addr_t bus_addr = 0;
287 puts("pci_hose_phys_to_bus: invalid hose\n");
292 * if PCI_REGION_MEM is set we do a two pass search with preference
293 * on matches that don't have PCI_REGION_SYS_MEMORY set
295 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
296 ret = __pci_hose_phys_to_bus(hose, phys_addr,
297 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
302 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
305 puts("pci_hose_phys_to_bus: invalid physical address\n");
310 int __pci_hose_bus_to_phys(struct pci_controller *hose,
313 unsigned long skip_mask,
316 struct pci_region *res;
319 for (i = 0; i < hose->region_count; i++) {
320 res = &hose->regions[i];
322 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
325 if (res->flags & skip_mask)
328 if (bus_addr >= res->bus_start &&
329 (bus_addr - res->bus_start) < res->size) {
330 *pa = (bus_addr - res->bus_start + res->phys_start);
338 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
342 phys_addr_t phys_addr = 0;
346 puts("pci_hose_bus_to_phys: invalid hose\n");
351 * if PCI_REGION_MEM is set we do a two pass search with preference
352 * on matches that don't have PCI_REGION_SYS_MEMORY set
354 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
355 ret = __pci_hose_bus_to_phys(hose, bus_addr,
356 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
361 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
364 puts("pci_hose_bus_to_phys: invalid physical address\n");
369 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
374 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
375 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
378 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
383 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
384 pci_hose_read_config_dword(hose, dev, bar, &addr);
385 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
386 return addr & PCI_BASE_ADDRESS_IO_MASK;
388 return addr & PCI_BASE_ADDRESS_MEM_MASK;
391 int pci_hose_config_device(struct pci_controller *hose,
395 unsigned long command)
398 unsigned int old_command;
399 pci_addr_t bar_value;
402 int bar, found_mem64;
404 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
407 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
409 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
410 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
411 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
418 /* Check the BAR type and set our address mask */
419 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
420 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
421 /* round up region base address to a multiple of size */
422 io = ((io - 1) | (bar_size - 1)) + 1;
424 /* compute new region base address */
427 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
428 PCI_BASE_ADDRESS_MEM_TYPE_64) {
429 u32 bar_response_upper;
431 pci_hose_write_config_dword(hose, dev, bar + 4,
433 pci_hose_read_config_dword(hose, dev, bar + 4,
434 &bar_response_upper);
436 bar64 = ((u64)bar_response_upper << 32) | bar_response;
438 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
441 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
444 /* round up region base address to multiple of size */
445 mem = ((mem - 1) | (bar_size - 1)) + 1;
447 /* compute new region base address */
448 mem = mem + bar_size;
451 /* Write it out and update our limit */
452 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
456 #ifdef CONFIG_SYS_PCI_64BIT
457 pci_hose_write_config_dword(hose, dev, bar,
458 (u32)(bar_value >> 32));
460 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
465 /* Configure Cache Line Size Register */
466 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
468 /* Configure Latency Timer */
469 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
471 /* Disable interrupt line, if device says it wants to use interrupts */
472 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
474 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
477 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
478 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
479 (old_command & 0xffff0000) | command);
488 struct pci_config_table *pci_find_config(struct pci_controller *hose,
489 unsigned short class,
496 struct pci_config_table *table;
498 for (table = hose->config_table; table && table->vendor; table++) {
499 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
500 (table->device == PCI_ANY_ID || table->device == device) &&
501 (table->class == PCI_ANY_ID || table->class == class) &&
502 (table->bus == PCI_ANY_ID || table->bus == bus) &&
503 (table->dev == PCI_ANY_ID || table->dev == dev) &&
504 (table->func == PCI_ANY_ID || table->func == func)) {
512 void pci_cfgfunc_config_device(struct pci_controller *hose,
514 struct pci_config_table *entry)
516 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
520 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
521 pci_dev_t dev, struct pci_config_table *entry)
526 * HJF: Changed this to return int. I think this is required
527 * to get the correct result when scanning bridges
529 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
531 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
532 const char * pci_class_str(u8 class)
535 case PCI_CLASS_NOT_DEFINED:
536 return "Build before PCI Rev2.0";
538 case PCI_BASE_CLASS_STORAGE:
539 return "Mass storage controller";
541 case PCI_BASE_CLASS_NETWORK:
542 return "Network controller";
544 case PCI_BASE_CLASS_DISPLAY:
545 return "Display controller";
547 case PCI_BASE_CLASS_MULTIMEDIA:
548 return "Multimedia device";
550 case PCI_BASE_CLASS_MEMORY:
551 return "Memory controller";
553 case PCI_BASE_CLASS_BRIDGE:
554 return "Bridge device";
556 case PCI_BASE_CLASS_COMMUNICATION:
557 return "Simple comm. controller";
559 case PCI_BASE_CLASS_SYSTEM:
560 return "Base system peripheral";
562 case PCI_BASE_CLASS_INPUT:
563 return "Input device";
565 case PCI_BASE_CLASS_DOCKING:
566 return "Docking station";
568 case PCI_BASE_CLASS_PROCESSOR:
571 case PCI_BASE_CLASS_SERIAL:
572 return "Serial bus controller";
574 case PCI_BASE_CLASS_INTELLIGENT:
575 return "Intelligent controller";
577 case PCI_BASE_CLASS_SATELLITE:
578 return "Satellite controller";
580 case PCI_BASE_CLASS_CRYPT:
581 return "Cryptographic device";
583 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
586 case PCI_CLASS_OTHERS:
587 return "Does not fit any class";
594 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
596 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
599 * Check if pci device should be skipped in configuration
601 if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
602 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
604 * Only skip configuration if "pciconfighost" is not set
606 if (getenv("pciconfighost") == NULL)
616 #ifdef CONFIG_PCI_SCAN_SHOW
617 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
619 if (dev == PCI_BDF(hose->first_busno, 0, 0))
624 #endif /* CONFIG_PCI_SCAN_SHOW */
626 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
628 unsigned int sub_bus, found_multi = 0;
629 unsigned short vendor, device, class;
630 unsigned char header_type;
631 #ifndef CONFIG_PCI_PNP
632 struct pci_config_table *cfg;
635 #ifdef CONFIG_PCI_SCAN_SHOW
636 static int indent = 0;
641 for (dev = PCI_BDF(bus,0,0);
642 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
643 PCI_MAX_PCI_FUNCTIONS - 1);
644 dev += PCI_BDF(0, 0, 1)) {
646 if (pci_skip_dev(hose, dev))
649 if (PCI_FUNC(dev) && !found_multi)
652 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
654 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
656 if (vendor == 0xffff || vendor == 0x0000)
660 found_multi = header_type & 0x80;
662 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
663 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
665 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
666 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
668 #ifdef CONFIG_PCI_FIXUP_DEV
669 board_pci_fixup_dev(hose, dev, vendor, device, class);
672 #ifdef CONFIG_PCI_SCAN_SHOW
675 /* Print leading space, including bus indentation */
676 printf("%*c", indent + 1, ' ');
678 if (pci_print_dev(hose, dev)) {
679 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
680 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
681 vendor, device, pci_class_str(class >> 8));
685 #ifdef CONFIG_PCI_PNP
686 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
689 cfg = pci_find_config(hose, class, vendor, device,
690 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
692 cfg->config_device(hose, dev, cfg);
693 sub_bus = max(sub_bus,
694 (unsigned int)hose->current_busno);
698 #ifdef CONFIG_PCI_SCAN_SHOW
703 hose->fixup_irq(hose, dev);
709 int pci_hose_scan(struct pci_controller *hose)
711 #if defined(CONFIG_PCI_BOOTDELAY)
712 static int pcidelay_done;
716 if (!pcidelay_done) {
717 /* wait "pcidelay" ms (if defined)... */
718 s = getenv("pcidelay");
720 int val = simple_strtoul(s, NULL, 10);
721 for (i = 0; i < val; i++)
726 #endif /* CONFIG_PCI_BOOTDELAY */
729 * Start scan at current_busno.
730 * PCIe will start scan at first_busno+1.
732 /* For legacy support, ensure current >= first */
733 if (hose->first_busno > hose->current_busno)
734 hose->current_busno = hose->first_busno;
735 #ifdef CONFIG_PCI_PNP
736 pciauto_config_init(hose);
738 return pci_hose_scan_bus(hose, hose->current_busno);
745 /* now call board specific pci_init()... */
749 /* Returns the address of the requested capability structure within the
750 * device's PCI configuration space or 0 in case the device does not
753 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
759 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
761 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
764 pos = pci_find_cap(hose, dev, pos, cap);
769 /* Find the header pointer to the Capabilities*/
770 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
775 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
777 if (!(status & PCI_STATUS_CAP_LIST))
781 case PCI_HEADER_TYPE_NORMAL:
782 case PCI_HEADER_TYPE_BRIDGE:
783 return PCI_CAPABILITY_LIST;
784 case PCI_HEADER_TYPE_CARDBUS:
785 return PCI_CB_CAPABILITY_LIST;
791 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
793 int ttl = PCI_FIND_CAP_TTL;
798 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
799 if (next_pos < CAP_START_POS)
802 pos = (int) next_pos;
803 pci_hose_read_config_byte(hose, dev,
804 pos + PCI_CAP_LIST_ID, &id);
809 pos += PCI_CAP_LIST_NEXT;