2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define PCI_HOSE_OP(rw, size, type) \
25 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
27 int offset, type value) \
29 return hose->rw##_##size(hose, dev, offset, value); \
32 PCI_HOSE_OP(read, byte, u8 *)
33 PCI_HOSE_OP(read, word, u16 *)
34 PCI_HOSE_OP(read, dword, u32 *)
35 PCI_HOSE_OP(write, byte, u8)
36 PCI_HOSE_OP(write, word, u16)
37 PCI_HOSE_OP(write, dword, u32)
39 #define PCI_OP(rw, size, type, error_code) \
40 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
42 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
50 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
53 PCI_OP(read, byte, u8 *, *value = 0xff)
54 PCI_OP(read, word, u16 *, *value = 0xffff)
55 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
56 PCI_OP(write, byte, u8, )
57 PCI_OP(write, word, u16, )
58 PCI_OP(write, dword, u32, )
60 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
61 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
63 int offset, type val) \
67 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
72 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
77 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
78 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
80 int offset, type val) \
82 u32 val32, mask, ldata, shift; \
84 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
87 shift = ((offset & (int)off_mask) * 8); \
88 ldata = (((unsigned long)val) & val_mask) << shift; \
89 mask = val_mask << shift; \
90 val32 = (val32 & ~mask) | ldata; \
92 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
98 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
99 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
100 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
101 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
103 /* Get a virtual address associated with a BAR region */
104 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
106 pci_addr_t pci_bus_addr;
109 /* read BAR address */
110 pci_read_config_dword(pdev, bar, &bar_response);
111 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
114 * Pass "0" as the length argument to pci_bus_to_virt. The arg
115 * isn't actualy used on any platform because u-boot assumes a static
116 * linear mapping. In the future, this could read the BAR size
117 * and pass that as the size if needed.
119 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
126 static struct pci_controller* hose_head;
128 struct pci_controller *pci_get_hose_head(void)
136 void pci_register_hose(struct pci_controller* hose)
138 struct pci_controller **phose = &hose_head;
141 phose = &(*phose)->next;
148 struct pci_controller *pci_bus_to_hose(int bus)
150 struct pci_controller *hose;
152 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
153 if (bus >= hose->first_busno && bus <= hose->last_busno)
157 printf("pci_bus_to_hose() failed\n");
161 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
163 struct pci_controller *hose;
165 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
166 if (hose->cfg_addr == cfg_addr)
173 int pci_last_busno(void)
175 struct pci_controller *hose = pci_get_hose_head();
183 return hose->last_busno;
186 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
188 struct pci_controller * hose;
192 int i, bus, found_multi = 0;
194 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
195 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
196 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
198 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
200 for (bdf = PCI_BDF(bus, 0, 0);
201 bdf < PCI_BDF(bus + 1, 0, 0);
202 bdf += PCI_BDF(0, 0, 1)) {
203 if (pci_skip_dev(hose, bdf))
206 if (!PCI_FUNC(bdf)) {
207 pci_read_config_byte(bdf,
211 found_multi = header_type & 0x80;
217 pci_read_config_word(bdf,
220 pci_read_config_word(bdf,
224 for (i = 0; ids[i].vendor != 0; i++) {
225 if (vendor == ids[i].vendor &&
226 device == ids[i].device) {
239 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
241 struct pci_device_id ids[2] = { {}, {0, 0} };
243 ids[0].vendor = vendor;
244 ids[0].device = device;
246 return pci_find_devices(ids, index);
253 int __pci_hose_phys_to_bus(struct pci_controller *hose,
254 phys_addr_t phys_addr,
256 unsigned long skip_mask,
259 struct pci_region *res;
263 for (i = 0; i < hose->region_count; i++) {
264 res = &hose->regions[i];
266 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
269 if (res->flags & skip_mask)
272 bus_addr = phys_addr - res->phys_start + res->bus_start;
274 if (bus_addr >= res->bus_start &&
275 bus_addr < res->bus_start + res->size) {
284 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
285 phys_addr_t phys_addr,
288 pci_addr_t bus_addr = 0;
292 puts("pci_hose_phys_to_bus: invalid hose\n");
297 * if PCI_REGION_MEM is set we do a two pass search with preference
298 * on matches that don't have PCI_REGION_SYS_MEMORY set
300 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
301 ret = __pci_hose_phys_to_bus(hose, phys_addr,
302 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
307 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
310 puts("pci_hose_phys_to_bus: invalid physical address\n");
315 int __pci_hose_bus_to_phys(struct pci_controller *hose,
318 unsigned long skip_mask,
321 struct pci_region *res;
324 for (i = 0; i < hose->region_count; i++) {
325 res = &hose->regions[i];
327 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
330 if (res->flags & skip_mask)
333 if (bus_addr >= res->bus_start &&
334 (bus_addr - res->bus_start) < res->size) {
335 *pa = (bus_addr - res->bus_start + res->phys_start);
343 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
347 phys_addr_t phys_addr = 0;
351 puts("pci_hose_bus_to_phys: invalid hose\n");
356 * if PCI_REGION_MEM is set we do a two pass search with preference
357 * on matches that don't have PCI_REGION_SYS_MEMORY set
359 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
360 ret = __pci_hose_bus_to_phys(hose, bus_addr,
361 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
366 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
369 puts("pci_hose_bus_to_phys: invalid physical address\n");
374 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
379 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
380 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
383 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
388 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
389 pci_hose_read_config_dword(hose, dev, bar, &addr);
390 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
391 return addr & PCI_BASE_ADDRESS_IO_MASK;
393 return addr & PCI_BASE_ADDRESS_MEM_MASK;
396 int pci_hose_config_device(struct pci_controller *hose,
400 unsigned long command)
403 unsigned int old_command;
404 pci_addr_t bar_value;
407 int bar, found_mem64;
409 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
412 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
414 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
415 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
416 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
423 /* Check the BAR type and set our address mask */
424 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
425 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
426 /* round up region base address to a multiple of size */
427 io = ((io - 1) | (bar_size - 1)) + 1;
429 /* compute new region base address */
432 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
433 PCI_BASE_ADDRESS_MEM_TYPE_64) {
434 u32 bar_response_upper;
436 pci_hose_write_config_dword(hose, dev, bar + 4,
438 pci_hose_read_config_dword(hose, dev, bar + 4,
439 &bar_response_upper);
441 bar64 = ((u64)bar_response_upper << 32) | bar_response;
443 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
446 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
449 /* round up region base address to multiple of size */
450 mem = ((mem - 1) | (bar_size - 1)) + 1;
452 /* compute new region base address */
453 mem = mem + bar_size;
456 /* Write it out and update our limit */
457 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
461 #ifdef CONFIG_SYS_PCI_64BIT
462 pci_hose_write_config_dword(hose, dev, bar,
463 (u32)(bar_value >> 32));
465 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
470 /* Configure Cache Line Size Register */
471 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
473 /* Configure Latency Timer */
474 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
476 /* Disable interrupt line, if device says it wants to use interrupts */
477 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
479 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
482 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
483 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
484 (old_command & 0xffff0000) | command);
493 struct pci_config_table *pci_find_config(struct pci_controller *hose,
494 unsigned short class,
501 struct pci_config_table *table;
503 for (table = hose->config_table; table && table->vendor; table++) {
504 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
505 (table->device == PCI_ANY_ID || table->device == device) &&
506 (table->class == PCI_ANY_ID || table->class == class) &&
507 (table->bus == PCI_ANY_ID || table->bus == bus) &&
508 (table->dev == PCI_ANY_ID || table->dev == dev) &&
509 (table->func == PCI_ANY_ID || table->func == func)) {
517 void pci_cfgfunc_config_device(struct pci_controller *hose,
519 struct pci_config_table *entry)
521 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
525 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
526 pci_dev_t dev, struct pci_config_table *entry)
531 * HJF: Changed this to return int. I think this is required
532 * to get the correct result when scanning bridges
534 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
536 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
537 const char * pci_class_str(u8 class)
540 case PCI_CLASS_NOT_DEFINED:
541 return "Build before PCI Rev2.0";
543 case PCI_BASE_CLASS_STORAGE:
544 return "Mass storage controller";
546 case PCI_BASE_CLASS_NETWORK:
547 return "Network controller";
549 case PCI_BASE_CLASS_DISPLAY:
550 return "Display controller";
552 case PCI_BASE_CLASS_MULTIMEDIA:
553 return "Multimedia device";
555 case PCI_BASE_CLASS_MEMORY:
556 return "Memory controller";
558 case PCI_BASE_CLASS_BRIDGE:
559 return "Bridge device";
561 case PCI_BASE_CLASS_COMMUNICATION:
562 return "Simple comm. controller";
564 case PCI_BASE_CLASS_SYSTEM:
565 return "Base system peripheral";
567 case PCI_BASE_CLASS_INPUT:
568 return "Input device";
570 case PCI_BASE_CLASS_DOCKING:
571 return "Docking station";
573 case PCI_BASE_CLASS_PROCESSOR:
576 case PCI_BASE_CLASS_SERIAL:
577 return "Serial bus controller";
579 case PCI_BASE_CLASS_INTELLIGENT:
580 return "Intelligent controller";
582 case PCI_BASE_CLASS_SATELLITE:
583 return "Satellite controller";
585 case PCI_BASE_CLASS_CRYPT:
586 return "Cryptographic device";
588 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
591 case PCI_CLASS_OTHERS:
592 return "Does not fit any class";
599 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
601 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
604 * Check if pci device should be skipped in configuration
606 if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
607 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
609 * Only skip configuration if "pciconfighost" is not set
611 if (getenv("pciconfighost") == NULL)
621 #ifdef CONFIG_PCI_SCAN_SHOW
622 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
624 if (dev == PCI_BDF(hose->first_busno, 0, 0))
629 #endif /* CONFIG_PCI_SCAN_SHOW */
631 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
633 unsigned int sub_bus, found_multi = 0;
634 unsigned short vendor, device, class;
635 unsigned char header_type;
636 #ifndef CONFIG_PCI_PNP
637 struct pci_config_table *cfg;
640 #ifdef CONFIG_PCI_SCAN_SHOW
641 static int indent = 0;
646 for (dev = PCI_BDF(bus,0,0);
647 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
648 PCI_MAX_PCI_FUNCTIONS - 1);
649 dev += PCI_BDF(0, 0, 1)) {
651 if (pci_skip_dev(hose, dev))
654 if (PCI_FUNC(dev) && !found_multi)
657 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
659 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
661 if (vendor == 0xffff || vendor == 0x0000)
665 found_multi = header_type & 0x80;
667 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
668 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
670 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
671 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
673 #ifdef CONFIG_PCI_FIXUP_DEV
674 board_pci_fixup_dev(hose, dev, vendor, device, class);
677 #ifdef CONFIG_PCI_SCAN_SHOW
680 /* Print leading space, including bus indentation */
681 printf("%*c", indent + 1, ' ');
683 if (pci_print_dev(hose, dev)) {
684 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
685 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
686 vendor, device, pci_class_str(class >> 8));
690 #ifdef CONFIG_PCI_PNP
691 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
694 cfg = pci_find_config(hose, class, vendor, device,
695 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
697 cfg->config_device(hose, dev, cfg);
698 sub_bus = max(sub_bus,
699 (unsigned int)hose->current_busno);
703 #ifdef CONFIG_PCI_SCAN_SHOW
708 hose->fixup_irq(hose, dev);
714 int pci_hose_scan(struct pci_controller *hose)
716 #if defined(CONFIG_PCI_BOOTDELAY)
720 if (!gd->pcidelay_done) {
721 /* wait "pcidelay" ms (if defined)... */
722 s = getenv("pcidelay");
724 int val = simple_strtoul(s, NULL, 10);
725 for (i = 0; i < val; i++)
728 gd->pcidelay_done = 1;
730 #endif /* CONFIG_PCI_BOOTDELAY */
733 * Start scan at current_busno.
734 * PCIe will start scan at first_busno+1.
736 /* For legacy support, ensure current >= first */
737 if (hose->first_busno > hose->current_busno)
738 hose->current_busno = hose->first_busno;
739 #ifdef CONFIG_PCI_PNP
740 pciauto_config_init(hose);
742 return pci_hose_scan_bus(hose, hose->current_busno);
749 /* now call board specific pci_init()... */
753 /* Returns the address of the requested capability structure within the
754 * device's PCI configuration space or 0 in case the device does not
757 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
763 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
765 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
768 pos = pci_find_cap(hose, dev, pos, cap);
773 /* Find the header pointer to the Capabilities*/
774 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
779 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
781 if (!(status & PCI_STATUS_CAP_LIST))
785 case PCI_HEADER_TYPE_NORMAL:
786 case PCI_HEADER_TYPE_BRIDGE:
787 return PCI_CAPABILITY_LIST;
788 case PCI_HEADER_TYPE_CARDBUS:
789 return PCI_CB_CAPABILITY_LIST;
795 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
797 int ttl = PCI_FIND_CAP_TTL;
802 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
803 if (next_pos < CAP_START_POS)
806 pos = (int) next_pos;
807 pci_hose_read_config_byte(hose, dev,
808 pos + PCI_CAP_LIST_ID, &id);
813 pos += PCI_CAP_LIST_NEXT;