2 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
4 * Driver for SPI controller on DaVinci. Based on atmel_spi.c
7 * Copyright (C) 2007 Atmel Corporation
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/hardware.h>
32 #include "davinci_spi.h"
39 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
40 unsigned int max_hz, unsigned int mode)
42 struct davinci_spi_slave *ds;
44 if (!spi_cs_is_valid(bus, cs))
47 ds = malloc(sizeof(*ds));
53 ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE;
59 void spi_free_slave(struct spi_slave *slave)
61 struct davinci_spi_slave *ds = to_davinci_spi(slave);
66 int spi_claim_bus(struct spi_slave *slave)
68 struct davinci_spi_slave *ds = to_davinci_spi(slave);
71 /* Enable the SPI hardware */
72 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
74 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
76 /* Set master mode, powered up and not activated */
77 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
79 /* CS, CLK, SIMO and SOMI are functional pins */
80 writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK |
81 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
84 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
87 * Use following format:
88 * character length = 8,
89 * clock signal delayed by half clk cycle,
90 * clock low in idle state - Mode 0,
91 * MSB shifted out first
93 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
94 (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
97 * Including a minor delay. No science here. Should be good even with
100 writel((50 << SPI_C2TDELAY_SHIFT) |
101 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
103 /* default chip select register */
104 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
107 writel(0, &ds->regs->int0);
108 writel(0, &ds->regs->lvl);
111 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
116 void spi_release_bus(struct spi_slave *slave)
118 struct davinci_spi_slave *ds = to_davinci_spi(slave);
120 /* Disable the SPI hardware */
121 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
125 * This functions needs to act like a macro to avoid pipeline reloads in the
126 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
127 * appears to be zero bytes (da830).
129 __attribute__((always_inline))
130 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
135 writel(data, &ds->regs->dat1);
137 /* wait for the data to clock in/out */
138 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
144 static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
145 u8 *rxp, unsigned long flags)
147 struct davinci_spi_slave *ds = to_davinci_spi(slave);
148 unsigned int data1_reg_val;
150 /* enable CS hold, CS[n] and clear the data bits */
151 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
152 (slave->cs << SPIDAT1_CSNR_SHIFT));
154 /* wait till TXFULL is deasserted */
155 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
158 /* preload the TX buffer to avoid clock starvation */
159 writel(data1_reg_val, &ds->regs->dat1);
161 /* keep reading 1 byte until only 1 byte left */
163 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
165 /* clear CS hold when we reach the end */
166 if (flags & SPI_XFER_END)
167 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
169 /* read the last byte */
170 *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
175 static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
176 const u8 *txp, unsigned long flags)
178 struct davinci_spi_slave *ds = to_davinci_spi(slave);
179 unsigned int data1_reg_val;
181 /* enable CS hold and clear the data bits */
182 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
183 (slave->cs << SPIDAT1_CSNR_SHIFT));
185 /* wait till TXFULL is deasserted */
186 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
189 /* preload the TX buffer to avoid clock starvation */
191 writel(data1_reg_val | *txp++, &ds->regs->dat1);
195 /* keep writing 1 byte until only 1 byte left */
197 davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
199 /* clear CS hold when we reach the end */
200 if (flags & SPI_XFER_END)
201 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
203 /* write the last byte */
204 davinci_spi_xfer_data(ds, data1_reg_val | *txp);
209 #ifndef CONFIG_SPI_HALF_DUPLEX
210 static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
211 u8 *rxp, const u8 *txp, unsigned long flags)
213 struct davinci_spi_slave *ds = to_davinci_spi(slave);
214 unsigned int data1_reg_val;
216 /* enable CS hold and clear the data bits */
217 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
218 (slave->cs << SPIDAT1_CSNR_SHIFT));
220 /* wait till TXFULL is deasserted */
221 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
224 /* keep reading and writing 1 byte until only 1 byte left */
226 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
228 /* clear CS hold when we reach the end */
229 if (flags & SPI_XFER_END)
230 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
232 /* read and write the last byte */
233 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
239 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
240 const void *dout, void *din, unsigned long flags)
245 /* Finish any previously submitted transfers */
249 * It's not clear how non-8-bit-aligned transfers are supposed to be
250 * represented as a stream of bytes...this is a limitation of
251 * the current SPI interface - here we terminate on receiving such a
255 /* Errors always terminate an ongoing transfer */
256 flags |= SPI_XFER_END;
263 return davinci_spi_read(slave, len, din, flags);
265 return davinci_spi_write(slave, len, dout, flags);
266 #ifndef CONFIG_SPI_HALF_DUPLEX
268 return davinci_spi_read_write(slave, len, din, dout, flags);
272 if (flags & SPI_XFER_END) {
274 davinci_spi_write(slave, 1, &dummy, flags);
279 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
281 return bus == 0 && cs == 0;
284 void spi_cs_activate(struct spi_slave *slave)
289 void spi_cs_deactivate(struct spi_slave *slave)