2 * Texas Instruments AM35x "glue layer"
4 * Copyright (c) 2010, by Texas Instruments
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/clk.h>
34 #include <linux/err.h>
36 #include <linux/platform_device.h>
37 #include <linux/dma-mapping.h>
42 #include <asm/omap_musb.h>
43 #include "linux-compat.h"
46 #include "musb_core.h"
49 * AM35x specific definitions
51 /* USB 2.0 OTG module registers */
52 #define USB_REVISION_REG 0x00
53 #define USB_CTRL_REG 0x04
54 #define USB_STAT_REG 0x08
55 #define USB_EMULATION_REG 0x0c
57 #define USB_AUTOREQ_REG 0x14
58 #define USB_SRP_FIX_TIME_REG 0x18
59 #define USB_TEARDOWN_REG 0x1c
60 #define EP_INTR_SRC_REG 0x20
61 #define EP_INTR_SRC_SET_REG 0x24
62 #define EP_INTR_SRC_CLEAR_REG 0x28
63 #define EP_INTR_MASK_REG 0x2c
64 #define EP_INTR_MASK_SET_REG 0x30
65 #define EP_INTR_MASK_CLEAR_REG 0x34
66 #define EP_INTR_SRC_MASKED_REG 0x38
67 #define CORE_INTR_SRC_REG 0x40
68 #define CORE_INTR_SRC_SET_REG 0x44
69 #define CORE_INTR_SRC_CLEAR_REG 0x48
70 #define CORE_INTR_MASK_REG 0x4c
71 #define CORE_INTR_MASK_SET_REG 0x50
72 #define CORE_INTR_MASK_CLEAR_REG 0x54
73 #define CORE_INTR_SRC_MASKED_REG 0x58
75 #define USB_END_OF_INTR_REG 0x60
77 /* Control register bits */
78 #define AM35X_SOFT_RESET_MASK 1
80 /* USB interrupt register bits */
81 #define AM35X_INTR_USB_SHIFT 16
82 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
83 #define AM35X_INTR_DRVVBUS 0x100
84 #define AM35X_INTR_RX_SHIFT 16
85 #define AM35X_INTR_TX_SHIFT 0
86 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
87 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
88 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
89 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
91 #define USB_MENTOR_CORE_OFFSET 0x400
95 struct platform_device *musb;
99 #define glue_to_musb(g) platform_get_drvdata(g->musb)
102 * am35x_musb_enable - enable interrupts
104 static void am35x_musb_enable(struct musb *musb)
106 void __iomem *reg_base = musb->ctrl_base;
109 /* Workaround: setup IRQs through both register sets. */
110 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
111 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
113 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
114 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
116 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
117 if (is_otg_enabled(musb))
118 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
119 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
123 * am35x_musb_disable - disable HDRC and flush interrupts
125 static void am35x_musb_disable(struct musb *musb)
127 void __iomem *reg_base = musb->ctrl_base;
129 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
130 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
131 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
132 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
133 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
137 #define portstate(stmt) stmt
139 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
141 WARN_ON(is_on && is_peripheral_active(musb));
144 #define POLL_SECONDS 2
146 static struct timer_list otg_workaround;
148 static void otg_timer(unsigned long _musb)
150 struct musb *musb = (void *)_musb;
151 void __iomem *mregs = musb->mregs;
156 * We poll because AM35x's won't expose several OTG-critical
157 * status change events (from the transceiver) otherwise.
159 devctl = musb_readb(mregs, MUSB_DEVCTL);
160 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
161 otg_state_string(musb->xceiv->state));
163 spin_lock_irqsave(&musb->lock, flags);
164 switch (musb->xceiv->state) {
165 case OTG_STATE_A_WAIT_BCON:
166 devctl &= ~MUSB_DEVCTL_SESSION;
167 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
169 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
170 if (devctl & MUSB_DEVCTL_BDEVICE) {
171 musb->xceiv->state = OTG_STATE_B_IDLE;
174 musb->xceiv->state = OTG_STATE_A_IDLE;
178 case OTG_STATE_A_WAIT_VFALL:
179 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
180 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
181 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
183 case OTG_STATE_B_IDLE:
184 if (!is_peripheral_enabled(musb))
187 devctl = musb_readb(mregs, MUSB_DEVCTL);
188 if (devctl & MUSB_DEVCTL_BDEVICE)
189 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
191 musb->xceiv->state = OTG_STATE_A_IDLE;
196 spin_unlock_irqrestore(&musb->lock, flags);
199 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
201 static unsigned long last_timer;
203 if (!is_otg_enabled(musb))
207 timeout = jiffies + msecs_to_jiffies(3);
209 /* Never idle if active, or when VBUS timeout is not set as host */
210 if (musb->is_active || (musb->a_wait_bcon == 0 &&
211 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
212 dev_dbg(musb->controller, "%s active, deleting timer\n",
213 otg_state_string(musb->xceiv->state));
214 del_timer(&otg_workaround);
215 last_timer = jiffies;
219 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
220 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
223 last_timer = timeout;
225 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
226 otg_state_string(musb->xceiv->state),
227 jiffies_to_msecs(timeout - jiffies));
228 mod_timer(&otg_workaround, timeout);
232 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
234 struct musb *musb = hci;
235 void __iomem *reg_base = musb->ctrl_base;
237 struct device *dev = musb->controller;
238 struct musb_hdrc_platform_data *plat = dev->platform_data;
239 struct omap_musb_board_data *data = plat->board_data;
240 struct usb_otg *otg = musb->xceiv->otg;
242 struct omap_musb_board_data *data =
243 (struct omap_musb_board_data *)musb->controller;
246 irqreturn_t ret = IRQ_NONE;
251 * It seems that on AM35X interrupt registers can be updated
252 * before core registers. This confuses the code.
253 * As a workaround add a small delay here.
257 spin_lock_irqsave(&musb->lock, flags);
259 /* Get endpoint interrupts */
260 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
263 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
266 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
268 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
271 /* Get usb core interrupts */
272 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
273 if (!usbintr && !epintr)
277 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
280 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
284 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
285 * AM35x's missing ID change IRQ. We need an ID change IRQ to
286 * switch appropriately between halves of the OTG state machine.
287 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
288 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
289 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
291 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
292 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
293 void __iomem *mregs = musb->mregs;
294 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
297 err = is_host_enabled(musb) && (musb->int_usb &
298 MUSB_INTR_VBUSERROR);
301 * The Mentor core doesn't debounce VBUS as needed
302 * to cope with device connect current spikes. This
303 * means it's not uncommon for bus-powered devices
304 * to get VBUS errors during enumeration.
306 * This is a workaround, but newer RTL from Mentor
307 * seems to allow a better one: "re"-starting sessions
308 * without waiting for VBUS to stop registering in
311 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
312 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
313 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
314 WARNING("VBUS error workaround (delay coming)\n");
315 } else if (is_host_enabled(musb) && drvvbus) {
318 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
319 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
320 del_timer(&otg_workaround);
325 musb->xceiv->state = OTG_STATE_B_IDLE;
326 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
329 /* NOTE: this must complete power-on within 100 ms. */
330 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
331 drvvbus ? "on" : "off",
332 otg_state_string(musb->xceiv->state),
339 if (musb->int_tx || musb->int_rx || musb->int_usb)
340 ret |= musb_interrupt(musb);
343 /* EOI needs to be written for the IRQ to be re-asserted. */
344 if (ret == IRQ_HANDLED || epintr || usbintr) {
345 /* clear level interrupt */
349 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
353 /* Poll for ID change */
354 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
355 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
358 spin_unlock_irqrestore(&musb->lock, flags);
364 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
366 struct device *dev = musb->controller;
367 struct musb_hdrc_platform_data *plat = dev->platform_data;
368 struct omap_musb_board_data *data = plat->board_data;
372 data->set_mode(musb_mode);
380 static int am35x_musb_init(struct musb *musb)
383 struct device *dev = musb->controller;
384 struct musb_hdrc_platform_data *plat = dev->platform_data;
385 struct omap_musb_board_data *data = plat->board_data;
387 struct omap_musb_board_data *data =
388 (struct omap_musb_board_data *)musb->controller;
390 void __iomem *reg_base = musb->ctrl_base;
393 musb->mregs += USB_MENTOR_CORE_OFFSET;
395 /* Returns zero if e.g. not clocked */
396 rev = musb_readl(reg_base, USB_REVISION_REG);
401 usb_nop_xceiv_register();
402 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
403 if (IS_ERR_OR_NULL(musb->xceiv))
406 if (is_host_enabled(musb))
407 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
414 /* Reset the controller */
415 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
417 /* Start the on-chip PHY and its PLL. */
418 if (data->set_phy_power)
419 data->set_phy_power(1);
423 musb->isr = am35x_musb_interrupt;
425 /* clear level interrupt */
432 static int am35x_musb_exit(struct musb *musb)
435 struct device *dev = musb->controller;
436 struct musb_hdrc_platform_data *plat = dev->platform_data;
437 struct omap_musb_board_data *data = plat->board_data;
439 struct omap_musb_board_data *data =
440 (struct omap_musb_board_data *)musb->controller;
444 if (is_host_enabled(musb))
445 del_timer_sync(&otg_workaround);
448 /* Shutdown the on-chip PHY and its PLL. */
449 if (data->set_phy_power)
450 data->set_phy_power(0);
453 usb_put_phy(musb->xceiv);
454 usb_nop_xceiv_unregister();
460 /* AM35x supports only 32bit read operation */
461 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
463 void __iomem *fifo = hw_ep->fifo;
467 /* Read for 32bit-aligned destination address */
468 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
469 readsl(fifo, dst, len >> 2);
474 * Now read the remaining 1 to 3 byte or complete length if
478 for (i = 0; i < (len >> 2); i++) {
479 *(u32 *) dst = musb_readl(fifo, 0);
485 val = musb_readl(fifo, 0);
486 memcpy(dst, &val, len);
491 static const struct musb_platform_ops am35x_ops = {
493 const struct musb_platform_ops am35x_ops = {
495 .init = am35x_musb_init,
496 .exit = am35x_musb_exit,
498 .enable = am35x_musb_enable,
499 .disable = am35x_musb_disable,
502 .set_mode = am35x_musb_set_mode,
503 .try_idle = am35x_musb_try_idle,
505 .set_vbus = am35x_musb_set_vbus,
510 static u64 am35x_dmamask = DMA_BIT_MASK(32);
512 static int __devinit am35x_probe(struct platform_device *pdev)
514 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
515 struct platform_device *musb;
516 struct am35x_glue *glue;
523 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
525 dev_err(&pdev->dev, "failed to allocate glue context\n");
529 musb = platform_device_alloc("musb-hdrc", -1);
531 dev_err(&pdev->dev, "failed to allocate musb device\n");
535 phy_clk = clk_get(&pdev->dev, "fck");
536 if (IS_ERR(phy_clk)) {
537 dev_err(&pdev->dev, "failed to get PHY clock\n");
538 ret = PTR_ERR(phy_clk);
542 clk = clk_get(&pdev->dev, "ick");
544 dev_err(&pdev->dev, "failed to get clock\n");
549 ret = clk_enable(phy_clk);
551 dev_err(&pdev->dev, "failed to enable PHY clock\n");
555 ret = clk_enable(clk);
557 dev_err(&pdev->dev, "failed to enable clock\n");
561 musb->dev.parent = &pdev->dev;
562 musb->dev.dma_mask = &am35x_dmamask;
563 musb->dev.coherent_dma_mask = am35x_dmamask;
565 glue->dev = &pdev->dev;
567 glue->phy_clk = phy_clk;
570 pdata->platform_ops = &am35x_ops;
572 platform_set_drvdata(pdev, glue);
574 ret = platform_device_add_resources(musb, pdev->resource,
575 pdev->num_resources);
577 dev_err(&pdev->dev, "failed to add resources\n");
581 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
583 dev_err(&pdev->dev, "failed to add platform_data\n");
587 ret = platform_device_add(musb);
589 dev_err(&pdev->dev, "failed to register musb device\n");
599 clk_disable(phy_clk);
608 platform_device_put(musb);
617 static int __devexit am35x_remove(struct platform_device *pdev)
619 struct am35x_glue *glue = platform_get_drvdata(pdev);
621 platform_device_del(glue->musb);
622 platform_device_put(glue->musb);
623 clk_disable(glue->clk);
624 clk_disable(glue->phy_clk);
626 clk_put(glue->phy_clk);
633 static int am35x_suspend(struct device *dev)
635 struct am35x_glue *glue = dev_get_drvdata(dev);
636 struct musb_hdrc_platform_data *plat = dev->platform_data;
637 struct omap_musb_board_data *data = plat->board_data;
639 /* Shutdown the on-chip PHY and its PLL. */
640 if (data->set_phy_power)
641 data->set_phy_power(0);
643 clk_disable(glue->phy_clk);
644 clk_disable(glue->clk);
649 static int am35x_resume(struct device *dev)
651 struct am35x_glue *glue = dev_get_drvdata(dev);
652 struct musb_hdrc_platform_data *plat = dev->platform_data;
653 struct omap_musb_board_data *data = plat->board_data;
656 /* Start the on-chip PHY and its PLL. */
657 if (data->set_phy_power)
658 data->set_phy_power(1);
660 ret = clk_enable(glue->phy_clk);
662 dev_err(dev, "failed to enable PHY clock\n");
666 ret = clk_enable(glue->clk);
668 dev_err(dev, "failed to enable clock\n");
675 static struct dev_pm_ops am35x_pm_ops = {
676 .suspend = am35x_suspend,
677 .resume = am35x_resume,
680 #define DEV_PM_OPS &am35x_pm_ops
682 #define DEV_PM_OPS NULL
685 static struct platform_driver am35x_driver = {
686 .probe = am35x_probe,
687 .remove = __devexit_p(am35x_remove),
689 .name = "musb-am35x",
694 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
695 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
696 MODULE_LICENSE("GPL v2");
698 static int __init am35x_init(void)
700 return platform_driver_register(&am35x_driver);
702 module_init(am35x_init);
704 static void __exit am35x_exit(void)
706 platform_driver_unregister(&am35x_driver);
708 module_exit(am35x_exit);