2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
32 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
34 #ifdef CONFIG_NAND_U_BOOT
35 #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
36 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
37 #ifdef CONFIG_NAND_SPL
38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
39 #endif /* CONFIG_NAND_SPL */
40 #endif /* CONFIG_NAND_U_BOOT */
42 #ifndef CONFIG_SYS_TEXT_BASE
43 #define CONFIG_SYS_TEXT_BASE 0xFE000000
46 #ifndef CONFIG_SYS_MONITOR_BASE
47 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
51 * High Level Configuration Options
53 #define CONFIG_E300 1 /* E300 family */
54 #define CONFIG_MPC83xx 1 /* MPC83xx family */
55 #define CONFIG_MPC831x 1 /* MPC831x CPU family */
56 #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
57 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
62 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
63 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
66 * Hardware Reset Configuration Word
67 * if CLKIN is 66.66MHz, then
68 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
70 #define CONFIG_SYS_HRCW_LOW (\
71 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
72 HRCWL_DDR_TO_SCB_CLK_2X1 |\
74 HRCWL_CSB_TO_CLKIN_2X1 |\
75 HRCWL_CORE_TO_CSB_3X1)
76 #define CONFIG_SYS_HRCW_HIGH_BASE (\
78 HRCWH_PCI1_ARBITER_ENABLE |\
80 HRCWH_BOOTSEQ_DISABLE |\
81 HRCWH_SW_WATCHDOG_DISABLE |\
82 HRCWH_TSEC1M_IN_RGMII |\
83 HRCWH_TSEC2M_IN_RGMII |\
87 #ifdef CONFIG_NAND_SPL
88 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
89 HRCWH_FROM_0XFFF00100 |\
90 HRCWH_ROM_LOC_NAND_SP_8BIT |\
93 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
94 HRCWH_FROM_0X00000100 |\
95 HRCWH_ROM_LOC_LOCAL_16BIT |\
102 #define CONFIG_SYS_SICRH 0x00000000
103 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
105 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
106 #define CONFIG_HWCONFIG
111 #define CONFIG_SYS_IMMR 0xE0000000
113 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
114 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
120 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
121 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
122 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
127 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
129 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
130 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
131 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
138 * Manually set up DDR parameters
139 * consist of two chips HY5PS12621BFP-C4 from HYNIX
141 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
142 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
143 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
144 | 0x00010000 /* ODT_WR to CSn */ \
145 | CSCONFIG_ROW_BIT_13 \
146 | CSCONFIG_COL_BIT_10)
148 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
149 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
150 | (0 << TIMING_CFG0_WRT_SHIFT) \
151 | (0 << TIMING_CFG0_RRT_SHIFT) \
152 | (0 << TIMING_CFG0_WWT_SHIFT) \
153 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
154 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
155 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
156 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
158 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
159 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
160 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
161 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
162 | (6 << TIMING_CFG1_REFREC_SHIFT) \
163 | (2 << TIMING_CFG1_WRREC_SHIFT) \
164 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
165 | (2 << TIMING_CFG1_WRTORD_SHIFT))
167 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
168 | (4 << TIMING_CFG2_CPO_SHIFT) \
169 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
170 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
171 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
172 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
173 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
175 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
176 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
178 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
179 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
182 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
183 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
184 | (0x0232 << SDRAM_MODE_SD_SHIFT))
185 /* ODT 150ohm CL=3, AL=1 on SDRAM */
186 #define CONFIG_SYS_DDR_MODE2 0x00000000
191 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
192 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
193 #define CONFIG_SYS_MEMTEST_END 0x00140000
196 * The reserved memory
198 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
199 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
202 * Initial RAM Base Address Setup
204 #define CONFIG_SYS_INIT_RAM_LOCK 1
205 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
206 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
207 #define CONFIG_SYS_GBL_DATA_OFFSET \
208 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
211 * Local Bus Configuration & Clock Setup
213 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
214 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
215 #define CONFIG_SYS_LBC_LBCR 0x00040000
216 #define CONFIG_FSL_ELBC 1
219 * FLASH on the Local Bus
221 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
222 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
223 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
225 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
226 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
227 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
229 /* Window base at flash base */
230 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
231 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
233 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
234 | (2 << BR_PS_SHIFT) /* 16 bit port */ \
236 #define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
246 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
247 /* 127 64KB sectors and 8 8KB top sectors per device */
248 #define CONFIG_SYS_MAX_FLASH_SECT 135
250 #undef CONFIG_SYS_FLASH_CHECKSUM
251 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
252 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
255 * NAND Flash on the Local Bus
258 #ifdef CONFIG_NAND_SPL
259 #define CONFIG_SYS_NAND_BASE 0xFFF00000
261 #define CONFIG_SYS_NAND_BASE 0xE0600000
264 #define CONFIG_MTD_DEVICE
265 #define CONFIG_MTD_PARTITION
266 #define CONFIG_CMD_MTDPARTS
267 #define MTDIDS_DEFAULT "nand0=e0600000.flash"
268 #define MTDPARTS_DEFAULT \
269 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
271 #define CONFIG_SYS_MAX_NAND_DEVICE 1
272 #define CONFIG_MTD_NAND_VERIFY_WRITE 1
273 #define CONFIG_CMD_NAND 1
274 #define CONFIG_NAND_FSL_ELBC 1
275 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
277 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
278 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
279 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
280 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
281 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
283 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
284 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
285 | BR_PS_8 /* 8 bit port */ \
286 | BR_MS_FCM /* MSEL = FCM */ \
288 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
297 #ifdef CONFIG_NAND_U_BOOT
298 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
299 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
300 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
301 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
303 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
304 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
305 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
306 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
309 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
310 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
312 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
313 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
315 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
316 !defined(CONFIG_NAND_SPL)
317 #define CONFIG_SYS_RAMBOOT
319 #undef CONFIG_SYS_RAMBOOT
325 #define CONFIG_CONS_INDEX 1
326 #define CONFIG_SYS_NS16550
327 #define CONFIG_SYS_NS16550_SERIAL
328 #define CONFIG_SYS_NS16550_REG_SIZE 1
329 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
331 #define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
334 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
335 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
337 /* Use the HUSH parser */
338 #define CONFIG_SYS_HUSH_PARSER
339 #ifdef CONFIG_SYS_HUSH_PARSER
340 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
343 /* Pass open firmware flat tree */
344 #define CONFIG_OF_LIBFDT 1
345 #define CONFIG_OF_BOARD_SETUP 1
346 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
349 #define CONFIG_HARD_I2C /* I2C with hardware support */
350 #define CONFIG_FSL_I2C
351 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave addr */
352 #define CONFIG_SYS_I2C_SLAVE 0x7F
353 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
354 #define CONFIG_SYS_I2C_OFFSET 0x3000
355 #define CONFIG_SYS_I2C2_OFFSET 0x3100
358 * Board info - revision and where boot from
360 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
363 * Config on-board RTC
365 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
366 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
370 * Addresses are mapped 1-1.
372 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
373 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
374 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
375 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
376 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
377 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
378 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
379 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
380 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
382 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
383 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
384 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
386 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
387 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
388 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
389 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
390 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
391 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
392 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
393 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
394 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
396 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
397 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
398 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
399 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
400 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
401 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
402 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
403 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
404 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
409 #define CONFIG_PCI_PNP /* do pci plug-and-play */
411 #define CONFIG_EEPRO100
412 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
413 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
415 #define CONFIG_HAS_FSL_DR_USB
416 #define CONFIG_SYS_SCCR_USBDRCM 3
418 #define CONFIG_CMD_USB
419 #define CONFIG_USB_STORAGE
420 #define CONFIG_USB_EHCI
421 #define CONFIG_USB_EHCI_FSL
422 #define CONFIG_USB_PHY_TYPE "utmi"
423 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
428 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
429 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
430 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
431 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
432 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
435 * TSEC ethernet configuration
437 #define CONFIG_MII 1 /* MII PHY management */
438 #define CONFIG_TSEC1 1
439 #define CONFIG_TSEC1_NAME "eTSEC0"
440 #define CONFIG_TSEC2 1
441 #define CONFIG_TSEC2_NAME "eTSEC1"
442 #define TSEC1_PHY_ADDR 0
443 #define TSEC2_PHY_ADDR 1
444 #define TSEC1_PHYIDX 0
445 #define TSEC2_PHYIDX 0
446 #define TSEC1_FLAGS TSEC_GIGABIT
447 #define TSEC2_FLAGS TSEC_GIGABIT
449 /* Options are: eTSEC[0-1] */
450 #define CONFIG_ETHPRIME "eTSEC1"
455 #define CONFIG_LIBATA
456 #define CONFIG_FSL_SATA
458 #define CONFIG_SYS_SATA_MAX_DEVICE 2
460 #define CONFIG_SYS_SATA1_OFFSET 0x18000
461 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
462 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
464 #define CONFIG_SYS_SATA2_OFFSET 0x19000
465 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
466 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
468 #ifdef CONFIG_FSL_SATA
470 #define CONFIG_CMD_SATA
471 #define CONFIG_DOS_PARTITION
472 #define CONFIG_CMD_EXT2
478 #if defined(CONFIG_NAND_U_BOOT)
479 #define CONFIG_ENV_IS_IN_NAND 1
480 #define CONFIG_ENV_OFFSET (512 * 1024)
481 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
482 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
483 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
484 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
485 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
487 #elif !defined(CONFIG_SYS_RAMBOOT)
488 #define CONFIG_ENV_IS_IN_FLASH 1
489 #define CONFIG_ENV_ADDR \
490 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
491 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
492 #define CONFIG_ENV_SIZE 0x2000
494 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
495 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
496 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
497 #define CONFIG_ENV_SIZE 0x2000
500 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
501 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
506 #define CONFIG_BOOTP_BOOTFILESIZE
507 #define CONFIG_BOOTP_BOOTPATH
508 #define CONFIG_BOOTP_GATEWAY
509 #define CONFIG_BOOTP_HOSTNAME
512 * Command line configuration.
514 #include <config_cmd_default.h>
516 #define CONFIG_CMD_PING
517 #define CONFIG_CMD_I2C
518 #define CONFIG_CMD_MII
519 #define CONFIG_CMD_DATE
520 #define CONFIG_CMD_PCI
522 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
523 #undef CONFIG_CMD_SAVEENV
524 #undef CONFIG_CMD_LOADS
527 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
528 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
530 #undef CONFIG_WATCHDOG /* watchdog disabled */
533 * Miscellaneous configurable options
535 #define CONFIG_SYS_LONGHELP /* undef to save memory */
536 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
537 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
539 #if defined(CONFIG_CMD_KGDB)
540 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
542 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
545 /* Print Buffer Size */
546 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
547 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
548 /* Boot Argument Buffer Size */
549 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
550 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
553 * For booting Linux, the board info and command line data
554 * have to be in the first 256 MB of memory, since this is
555 * the maximum mapped by the Linux kernel during initialization.
557 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
562 #define CONFIG_SYS_HID0_INIT 0x000000000
563 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
564 HID0_ENABLE_INSTRUCTION_CACHE | \
565 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
566 #define CONFIG_SYS_HID2 HID2_HBE
571 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
573 /* DDR: cache cacheable */
574 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
577 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
581 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
582 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
584 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
585 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
587 | BATL_CACHEINHIBIT \
588 | BATL_GUARDEDSTORAGE)
589 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
593 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
594 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
596 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
597 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
600 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
604 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
606 | BATL_CACHEINHIBIT \
607 | BATL_GUARDEDSTORAGE)
608 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
610 /* Stack in dcache: cacheable, no memory coherence */
611 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
612 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
616 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
617 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
619 /* PCI MEM space: cacheable */
620 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
623 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
627 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
628 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
630 /* PCI MMIO space: cache-inhibit and guarded */
631 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
633 | BATL_CACHEINHIBIT \
634 | BATL_GUARDEDSTORAGE)
635 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
639 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
640 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
642 #define CONFIG_SYS_IBAT6L 0
643 #define CONFIG_SYS_IBAT6U 0
644 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
645 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
647 #define CONFIG_SYS_IBAT7L 0
648 #define CONFIG_SYS_IBAT7U 0
649 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
650 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
652 #if defined(CONFIG_CMD_KGDB)
653 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
654 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
658 * Environment Configuration
661 #define CONFIG_ENV_OVERWRITE
663 #if defined(CONFIG_TSEC_ENET)
664 #define CONFIG_HAS_ETH0
665 #define CONFIG_HAS_ETH1
668 #define CONFIG_BAUDRATE 115200
670 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
672 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
673 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
675 #define CONFIG_EXTRA_ENV_SETTINGS \
677 "consoledev=ttyS0\0" \
678 "ramdiskaddr=1000000\0" \
679 "ramdiskfile=ramfs.83xx\0" \
681 "fdtfile=mpc8315erdb.dtb\0" \
682 "usb_phy_type=utmi\0" \
685 #define CONFIG_NFSBOOTCOMMAND \
686 "setenv bootargs root=/dev/nfs rw " \
687 "nfsroot=$serverip:$rootpath " \
688 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
690 "console=$consoledev,$baudrate $othbootargs;" \
691 "tftp $loadaddr $bootfile;" \
692 "tftp $fdtaddr $fdtfile;" \
693 "bootm $loadaddr - $fdtaddr"
695 #define CONFIG_RAMBOOTCOMMAND \
696 "setenv bootargs root=/dev/ram rw " \
697 "console=$consoledev,$baudrate $othbootargs;" \
698 "tftp $ramdiskaddr $ramdiskfile;" \
699 "tftp $loadaddr $bootfile;" \
700 "tftp $fdtaddr $fdtfile;" \
701 "bootm $loadaddr $ramdiskaddr $fdtaddr"
704 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
706 #endif /* __CONFIG_H */