2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
35 #define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $"
37 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
38 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
39 #define CONFIG_PCI405 1 /* ...on a PCI405 board */
41 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
42 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
44 #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
46 #define CONFIG_BOARD_TYPES 1 /* support board types */
48 #define CONFIG_BAUDRATE 115200
49 #define CONFIG_BOOTDELAY 0 /* autoboot after 0 seconds */
51 #undef CONFIG_BOOTARGS
52 #define CONFIG_EXTRA_ENV_SETTINGS \
53 "mem_linux=14336k\0" \
55 "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
56 "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
58 #define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci"
60 #define CONFIG_PREBOOT /* enable preboot variable */
62 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
63 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
65 #define CONFIG_MII 1 /* MII PHY management */
66 #define CONFIG_PHY_ADDR 0 /* PHY address */
68 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
70 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
79 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
80 #include <cmd_confdefs.h>
82 #undef CONFIG_WATCHDOG /* watchdog disabled */
84 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
86 #define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
89 * Miscellaneous configurable options
91 #define CFG_LONGHELP /* undef to save memory */
92 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
94 #define CFG_HUSH_PARSER /* use "hush" command parser */
95 #ifdef CFG_HUSH_PARSER
96 #define CFG_PROMPT_HUSH_PS2 "> "
99 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
100 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
102 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105 #define CFG_MAXARGS 16 /* max number of command args */
106 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
108 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
110 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
112 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
113 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
115 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
116 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
117 #define CFG_BASE_BAUD 691200
119 /* The following table includes the supported baudrates */
120 #define CFG_BAUDRATE_TABLE \
121 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
122 57600, 115200, 230400, 460800, 921600 }
124 #define CFG_LOAD_ADDR 0x100000 /* default load address */
125 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
127 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
129 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
131 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
133 /*-----------------------------------------------------------------------
135 *-----------------------------------------------------------------------
137 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
138 #define PCI_HOST_FORCE 1 /* configure as pci host */
139 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
141 #define CONFIG_PCI /* include pci support */
142 #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */
143 #undef CONFIG_PCI_PNP /* no pci plug-and-play */
144 /* resource configuration */
146 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
148 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
149 #define CFG_PCI_SUBSYS_DEVICEID 0x0407 /* PCI Device ID: PCI-405 */
150 #define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
151 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
152 #define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
153 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
155 #if 0 /* test-only */
156 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
157 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
158 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
160 #define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs */
161 #define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
162 #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
165 /*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
168 * Please note that CFG_SDRAM_BASE _must_ start at 0
170 #define CFG_SDRAM_BASE 0x00000000
171 #define CFG_FLASH_BASE 0xFFFD0000
172 #define CFG_MONITOR_BASE CFG_FLASH_BASE
173 #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
174 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
177 * For booting Linux, the board info and command line data
178 * have to be in the first 8 MB of memory, since this is
179 * the maximum mapped by the Linux kernel during initialization.
181 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
182 /*-----------------------------------------------------------------------
185 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
186 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
188 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
189 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
191 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
192 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
193 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
195 * The following defines are added for buggy IOP480 byte interface.
196 * All other boards should use the standard values (CPCI405 etc.)
198 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
199 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
200 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
202 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
204 #if 0 /* Use NVRAM for environment variables */
205 /*-----------------------------------------------------------------------
208 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
209 #define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
210 #define CFG_ENV_ADDR \
211 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
213 #else /* Use EEPROM for environment variables */
215 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
216 #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
217 #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
218 /* total size of a CAT24WC08 is 1024 bytes */
221 #define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
222 #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
224 /*-----------------------------------------------------------------------
225 * I2C EEPROM (CAT24WC16) for environment
227 #define CONFIG_HARD_I2C /* I2c with hardware support */
228 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
229 #define CFG_I2C_SLAVE 0x7F
231 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
232 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
233 /* mask of address bits that overflow into the "EEPROM chip address" */
234 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
235 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
236 /* 16 byte page write mode using*/
237 /* last 4 bits of the address */
238 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
239 #define CFG_EEPROM_PAGE_WRITE_ENABLE
241 /*-----------------------------------------------------------------------
242 * Cache Configuration
244 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
245 #define CFG_CACHELINE_SIZE 32 /* ... */
246 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
247 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
251 * Init Memory Controller:
253 * BR0/1 and OR0/1 (FLASH)
256 #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
258 /*-----------------------------------------------------------------------
259 * External Bus Controller (EBC) Setup
262 /* Memory Bank 0 (Flash Bank 0) initialization */
263 #define CFG_EBC_PB0AP 0x92015480
264 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
266 /* Memory Bank 1 (NVRAM/RTC) initialization */
267 #define CFG_EBC_PB1AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
268 #define CFG_EBC_PB1CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
270 /* Memory Bank 2 (CAN0, 1) initialization */
271 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
272 /*#define CFG_EBC_PB2AP 0x038056C0 / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
273 #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
275 /* Memory Bank 3 (FPGA internal) initialization */
276 #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
277 #define CFG_EBC_PB3CR 0xF041C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
278 #define CFG_FPGA_BASE_ADDR 0xF0400000
280 /*-----------------------------------------------------------------------
283 /* FPGA internal regs */
284 #define CFG_FPGA_MODE 0x00
285 #define CFG_FPGA_STATUS 0x02
286 #define CFG_FPGA_TS 0x04
287 #define CFG_FPGA_TS_LOW 0x06
288 #define CFG_FPGA_TS_CAP0 0x10
289 #define CFG_FPGA_TS_CAP0_LOW 0x12
290 #define CFG_FPGA_TS_CAP1 0x14
291 #define CFG_FPGA_TS_CAP1_LOW 0x16
292 #define CFG_FPGA_TS_CAP2 0x18
293 #define CFG_FPGA_TS_CAP2_LOW 0x1a
294 #define CFG_FPGA_TS_CAP3 0x1c
295 #define CFG_FPGA_TS_CAP3_LOW 0x1e
298 #define CFG_FPGA_MODE_CF_RESET 0x0001
299 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
300 #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
301 #define CFG_FPGA_MODE_TS_CLEAR 0x2000
303 /* FPGA Status Reg */
304 #define CFG_FPGA_STATUS_DIP0 0x0001
305 #define CFG_FPGA_STATUS_DIP1 0x0002
306 #define CFG_FPGA_STATUS_DIP2 0x0004
307 #define CFG_FPGA_STATUS_FLASH 0x0008
308 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
310 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
311 #define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
313 /* FPGA program pin configuration */
314 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
315 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
316 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
317 #define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
318 #define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
319 /* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support) */
320 #define CFG_FPGA_INIT_V12 0x00008000 /* FPGA init pin (ppc input) */
321 #define CFG_FPGA_DONE_V12 0x00010000 /* FPGA done pin (ppc input) */
323 /*-----------------------------------------------------------------------
324 * Definitions for initial stack pointer and data area (in data cache)
326 #if 0 /* test-only */
327 #define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
328 #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
329 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
330 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
331 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
332 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
334 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
335 #define CFG_TEMP_STACK_OCM 1
336 /* On Chip Memory location */
337 #define CFG_OCM_DATA_ADDR 0xF8000000
338 #define CFG_OCM_DATA_SIZE 0x1000
339 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
340 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
342 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
343 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
344 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
348 * Internal Definitions
352 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
353 #define BOOTFLAG_WARM 0x02 /* Software reboot */
355 #endif /* __CONFIG_H */