dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / exynos / clock.c

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index c0c95fbc83dc805953717b48d8701b15c52f7211..b31c13b14bfbd1c4d663e4f518bdd486e4736c72 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
                        div = PLL_DIV_1024;
                else if (proid_is_exynos4412())
                        div = PLL_DIV_65535;
-               else if (proid_is_exynos5250() || proid_is_exynos5420())
+               else if (proid_is_exynos5250() || proid_is_exynos5420()
+                        || proid_is_exynos5800())
                        div = PLL_DIV_65536;
                else
                        return 0;
@@ -847,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index)
 
        if (sel == 0x3)
                sclk = get_pll_clk(MPLL);
+       else if (sel == 0x4)
+               sclk = get_pll_clk(SPLL);
        else if (sel == 0x6)
                sclk = get_pll_clk(EPLL);
        else
@@ -1581,7 +1584,7 @@ static unsigned long exynos4_get_i2c_clk(void)
 unsigned long get_pll_clk(int pllreg)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_pll_clk(pllreg);
                return exynos5_get_pll_clk(pllreg);
        } else {
@@ -1617,7 +1620,7 @@ unsigned long get_i2c_clk(void)
 unsigned long get_pwm_clk(void)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_pwm_clk();
                return clock_get_periph_rate(PERIPH_ID_PWM0);
        } else {
@@ -1630,7 +1633,7 @@ unsigned long get_pwm_clk(void)
 unsigned long get_uart_clk(int dev_index)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_uart_clk(dev_index);
                return exynos5_get_uart_clk(dev_index);
        } else {
@@ -1643,7 +1646,7 @@ unsigned long get_uart_clk(int dev_index)
 unsigned long get_mmc_clk(int dev_index)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_mmc_clk(dev_index);
                return exynos5_get_mmc_clk(dev_index);
        } else {
@@ -1654,7 +1657,7 @@ unsigned long get_mmc_clk(int dev_index)
 void set_mmc_clk(int dev_index, unsigned int div)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        exynos5420_set_mmc_clk(dev_index, div);
                else
                        exynos5_set_mmc_clk(dev_index, div);
@@ -1668,7 +1671,7 @@ unsigned long get_lcd_clk(void)
        if (cpu_is_exynos4())
                return exynos4_get_lcd_clk();
        else {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_get_lcd_clk();
                else
                        return exynos5_get_lcd_clk();
@@ -1682,7 +1685,7 @@ void set_lcd_clk(void)
        else {
                if (proid_is_exynos5250())
                        exynos5_set_lcd_clk();
-               else if (proid_is_exynos5420())
+               else if (proid_is_exynos5420() || proid_is_exynos5800())
                        exynos5420_set_lcd_clk();
        }
 }
@@ -1696,7 +1699,7 @@ void set_mipi_clk(void)
 int set_spi_clk(int periph_id, unsigned int rate)
 {
        if (cpu_is_exynos5()) {
-               if (proid_is_exynos5420())
+               if (proid_is_exynos5420() || proid_is_exynos5800())
                        return exynos5420_set_spi_clk(periph_id, rate);
                return exynos5_set_spi_clk(periph_id, rate);
        } else {