ARM: AM33xx: Cleanup dplls data

[karo-tx-uboot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 260cc3484f09330fdcb19707a1db89c1f3058c8d..683ba8ea99ef3776fcc89a86c9923c06b085c1a5 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -5,15 +5,7 @@
  *
  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _DDR_DEFS_H
@@ -84,20 +76,20 @@
 #define MT41J256M8HX15E_IOCTRL_VALUE           0x18B
 
 /* Micron MT41K256M16HA-125E */
-#define MT41K256M16HA125E_EMIF_READ_LATENCY    0x100006
-#define MT41K256M16HA125E_EMIF_TIM1            0x0888A39B
-#define MT41K256M16HA125E_EMIF_TIM2            0x26517FDA
-#define MT41K256M16HA125E_EMIF_TIM3            0x501F84EF
-#define MT41K256M16HA125E_EMIF_SDCFG           0x61C04BB2
-#define MT41K256M16HA125E_EMIF_SDREF           0x0000093B
+#define MT41K256M16HA125E_EMIF_READ_LATENCY    0x100007
+#define MT41K256M16HA125E_EMIF_TIM1            0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2            0x266B7FDA
+#define MT41K256M16HA125E_EMIF_TIM3            0x501F867F
+#define MT41K256M16HA125E_EMIF_SDCFG           0x61C05332
+#define MT41K256M16HA125E_EMIF_SDREF           0xC30
 #define MT41K256M16HA125E_ZQ_CFG               0x50074BE4
 #define MT41K256M16HA125E_DLL_LOCK_DIFF                0x1
-#define MT41K256M16HA125E_RATIO                        0x40
+#define MT41K256M16HA125E_RATIO                        0x80
 #define MT41K256M16HA125E_INVERT_CLKOUT                0x0
-#define MT41K256M16HA125E_RD_DQS               0x3C
-#define MT41K256M16HA125E_WR_DQS               0x45
-#define MT41K256M16HA125E_PHY_WR_DATA          0x7F
-#define MT41K256M16HA125E_PHY_FIFO_WE          0x9B
+#define MT41K256M16HA125E_RD_DQS               0x38
+#define MT41K256M16HA125E_WR_DQS               0x44
+#define MT41K256M16HA125E_PHY_WR_DATA          0x7D
+#define MT41K256M16HA125E_PHY_FIFO_WE          0x94
 #define MT41K256M16HA125E_IOCTRL_VALUE         0x18B
 
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
@@ -117,6 +109,23 @@
 #define MT41J512M8RH125_PHY_WR_DATA            0x74
 #define MT41J512M8RH125_IOCTRL_VALUE           0x18B
 
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x06
+#define K4B2G1646EBIH9_EMIF_TIM1               0x0888A39B
+#define K4B2G1646EBIH9_EMIF_TIM2               0x2A04011A
+#define K4B2G1646EBIH9_EMIF_TIM3               0x501F820F
+#define K4B2G1646EBIH9_EMIF_SDCFG              0x61C24AB2
+#define K4B2G1646EBIH9_EMIF_SDREF              0x0000093B
+#define K4B2G1646EBIH9_ZQ_CFG                  0x50074BE4
+#define K4B2G1646EBIH9_DLL_LOCK_DIFF           0x1
+#define K4B2G1646EBIH9_RATIO                   0x40
+#define K4B2G1646EBIH9_INVERT_CLKOUT           0x1
+#define K4B2G1646EBIH9_RD_DQS                  0x3B
+#define K4B2G1646EBIH9_WR_DQS                  0x85
+#define K4B2G1646EBIH9_PHY_FIFO_WE             0x100
+#define K4B2G1646EBIH9_PHY_WR_DATA             0xC1
+#define K4B2G1646EBIH9_IOCTRL_VALUE            0x18B
+
 /**
  * Configure DMM
  */
@@ -137,6 +146,8 @@ void set_sdram_timings(const struct emif_regs *regs, int nr);
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr);
 
+void ddr_pll_config(unsigned int ddrpll_m);
+
 struct ddr_cmd_regs {
        unsigned int resv0[7];
        unsigned int cm0csratio;        /* offset 0x01C */
@@ -267,7 +278,6 @@ void config_ddr_data(const struct ddr_data *data, int nr);
  * This structure represents the DDR io control on AM33XX devices.
  */
 struct ddr_cmdtctrl {
-       unsigned int resv1[1];
        unsigned int cm0ioctl;
        unsigned int cm1ioctl;
        unsigned int cm2ioctl;