arm: mvebu: Enable NAND controller on MVEBU SoC's

[karo-tx-uboot.git] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 9496d5fc5b9b153257e54d0ef0bb56b47f74b787..38e15aa7b67b07a9b6e97e9b20deffa88a557c7c 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -19,18 +19,20 @@
 
 static struct mbus_win windows[] = {
        /* PCIE MEM address space */
-       { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
+       { MBUS_PCI_MEM_BASE, MBUS_PCI_MEM_SIZE,
+         CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
 
        /* PCIE IO address space */
-       { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
+       { MBUS_PCI_IO_BASE, MBUS_PCI_IO_SIZE,
+         CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
 
        /* SPI */
-       { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
-         CPU_ATTR_SPIFLASH },
+       { MBUS_SPI_BASE, MBUS_SPI_SIZE,
+         CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
 
        /* NOR */
-       { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
-         CPU_ATTR_BOOTROM },
+       { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
+         CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
 };
 
 void reset_cpu(unsigned long ignored)
@@ -181,13 +183,25 @@ static void set_cbar(u32 addr)
 int arch_cpu_init(void)
 {
 #ifndef CONFIG_SPL_BUILD
-       /*
-        * Only with disabled MMU its possible to switch the base
-        * register address on Armada 38x. Without this the SDRAM
-        * located at >= 0x4000.0000 is also not accessible, as its
-        * still locked to cache.
-        */
-       mmu_disable();
+       if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+               struct pl310_regs *const pl310 =
+                       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+               /*
+                * Only with disabled MMU its possible to switch the base
+                * register address on Armada 38x. Without this the SDRAM
+                * located at >= 0x4000.0000 is also not accessible, as its
+                * still locked to cache.
+                *
+                * So to fully release / unlock this area from cache, we need
+                * to first flush all caches, then disable the MMU and
+                * disable the L2 cache.
+                */
+               icache_disable();
+               dcache_disable();
+               mmu_disable();
+               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+       }
 #endif
 
        /* Linux expects the internal registers to be at 0xf1000000 */
@@ -227,10 +241,30 @@ int arch_cpu_init(void)
         */
        mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
 
+       if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+               /* Enable GBE0, GBE1, LCD and NFC PUP */
+               clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
+                               GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
+                               NAND_PUP_EN | SPI_PUP_EN);
+       }
+
+       /* Enable NAND and NAND arbiter */
+       clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
+
+       /* Disable MBUS error propagation */
+       clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
+
        return 0;
 }
 #endif /* CONFIG_ARCH_CPU_INIT */
 
+u32 mvebu_get_nand_clock(void)
+{
+       return CONFIG_SYS_MVEBU_PLL_CLOCK /
+               ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
+                 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
+}
+
 /*
  * SOC specific misc init
  */