spl, common, serial: build SPL without serial support

[karo-tx-uboot.git] / arch / arm / mach-tegra / cpu.c

diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index f7d45e8f6536921a657c2b124622e27557513605..ba04a56be765df9dfa98223796978fa55e386b72 100644 (file)
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -67,6 +67,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
                { .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
                { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
                { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+               { .n =    0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 38.4 MHz (N/A) */
+               { .n =    0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 48.0 MHz (N/A) */
        },
        /*
         * T25: 1.2 GHz
@@ -83,6 +85,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
                { .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
                { .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
                { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+               { .n =   0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 38.4 MHz (N/A) */
+               { .n =   0, .m =  0, .p = 0, .cpcon =  0 }, /* OSC: 48.0 MHz (N/A) */
        },
        /*
         * T30: 600 MHz
@@ -99,6 +103,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
                { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
                { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
                { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+               { .n =   0, .m =  0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
+               { .n =   0, .m =  0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
        },
        /*
         * T114: 700 MHz
@@ -114,6 +120,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
                { .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
                { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
                { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+               { .n =   0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
+               { .n =   0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
        },
 
        /*
@@ -130,6 +138,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
                { .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
                { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
                { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+               { .n =   0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
+               { .n =   0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
        },
 
        /*
@@ -146,6 +156,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
                { .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
                { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696   MHz*/
                { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702   MHz*/
+               { .n =  36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
+               { .n =  58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696   MHz */
        },
 };
 
@@ -169,6 +181,7 @@ static inline void pllx_set_iddq(void)
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
                u32 divp, u32 cpcon)
 {
+       struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
        int chip = tegra_get_chip();
        u32 reg;
        debug("%s entry\n", __func__);
@@ -182,17 +195,21 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
        pllx_set_iddq();
 
        /* Set BYPASS, m, n and p to PLLX_BASE */
-       reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
-       reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
+       reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
+       reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
        writel(reg, &pll->pll_base);
 
        /* Set cpcon to PLLX_MISC */
        if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
-               reg = (cpcon << PLL_CPCON_SHIFT);
+               reg = (cpcon << pllinfo->kcp_shift);
        else
                reg = 0;
 
-       /* Set dccon to PLLX_MISC if freq > 600MHz */
+       /*
+        * TODO(twarren@nvidia.com) Check which SoCs use DCCON
+        * and add to pllinfo table if needed!
+        */
+        /* Set dccon to PLLX_MISC if freq > 600MHz */
        if (divn > 600)
                reg |= (1 << PLL_DCCON_SHIFT);
        writel(reg, &pll->pll_misc);
@@ -203,9 +220,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
        writel(reg, &pll->pll_base);
        debug("%s: base = 0x%08X\n", __func__, reg);
 
-       /* Set lock_enable to PLLX_MISC */
+       /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
        reg = readl(&pll->pll_misc);
-       reg |= PLL_LOCK_ENABLE_MASK;
+       if (pllinfo->lock_ena < 32)
+               reg |= (1 << pllinfo->lock_ena);
        writel(reg, &pll->pll_misc);
        debug("%s: misc = 0x%08X\n", __func__, reg);