powerpc/mpc85xx: Add definitions for HDBCR registers

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / start.S

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index bb0dc1a653e193fb1f141e13ede0980f0c075198..2ce5505e00e0cc823afe4723b162832406ad7b5c 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -70,7 +70,7 @@
 #endif
 
        GOT_ENTRY(__init_end)
-       GOT_ENTRY(__bss_end__)
+       GOT_ENTRY(__bss_end)
        GOT_ENTRY(__bss_start)
        END_GOT
 
@@ -116,10 +116,10 @@ _start_e500:
        /* Erratum says set bits 55:60 to 001001 */
        msync
        isync
-       mfspr   r3,976
+       mfspr   r3,SPRN_HDBCR0
        li      r4,0x48
        rlwimi  r3,r4,0,0x1f8
-       mtspr   976,r3
+       mtspr   SPRN_HDBCR0,r3
        isync
 2:
 #endif
@@ -372,9 +372,9 @@ l2_disabled:
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
-       mfspr   r3,977
+       mfspr   r3,SPRN_HDBCR1
        oris    r3,r3,0x0100
-       mtspr   977,r3
+       mtspr   SPRN_HDBCR1,r3
 #endif
 
        /* Enable Branch Prediction */
@@ -449,7 +449,7 @@ nexti:      mflr    r1              /* R1 = our PC */
 
        /* Set the size of the TLB to 4KB */
        mfspr   r3, MAS1
-       li      r2, 0xF00
+       li      r2, 0xF80
        andc    r3, r3, r2      /* Clear the TSIZE bits */
        ori     r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
        oris    r3, r3, MAS1_IPROT@h
@@ -1784,7 +1784,7 @@ clear_bss:
         * Now clear BSS segment
         */
        lwz     r3,GOT(__bss_start)
-       lwz     r4,GOT(__bss_end__)
+       lwz     r4,GOT(__bss_end)
 
        cmplw   0,r3,r4
        beq     6f