#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
-#include <asm/pcie_layerscape.h>
+#include <hwconfig.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
+#include <fsl_immap.h>
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
#include <spl.h>
+#include "../common/sleep.h"
#ifdef CONFIG_U_QE
#include "../../../drivers/qe/qe.h"
#endif
#define KEEP_STATUS 0x0
#define NEED_RESET 0x1
+#define SOFT_MUX_ON_I2C3_IFC 0x2
+#define SOFT_MUX_ON_CAN3_USB2 0x8
+#define SOFT_MUX_ON_QE_LCD 0x10
+
+#define PIN_I2C3_IFC_MUX_I2C3 0x0
+#define PIN_I2C3_IFC_MUX_IFC 0x1
+#define PIN_CAN3_USB2_MUX_USB2 0x0
+#define PIN_CAN3_USB2_MUX_CAN3 0x1
+#define PIN_QE_LCD_MUX_LCD 0x0
+#define PIN_QE_LCD_MUX_QE 0x1
+
struct cpld_data {
u8 cpld_ver; /* cpld revision */
u8 cpld_ver_sub; /* cpld sub revision */
return 0;
}
+unsigned int get_soc_major_rev(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
+
+ svr = in_be32(&gur->svr);
+ major = SVR_MAJ(svr);
+
+ return major;
+}
+
void ddrmc_init(void)
{
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ u32 temp_sdram_cfg;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
- out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ out_be32(&ddr->sdram_cfg_2,
+ DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
+ out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_ext_addr, (1 << 31));
+
+ /* DRAM VRef will not be trained */
+ out_be32(&ddr->ddr_cdr2,
+ DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
+ } else
+#endif
+ {
+ out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+ out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+ }
out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
- out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
udelay(1);
- out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* enter self-refresh */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+ out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+
+ temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+ } else
+#endif
+ temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* exit self-refresh */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+ out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ }
+#endif
}
int dram_init(void)
#endif
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return 0;
}
}
#endif
+#ifndef CONFIG_QSPI_BOOT
+int config_board_mux(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ int conflict_flag;
+
+ conflict_flag = 0;
+ if (hwconfig("i2c3")) {
+ conflict_flag++;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
+ cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
+ }
+
+ if (hwconfig("ifc")) {
+ conflict_flag++;
+ /* some signals can not enable simultaneous*/
+ if (conflict_flag > 1)
+ goto conflict;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
+ cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
+ }
+
+ conflict_flag = 0;
+ if (hwconfig("usb2")) {
+ conflict_flag++;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
+ cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
+ }
+
+ if (hwconfig("can3")) {
+ conflict_flag++;
+ /* some signals can not enable simultaneous*/
+ if (conflict_flag > 1)
+ goto conflict;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
+ cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
+ }
+
+ conflict_flag = 0;
+ if (hwconfig("lcd")) {
+ conflict_flag++;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
+ cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
+ }
+
+ if (hwconfig("qe")) {
+ conflict_flag++;
+ /* some signals can not enable simultaneous*/
+ if (conflict_flag > 1)
+ goto conflict;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
+ cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
+ }
+
+ return 0;
+
+conflict:
+ printf("WARNING: pin conflict! MUX setting may failed!\n");
+ return 0;
+}
+#endif
+
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ unsigned int major;
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /* Configure Little endian for SAI, ASRC and SPDIF */
+ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
+
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A7 core cluster)
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
- /*
- * Set CCI-400 Slave interface S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ major = get_soc_major_rev();
+ if (major == SOC_MAJOR_VER_1_0) {
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override
+ * Register All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ }
+
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
return 0;
}
get_clocks();
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
preloader_console_init();
dram_init();
};
#endif
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
+ SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
+};
+
struct smmu_stream_id dev_stream_id[] = {
{ 0x100, 0x01, "ETSEC MAC1" },
{ 0x104, 0x02, "ETSEC MAC2" },
#endif
#endif
+ ls1021x_config_caam_stream_id(sec_liodn_tbl,
+ ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
+#ifndef CONFIG_QSPI_BOOT
+ config_board_mux();
+#endif
+
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
}
#endif
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCIE_LAYERSCAPE
- ft_pcie_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
#endif
return 0;
projects / karo-tx-uboot.git / blobdiff