Merge branch 'master' of git://git.denx.de/u-boot-video

[karo-tx-uboot.git] / board / motionpro / motionpro.c

diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index f83998e5aa05c9970ff1cf844e38d483c3b72e29..47ef6e53eda2b5ae3958073f0135fe8265bfa6b9 100644 (file)
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -5,7 +5,7 @@
  * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
  * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
  * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
- * Also changed the refresh for 100Mhz operation
+ * Also changed the refresh for 100MHz operation
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -90,13 +90,13 @@ void reset_phy(void)
 {
        unsigned short mode_control;
 
-       miiphy_read("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15, &mode_control);
-       miiphy_write("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15,
+       miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
+       miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
                        mode_control & 0xfffe);
        return;
 }
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 /*
  * Helper function to initialize SDRAM controller.
  */
@@ -126,18 +126,24 @@ static void sdram_start(int hi_addr)
        /* normal operation */
        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 }
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
        ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
        ulong test1, test2;
 
+       /* According to AN3221 (MPC5200B SDRAM Initialization and
+        * Configuration), the SDelay register must be written a value of
+        * 0x00000004 as the first step of the SDRAM contorller configuration.
+        */
+       *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+
        /* configure SDRAM start/end for detection */
        *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
@@ -147,9 +153,9 @@ long int initdram(int board_type)
        *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 
        sdram_start(0);
-       test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
        sdram_start(1);
-       test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
        if (test1 > test2) {
                sdram_start(0);
                dramsize = test1;
@@ -172,14 +178,14 @@ long int initdram(int board_type)
        /* let SDRAM CS1 start right after CS0 and disable it */
        *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
 
-#else /* !CFG_RAMBOOT */
+#else /* !CONFIG_SYS_RAMBOOT */
        /* retrieve size of memory connected to SDRAM CS0 */
        dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
        if (dramsize >= 0x13)
                dramsize = (1 << (dramsize - 0x13)) << 20;
        else
                dramsize = 0;
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
        /* return total ram size */
        return dramsize;