#ifdef CONFIG_PCI
#include <command.h>
-#include <cmd_boot.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <cmd_pci.h>
#include <pci.h>
#if (CONFIG_COMMANDS & CFG_CMD_PCI)
if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
continue;
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
+ if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
if (ShortPCIListing)
{
}
}
-char* pci_classes_str(u8 class)
+static char *pci_classes_str(u8 class)
{
- static char *pci_classes[] = {
- "Build before PCI Rev2.0",
- "Mass storage controller",
- "Network controller ",
- "Display controller ",
- "Multimedia device ",
- "Memory controller ",
- "Bridge device ",
- "Simple comm. controller",
- "Base system peripheral ",
- "Input device ",
- "Docking station ",
- "Processor ",
- "Serial bus controller ",
- "Reserved entry ",
- "Does not fit any class "
+ switch (class) {
+ case PCI_CLASS_NOT_DEFINED:
+ return "Build before PCI Rev2.0";
+ break;
+ case PCI_BASE_CLASS_STORAGE:
+ return "Mass storage controller";
+ break;
+ case PCI_BASE_CLASS_NETWORK:
+ return "Network controller";
+ break;
+ case PCI_BASE_CLASS_DISPLAY:
+ return "Display controller";
+ break;
+ case PCI_BASE_CLASS_MULTIMEDIA:
+ return "Multimedia device";
+ break;
+ case PCI_BASE_CLASS_MEMORY:
+ return "Memory controller";
+ break;
+ case PCI_BASE_CLASS_BRIDGE:
+ return "Bridge device";
+ break;
+ case PCI_BASE_CLASS_COMMUNICATION:
+ return "Simple comm. controller";
+ break;
+ case PCI_BASE_CLASS_SYSTEM:
+ return "Base system peripheral";
+ break;
+ case PCI_BASE_CLASS_INPUT:
+ return "Input device";
+ break;
+ case PCI_BASE_CLASS_DOCKING:
+ return "Docking station";
+ break;
+ case PCI_BASE_CLASS_PROCESSOR:
+ return "Processor";
+ break;
+ case PCI_BASE_CLASS_SERIAL:
+ return "Serial bus controller";
+ break;
+ case PCI_BASE_CLASS_INTELLIGENT:
+ return "Intelligent controller";
+ break;
+ case PCI_BASE_CLASS_SATELLITE:
+ return "Satellite controller";
+ break;
+ case PCI_BASE_CLASS_CRYPT:
+ return "Cryptographic device";
+ break;
+ case PCI_BASE_CLASS_SIGNAL_PROCESSING:
+ return "DSP";
+ break;
+ case PCI_CLASS_OTHERS:
+ return "Does not fit any class";
+ break;
+ default:
+ return "???";
+ break;
};
-
- if (class < (sizeof pci_classes / sizeof *pci_classes))
- return pci_classes[(int) class];
-
- return "??? ";
}
/*
pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
- printf("0x%.4x 0x%.4x %s 0x%.2x\n",
+ printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
vendor, device,
pci_classes_str(class), subclass);
}
PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
- pci_classes_str);
+ pci_classes_str);
PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
- PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
- if (header_type & 0x01) { /* PCI-to-PCI bridge */
+ switch (header_type & 0x03) {
+ case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
+ PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
+ PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
+ PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
+ PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
+ PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
+ PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
+ PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
+ PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
+ PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
+ PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
+ PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
+ PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
+ PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
+ break;
+
+ case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
+
+ PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
- } else { /* PCI device */
- PRINT(" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
- PRINT(" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
- PRINT(" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
- PRINT(" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
- PRINT(" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
- PRINT(" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
- PRINT(" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
- PRINT(" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
- PRINT(" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
- PRINT(" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
- PRINT(" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
- PRINT(" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
+ break;
+
+ case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
+
+ PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
+ PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
+ PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
+ PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
+ PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
+ PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
+ PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
+ PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
+ PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
+ PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
+ PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
+ PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
+ PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
+ PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
+ PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
+ PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
+ PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
+ PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
+ PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
+ PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
+ PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
+ PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
+ PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
+ PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
+ break;
+
+ default:
+ printf("unknown header\n");
+ break;
}
#undef PRINT
return 1;
}
+/***************************************************/
+
+
+U_BOOT_CMD(
+ pci, 5, 1, do_pci,
+ "pci - list and access PCI Configuration Space\n",
+ "[bus] [long]\n"
+ " - short or long list of PCI devices on bus 'bus'\n"
+ "pci header b.d.f\n"
+ " - show header of PCI device 'bus.device.function'\n"
+ "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
+ " - display PCI configuration space (CFG)\n"
+ "pci next[.b, .w, .l] b.d.f address\n"
+ " - modify, read and keep CFG address\n"
+ "pci modify[.b, .w, .l] b.d.f address\n"
+ " - modify, auto increment CFG address\n"
+ "pci write[.b, .w, .l] b.d.f address value\n"
+ " - write to CFG address\n"
+);
+
#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */
#endif /* CONFIG_PCI */
projects / karo-tx-uboot.git / blobdiff