/* Alignment exception. */
. = 0x600
Alignment:
- EXCEPTION_PROLOG
+ EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
/* Program check exception */
. = 0x700
ProgramCheck:
- EXCEPTION_PROLOG
+ EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
li r4, 0x556C
sth r4, SWSRR@l(r3)
- li r4, 0xAA39
+ li r4, -0x55C7
sth r4, SWSRR@l(r3)
#else
/* Disable Wathcdog */
mfspr r3, PVR
blr
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbf */
-/* Description: Data Cache block flush */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbf
-ppcDcbf:
- dcbf r0,r3
- blr
-
-/*------------------------------------------------------------------------------- */
-/* Function: ppcDcbi */
-/* Description: Data Cache block Invalidate */
-/* Input: r3 = effective address */
-/* Output: none. */
-/*------------------------------------------------------------------------------- */
- .globl ppcDcbi
-ppcDcbi:
- dcbi r0,r3
- blr
-
-/*--------------------------------------------------------------------------
- * Function: ppcDcbz
- * Description: Data Cache block zero.
- * Input: r3 = effective address
- * Output: none.
- *-------------------------------------------------------------------------- */
-
- .globl ppcDcbz
-ppcDcbz:
- dcbz r0,r3
- blr
-
.globl ppcDWstore
ppcDWstore:
lfd 1, 0(r4)