ARM: enable device tree for beagle

[karo-tx-uboot.git] / include / configs / M5329EVB.h

diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index c207947ff61f2c5558c5c48d13356a2fe4483762..159b178f401757e3104912d951ee69a1a5c09918 100644 (file)
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -196,6 +196,7 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 #define CONFIG_SYS_BOOTMAPSZ           (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN           (CONFIG_SYS_SDRAM_SIZE << 20)
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -215,7 +216,6 @@
 #      define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 #      define CONFIG_SYS_NAND_SIZE             1
 #      define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
-#      define NAND_MAX_CHIPS           1
 #      define NAND_ALLOW_ERASE_ALL     1
 #      define CONFIG_JFFS2_NAND        1
 #      define CONFIG_JFFS2_DEV         "nand0"
@@ -231,13 +231,23 @@
 #define CONFIG_ENV_OFFSET              0x4000
 #define CONFIG_ENV_SECT_SIZE   0x2000
 #define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_IS_EMBEDDED 1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_EC | CF_CACR_CINVA | \
+                                        CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */