Unified codebase for TX28, TX48, TX51, TX53

[karo-tx-uboot.git] / include / configs / MIP405.h

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index e833e6d193366c50ddb9cb59478031cb7abd4ae7..9961fb55ca509c3e6c6381bad334837e21ef4dd8 100644 (file)
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -35,6 +35,9 @@
 #define CONFIG_405GP           1       /* This is a PPC405 CPU         */
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_MIP405          1       /* ...on a MIP405 board         */
+
+#define        CONFIG_SYS_TEXT_BASE    0xFFF80000
+
 /***********************************************************
  * Note that it may also be a MIP405T board which is a subset of the
  * MIP405
@@ -236,11 +239,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
+#define CONFIG_FLASH_SHOW_PROGRESS     45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      256
 
 /*
  * JFFS2 partitions
@@ -288,6 +297,7 @@
 #define FLASH_SIZE_PRELIM       3  /* maximal flash FLASH size bank #0 */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_R
 
 /* Peripheral Bus Mapping */
 #define PER_PLD_ADDR           0xF4000000 /* smallest window is 1MByte 0x10 0000*/
@@ -305,29 +315,15 @@
 #define CONFIG_SYS_OCM_DATA_ADDR       0xF0000000
 #define CONFIG_SYS_OCM_DATA_SIZE       0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_END        CONFIG_SYS_OCM_DATA_SIZE        /* End of On Chip SRAM         */
-#define CONFIG_SYS_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for POST and BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - 32)
 
-#ifdef  CONFIG_POST            /* reserve one word for POST Info */
-#define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_GBL_DATA_OFFSET - 4)
-#endif
-
 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
 #endif
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
-#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
-
-
 /***********************************************************************
  * External peripheral base address
  ***********************************************************************/
@@ -345,7 +341,6 @@
 #define CONFIG_PHY_ADDR                1       /* PHY address                  */
 #define CONFIG_PHY_RESET_DELAY 300     /* Intel LXT971A needs this */
 #define CONFIG_PHY_CMD_DELAY   40      /* Intel LXT971A needs this */
-#define CONFIG_NET_MULTI
 /************************************************************
  * RTC
  ***********************************************************/