arm: socfpga: misc: Export bootmode into environment variable

[karo-tx-uboot.git] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c4ac94d0eb302ec6c64193fc99f109f069b00de8..bed8600a94a109559744bc8283d5120c33b67a26 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -13,14 +13,12 @@
 
 #define CONFIG_SYS_THUMB_BUILD
 
-#define CONFIG_SOCFPGA
-
 /*
  * High level configuration
  */
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_ARCH_MISC_INIT
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
@@ -41,7 +39,7 @@
 #define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
 
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE       (0x10000 - 0x100)
+#define CONFIG_SYS_INIT_RAM_SIZE       (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR                                        \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE -  \
        GENERATED_GBL_DATA_SIZE)
@@ -77,6 +75,11 @@
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
+/*
+ * SDRAM controller
+ */
+#define CONFIG_ALTERA_SDRAM
+
 /*
  * EPCS/EPCQx1 Serial Flash Controller
  */
@@ -84,7 +87,6 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED                30000000
-#define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_BAR
 /*
@@ -100,8 +102,6 @@
  * Ethernet on SoC (EMAC)
  */
 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_NET_MULTI
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
 #define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
@@ -139,7 +139,7 @@
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ                25000
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  12000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  30000
 #endif
 
 /*
@@ -159,7 +159,7 @@
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256     /* FIXME -- SPL only? */
 #endif
 
- /*
+/*
  * I2C support
  */
 #define CONFIG_SYS_I2C
@@ -186,6 +186,29 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #endif
 #define CONFIG_CMD_I2C
 
+/*
+ * QSPI support
+ */
+#ifdef CONFIG_OF_CONTROL       /* QSPI is controlled via DT */
+#define CONFIG_CADENCE_QSPI
+/* Enable multiple SPI NOR flash manufacturers */
+#define CONFIG_SPI_FLASH_STMICRO       /* Micron/Numonyx flash */
+#define CONFIG_SPI_FLASH_SPANSION      /* Spansion flash */
+#define CONFIG_SPI_FLASH_MTD
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK           cm_get_qspi_controller_clk_hz()
+#endif
+#define CONFIG_CQSPI_DECODER           0
+#define CONFIG_CMD_SF
+#endif
+
+#ifdef CONFIG_OF_CONTROL       /* DW SPI is controlled via DT */
+#define CONFIG_DESIGNWARE_SPI
+#define CONFIG_CMD_SPI
+#endif
+
 /*
  * Serial Driver
  */
@@ -226,10 +249,10 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #define CONFIG_USB_GADGET_VBUS_DRAW    2
 
 /* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_DFU_FUNCTION
+#define CONFIG_USB_FUNCTION_DFU
 #define CONFIG_DFU_MMC
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE   (32 * 1024 * 1024)
 #define DFU_DEFAULT_POLL_TIMEOUT       300
@@ -265,22 +288,47 @@ unsigned int cm_get_l4_sp_clk_hz(void);
  * 0xFFFF_FF00 ...... End of SRAM
  */
 #define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_RAM_DEVICE
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SYS_SPL_MALLOC_START    CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_SPL_MALLOC_SIZE     (5 * 1024)
+#define CONFIG_SPL_MAX_SIZE            (64 * 1024)
 
 #define CHUNKSZ_CRC32                  (1 * 1024)      /* FIXME: ewww */
 #define CONFIG_CRC32_VERIFY
 
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT    "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
-
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+
+/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_MMC_SUPPORT
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     2
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot-dtb.img"
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#else
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0xa00 /* offset 2560 sect (1M+256k) */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS     800 /* 400 KB */
+#endif
+#endif
+
+/* SPL QSPI boot support */
+#ifdef CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_DM_SEQ_ALIAS            1
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
+#endif
+
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK               CONFIG_SYS_INIT_SP_ADDR
 
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_PARTITIONS