arm-imx: Fix register definitions

[karo-tx-uboot.git] / include / mpc5xxx.h

diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index daa4d5f6d4cbc5312cd37530f48f9fd8998520ce..a4581a3e6bb818cd506c31d8c1c2d53de43e8a8d 100644 (file)
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -39,6 +39,7 @@
 
 /* Exception offsets (PowerPC standard) */
 #define EXC_OFF_SYS_RESET      0x0100
+#define _START_OFFSET          EXC_OFF_SYS_RESET
 
 /* useful macros for manipulating CSx_START/STOP */
 #if defined(CONFIG_MGT5100)
@@ -188,7 +189,14 @@
 #define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
 #define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
 #define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
-#define MPC5XXX_WU_GPIO_DATA    (MPC5XXX_WU_GPIO + 0x000c)
+#define MPC5XXX_WU_GPIO_DATA_O  (MPC5XXX_WU_GPIO + 0x000c)
+#define MPC5XXX_WU_GPIO_DATA_I  (MPC5XXX_WU_GPIO + 0x0020)
+
+/* GPIO pins */
+#define GPIO_WKUP_7            0x80000000UL
+#define GPIO_PSC6_0            0x10000000UL
+#define GPIO_PSC3_9            0x04000000UL
+#define GPIO_PSC1_4            0x01000000UL
 
 /* PCI registers */
 #define MPC5XXX_PCI_CMD                (MPC5XXX_PCI + 0x04)
@@ -232,6 +240,65 @@
 #define MPC5XXX_ICTL_PER_STS   (MPC5XXX_ICTL + 0x0030)
 #define MPC5XXX_ICTL_BUS_STS   (MPC5XXX_ICTL + 0x0038)
 
+#define NR_IRQS                        64
+
+/* IRQ mapping - these are our logical IRQ numbers */
+#define MPC5XXX_CRIT_IRQ_NUM   4
+#define MPC5XXX_MAIN_IRQ_NUM   17
+#define MPC5XXX_SDMA_IRQ_NUM   17
+#define MPC5XXX_PERP_IRQ_NUM   23
+
+#define MPC5XXX_CRIT_IRQ_BASE  1
+#define MPC5XXX_MAIN_IRQ_BASE  (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
+#define MPC5XXX_SDMA_IRQ_BASE  (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
+#define MPC5XXX_PERP_IRQ_BASE  (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
+
+#define MPC5XXX_IRQ0                   (MPC5XXX_CRIT_IRQ_BASE + 0)
+#define MPC5XXX_SLICE_TIMER_0_IRQ      (MPC5XXX_CRIT_IRQ_BASE + 1)
+#define MPC5XXX_HI_INT_IRQ             (MPC5XXX_CRIT_IRQ_BASE + 2)
+#define MPC5XXX_CCS_IRQ                        (MPC5XXX_CRIT_IRQ_BASE + 3)
+
+#define MPC5XXX_IRQ1                   (MPC5XXX_MAIN_IRQ_BASE + 1)
+#define MPC5XXX_IRQ2                   (MPC5XXX_MAIN_IRQ_BASE + 2)
+#define MPC5XXX_IRQ3                   (MPC5XXX_MAIN_IRQ_BASE + 3)
+#define MPC5XXX_RTC_PINT_IRQ           (MPC5XXX_MAIN_IRQ_BASE + 5)
+#define MPC5XXX_RTC_SINT_IRQ           (MPC5XXX_MAIN_IRQ_BASE + 6)
+#define MPC5XXX_RTC_GPIO_STD_IRQ       (MPC5XXX_MAIN_IRQ_BASE + 7)
+#define MPC5XXX_RTC_GPIO_WKUP_IRQ      (MPC5XXX_MAIN_IRQ_BASE + 8)
+#define MPC5XXX_TMR0_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 9)
+#define MPC5XXX_TMR1_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 10)
+#define MPC5XXX_TMR2_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 11)
+#define MPC5XXX_TMR3_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 12)
+#define MPC5XXX_TMR4_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 13)
+#define MPC5XXX_TMR5_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 14)
+#define MPC5XXX_TMR6_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 15)
+#define MPC5XXX_TMR7_IRQ               (MPC5XXX_MAIN_IRQ_BASE + 16)
+
+#define MPC5XXX_SDMA_IRQ               (MPC5XXX_PERP_IRQ_BASE + 0)
+#define MPC5XXX_PSC1_IRQ               (MPC5XXX_PERP_IRQ_BASE + 1)
+#define MPC5XXX_PSC2_IRQ               (MPC5XXX_PERP_IRQ_BASE + 2)
+#define MPC5XXX_PSC3_IRQ               (MPC5XXX_PERP_IRQ_BASE + 3)
+#define MPC5XXX_PSC6_IRQ               (MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_IRDA_IRQ               (MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_FEC_IRQ                        (MPC5XXX_PERP_IRQ_BASE + 5)
+#define MPC5XXX_USB_IRQ                        (MPC5XXX_PERP_IRQ_BASE + 6)
+#define MPC5XXX_ATA_IRQ                        (MPC5XXX_PERP_IRQ_BASE + 7)
+#define MPC5XXX_PCI_CNTRL_IRQ          (MPC5XXX_PERP_IRQ_BASE + 8)
+#define MPC5XXX_PCI_SCIRX_IRQ          (MPC5XXX_PERP_IRQ_BASE + 9)
+#define MPC5XXX_PCI_SCITX_IRQ          (MPC5XXX_PERP_IRQ_BASE + 10)
+#define MPC5XXX_PSC4_IRQ               (MPC5XXX_PERP_IRQ_BASE + 11)
+#define MPC5XXX_PSC5_IRQ               (MPC5XXX_PERP_IRQ_BASE + 12)
+#define MPC5XXX_SPI_MODF_IRQ           (MPC5XXX_PERP_IRQ_BASE + 13)
+#define MPC5XXX_SPI_SPIF_IRQ           (MPC5XXX_PERP_IRQ_BASE + 14)
+#define MPC5XXX_I2C1_IRQ               (MPC5XXX_PERP_IRQ_BASE + 15)
+#define MPC5XXX_I2C2_IRQ               (MPC5XXX_PERP_IRQ_BASE + 16)
+#define MPC5XXX_MSCAN1_IRQ             (MPC5XXX_PERP_IRQ_BASE + 17)
+#define MPC5XXX_MSCAN2_IRQ             (MPC5XXX_PERP_IRQ_BASE + 18)
+#define MPC5XXX_IR_RX_IRQ              (MPC5XXX_PERP_IRQ_BASE + 19)
+#define MPC5XXX_IR_TX_IRQ              (MPC5XXX_PERP_IRQ_BASE + 20)
+#define MPC5XXX_XLB_ARB_IRQ            (MPC5XXX_PERP_IRQ_BASE + 21)
+#define MPC5XXX_BDLC_IRQ               (MPC5XXX_PERP_IRQ_BASE + 22)
+
 /* General Purpose Timers registers */
 #define MPC5XXX_GPT0_ENABLE            (MPC5XXX_GPT + 0x0)
 #define MPC5XXX_GPT0_COUNTER           (MPC5XXX_GPT + 0x4)