arch/arm/boot/dts/imx6qdl-tx6.dtsi

   1 /*
   2  * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14
  15 / {
  16         aliases {
  17 #if 0
  18                 can0 = &can2;
  19                 can1 = &can1;
  20 #endif
  21                 ethernet0 = &fec;
  22                 lcdif_23bit_pins_a = &pinctrl_disp0_1;
  23                 lcdif_24bit_pins_a = &pinctrl_disp0_2;
  24                 pwm0 = &pwm1;
  25                 pwm1 = &pwm2;
  26                 reg_can_xcvr = &reg_can_xcvr;
  27                 stk5led = &user_led;
  28                 usbotg = &usbotg;
  29                 sdhc0 = &usdhc1;
  30                 sdhc1 = &usdhc2;
  31         };
  32
  33         memory {
  34                 reg = <0 0>; /* will be filled by U-Boot */
  35         };
  36
  37         clocks {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40                 mclk: clock@0 {
  41                         compatible = "fixed-clock";
  42                         reg = <0>;
  43                         #clock-cells = <0>;
  44                         clock-frequency = <27000000>;
  45                 };
  46         };
  47 #if 0
  48         gpio-keys {
  49                 compatible = "gpio-keys";
  50
  51                 power {
  52                         label = "Power Button";
  53                         gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  54                         linux,code = <KEY_POWER>;
  55                         gpio-key,wakeup;
  56                 };
  57         };
  58 #endif
  59         leds {
  60                 compatible = "gpio-leds";
  61
  62                 user_led: user {
  63                         label = "Heartbeat";
  64                         gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  65                         linux,default-trigger = "heartbeat";
  66                 };
  67         };
  68
  69         regulators {
  70                 compatible = "simple-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 reg_3v3_etn: regulator@0 {
  75                         compatible = "regulator-fixed";
  76                         reg = <0>;
  77                         regulator-name = "3V3_ETN";
  78                         regulator-min-microvolt = <3300000>;
  79                         regulator-max-microvolt = <3300000>;
  80                         pinctrl-names = "default";
  81                         pinctrl-0 = <&pinctrl_etnphy_power>;
  82                         gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  83                         enable-active-high;
  84                 };
  85
  86                 reg_2v5: regulator@1 {
  87                         compatible = "regulator-fixed";
  88                         reg = <1>;
  89                         regulator-name = "2V5";
  90                         regulator-min-microvolt = <2500000>;
  91                         regulator-max-microvolt = <2500000>;
  92                         regulator-always-on;
  93                 };
  94
  95                 reg_3v3: regulator@2 {
  96                         compatible = "regulator-fixed";
  97                         reg = <2>;
  98                         regulator-name = "3V3";
  99                         regulator-min-microvolt = <3300000>;
 100                         regulator-max-microvolt = <3300000>;
 101                         regulator-always-on;
 102                 };
 103
 104                 reg_can_xcvr: regulator@3 {
 105                         compatible = "regulator-fixed";
 106                         reg = <3>;
 107                         regulator-name = "CAN XCVR";
 108                         regulator-min-microvolt = <3300000>;
 109                         regulator-max-microvolt = <3300000>;
 110                         pinctrl-names = "default";
 111                         pinctrl-0 = <&pinctrl_flexcan_xcvr>;
 112                         gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 113                         enable-active-low;
 114                 };
 115
 116                 reg_lcd0_pwr: regulator@4 {
 117                         compatible = "regulator-fixed";
 118                         reg = <4>;
 119                         regulator-name = "LCD0 POWER";
 120                         regulator-min-microvolt = <3300000>;
 121                         regulator-max-microvolt = <3300000>;
 122                         pinctrl-names = "default";
 123                         pinctrl-0 = <&pinctrl_lcd0_pwr>;
 124                         gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 125                         enable-active-high;
 126                         regulator-boot-on;
 127                         regulator-always-on;
 128                         status = "disabled";
 129                 };
 130
 131                 reg_lcd1_pwr: regulator@5 {
 132                         compatible = "regulator-fixed";
 133                         reg = <5>;
 134                         regulator-name = "LCD1 POWER";
 135                         regulator-min-microvolt = <3300000>;
 136                         regulator-max-microvolt = <3300000>;
 137                         pinctrl-names = "default";
 138                         pinctrl-0 = <&pinctrl_lcd1_pwr>;
 139                         gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
 140                         enable-active-high;
 141                         regulator-boot-on;
 142                         regulator-always-on;
 143                         status = "disabled";
 144                 };
 145
 146                 reg_usbh1_vbus: regulator@6 {
 147                         compatible = "regulator-fixed";
 148                         reg = <6>;
 149                         regulator-name = "usbh1_vbus";
 150                         regulator-min-microvolt = <5000000>;
 151                         regulator-max-microvolt = <5000000>;
 152                         pinctrl-names = "default";
 153                         pinctrl-0 = <&pinctrl_usbh1_vbus>;
 154                         gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 155                         enable-active-high;
 156                 };
 157
 158                 reg_usbotg_vbus: regulator@7 {
 159                         compatible = "regulator-fixed";
 160                         reg = <7>;
 161                         regulator-name = "usbotg_vbus";
 162                         regulator-min-microvolt = <5000000>;
 163                         regulator-max-microvolt = <5000000>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&pinctrl_usbotg_vbus>;
 166                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 167                         enable-active-high;
 168                 };
 169         };
 170
 171         sound {
 172                 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
 173                              "fsl,imx-audio-sgtl5000";
 174                 model = "sgtl5000-audio";
 175                 pinctrl-names = "default";
 176                 pinctrl-0 = <&pinctrl_audmux>;
 177                 ssi-controller = <&ssi1>;
 178                 audio-codec = <&sgtl5000>;
 179                 audio-routing =
 180                         "MIC_IN", "Mic Jack",
 181                         "Mic Jack", "Mic Bias",
 182                         "Headphone Jack", "HP_OUT";
 183                 mux-int-port = <1>;
 184                 mux-ext-port = <5>;
 185         };
 186 };
 187
 188 &audmux {
 189         status = "okay";
 190 };
 191
 192 #if 0
 193 &can1 {
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&pinctrl_flexcan1>;
 196         xceiver-supply = <&reg_can_xcvr>;
 197         status = "okay";
 198 };
 199
 200 &can2 {
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_flexcan2>;
 203         xceiver-supply = <&reg_can_xcvr>;
 204         status = "okay";
 205 };
 206 #endif
 207
 208 &ecspi1 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_ecspi1>;
 211         fsl,spi-num-chipselects = <2>;
 212         cs-gpios = <
 213                 &gpio2 30 GPIO_ACTIVE_HIGH
 214                 &gpio3 19 GPIO_ACTIVE_HIGH
 215         >;
 216         status = "okay";
 217
 218         spidev0: spi@0 {
 219                 compatible = "spidev";
 220                 reg = <0>;
 221                 spi-max-frequency = <54000000>;
 222         };
 223
 224         spidev1: spi@1 {
 225                 compatible = "spidev";
 226                 reg = <1>;
 227                 spi-max-frequency = <54000000>;
 228         };
 229 };
 230
 231 &fec {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_enet>;
 234         phy-mode = "rmii";
 235         phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
 236         phy-supply = <&reg_3v3_etn>;
 237         status = "okay";
 238 };
 239
 240 &gpmi {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_gpmi_nand>;
 243         nand-on-flash-bbt;
 244         fsl,no-blockmark-swap;
 245         status = "okay";
 246 };
 247
 248 &i2c1 {
 249         pinctrl-names = "default";
 250         pinctrl-0 = <&pinctrl_i2c1>;
 251         clock-frequency = <400000>;
 252         status = "okay";
 253
 254         ds1339: rtc@68 {
 255                 compatible = "dallas,ds1339";
 256                 reg = <0x68>;
 257         };
 258 };
 259
 260 &i2c3 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_i2c3>;
 263         clock-frequency = <400000>;
 264         status = "okay";
 265
 266         sgtl5000: sgtl5000@0a {
 267                 compatible = "fsl,sgtl5000";
 268                 reg = <0x0a>;
 269                 VDDA-supply = <&reg_2v5>;
 270                 VDDIO-supply = <&reg_3v3>;
 271                 clocks = <&mclk>;
 272         };
 273
 274         polytouch: edt-ft5x06@38 {
 275                 compatible = "edt,edt-ft5x06";
 276                 reg = <0x38>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&pinctrl_edt_ft5x06>;
 279                 interrupt-parent = <&gpio6>;
 280                 interrupts = <15 0>;
 281                 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
 282                 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 283                 linux,wakeup;
 284         };
 285
 286         touchscreen: tsc2007@48 {
 287                 compatible = "ti,tsc2007";
 288                 reg = <0x48>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&pinctrl_tsc2007>;
 291                 interrupt-parent = <&gpio3>;
 292                 interrupts = <26 0>;
 293                 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 294                 ti,x-plate-ohms = <660>;
 295                 linux,wakeup;
 296         };
 297 };
 298
 299 &iomuxc {
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&pinctrl_hog>;
 302
 303         imx6qdl-tx6 {
 304                 pinctrl_hog: hoggrp {
 305                         fsl,pins = <
 306                                 MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b1 /* LED */
 307                                 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06         0x1b0b1 /* ETN PHY RESET */
 308                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b1 /* ETN PHY INT */
 309                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* PWR BTN */
 310                         >;
 311                 };
 312
 313                 pinctrl_audmux: audmuxgrp {
 314                         fsl,pins = <
 315                                 MX6QDL_PAD_KEY_ROW1__AUD5_RXD           0x130b0 /* SSI1_RXD */
 316                                 MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0 /* SSI1_TXD */
 317                                 MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0 /* SSI1_CLK */
 318                                 MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0 /* SSI1_FS */
 319                         >;
 320                 };
 321
 322                 pinctrl_disp0_1: disp0grp-1 {
 323                         fsl,pins = <
 324                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 325                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 326                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 327                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 328                                 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
 329                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 330                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 331                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 332                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 333                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 334                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 335                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 336                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 337                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 338                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 339                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 340                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 341                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 342                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 343                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 344                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 345                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 346                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 347                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 348                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 349                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 350                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 351                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 352                         >;
 353                 };
 354
 355                 pinctrl_disp0_2: disp0grp-2 {
 356                         fsl,pins = <
 357                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 358                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 359                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 360                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 361                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 362                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 363                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 364                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 365                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 366                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 367                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 368                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 369                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 370                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 371                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 372                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 373                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 374                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 375                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 376                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 377                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 378                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 379                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 380                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 381                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 382                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 383                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 384                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 385                         >;
 386                 };
 387
 388                 pinctrl_ecspi1: ecspi1grp {
 389                         fsl,pins = <
 390                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x0b0b0
 391                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x0b0b0
 392                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x0b0b0
 393                                 MX6QDL_PAD_GPIO_19__ECSPI1_RDY          0x0b0b0
 394                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x0b0b0 /* SPI CS0 */
 395                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x0b0b0 /* SPI CS1 */
 396                         >;
 397                 };
 398
 399                 pinctrl_edt_ft5x06: edt-ft5x06grp {
 400                         fsl,pins = <
 401                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0 /* Interrupt */
 402                                 MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x1b0b0 /* Reset */
 403                                 MX6QDL_PAD_EIM_A17__GPIO2_IO21          0x1b0b0 /* Wake */
 404                         >;
 405                 };
 406
 407                 pinctrl_enet: enetgrp {
 408                         fsl,pins = <
 409                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 410                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 411                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 412                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 413                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 414                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 415                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 416                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 417                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 418                         >;
 419                 };
 420
 421                 pinctrl_etnphy_power: etnphy-pwrgrp {
 422                         fsl,pins = <
 423                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b1 /* ETN PHY POWER */
 424                         >;
 425                 };
 426
 427                 pinctrl_flexcan1: flexcan1grp {
 428                         fsl,pins = <
 429                                 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 430                                 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 431                         >;
 432                 };
 433
 434                 pinctrl_flexcan2: flexcan2grp {
 435                         fsl,pins = <
 436                                 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 437                                 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 438                         >;
 439                 };
 440
 441                 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
 442                         fsl,pins = <
 443                                 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21       0x1b0b0 /* Flexcan XCVR enable */
 444                         >;
 445                 };
 446
 447                 pinctrl_gpmi_nand: gpminandgrp {
 448                         fsl,pins = <
 449                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0x0b0b1
 450                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0x0b0b1
 451                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0x0b0b1
 452                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0x0b000
 453                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0x0b0b1
 454                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0x0b0b1
 455                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0x0b0b1
 456                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0x0b0b1
 457                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0x0b0b1
 458                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0x0b0b1
 459                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0x0b0b1
 460                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0x0b0b1
 461                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0x0b0b1
 462                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0x0b0b1
 463                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0x0b0b1
 464                         >;
 465                 };
 466
 467                 pinctrl_i2c1: i2c1grp {
 468                         fsl,pins = <
 469                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 470                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 471                         >;
 472                 };
 473
 474                 pinctrl_i2c3: i2c3grp {
 475                         fsl,pins = <
 476                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 477                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 478                         >;
 479                 };
 480
 481                 pinctrl_kpp: kppgrp {
 482                         fsl,pins = <
 483                                 MX6QDL_PAD_GPIO_9__KEY_COL6             0x1b0b1
 484                                 MX6QDL_PAD_GPIO_4__KEY_COL7             0x1b0b1
 485                                 MX6QDL_PAD_KEY_COL2__KEY_COL2           0x1b0b1
 486                                 MX6QDL_PAD_KEY_COL3__KEY_COL3           0x1b0b1
 487                                 MX6QDL_PAD_GPIO_2__KEY_ROW6             0x1b0b1
 488                                 MX6QDL_PAD_GPIO_5__KEY_ROW7             0x1b0b1
 489                                 MX6QDL_PAD_KEY_ROW2__KEY_ROW2           0x1b0b1
 490                                 MX6QDL_PAD_KEY_ROW3__KEY_ROW3           0x1b0b1
 491                         >;
 492                 };
 493
 494                 pinctrl_lcd0_pwr: lcd0-pwrgrp {
 495                         fsl,pins = <
 496                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x1b0b1 /* LCD Reset */
 497                         >;
 498                 };
 499
 500                 pinctrl_lcd1_pwr: lcd1-pwrgrp {
 501                         fsl,pins = <
 502                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b1 /* LCD Power Enable */
 503                         >;
 504                 };
 505
 506                 pinctrl_pwm1: pwm1grp {
 507                         fsl,pins = <
 508                                 MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 509                         >;
 510                 };
 511
 512                 pinctrl_pwm2: pwm2grp {
 513                         fsl,pins = <
 514                                 MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 515                         >;
 516                 };
 517
 518                 pinctrl_tsc2007: tsc2007grp {
 519                         fsl,pins = <
 520                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0 /* Interrupt */
 521                         >;
 522                 };
 523
 524                 pinctrl_uart1: uart1grp {
 525                         fsl,pins = <
 526                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 527                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 528                         >;
 529                 };
 530
 531                 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
 532                         fsl,pins = <
 533                                 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B        0x1b0b1
 534                                 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B        0x1b0b1
 535                         >;
 536                 };
 537
 538                 pinctrl_uart2: uart2grp {
 539                         fsl,pins = <
 540                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 541                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 542                         >;
 543                 };
 544
 545                 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
 546                         fsl,pins = <
 547                                 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 548                                 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 549                         >;
 550                 };
 551
 552                 pinctrl_uart3: uart3grp {
 553                         fsl,pins = <
 554                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 555                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 556                         >;
 557                 };
 558
 559                 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
 560                         fsl,pins = <
 561                                 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B        0x1b0b1
 562                                 MX6QDL_PAD_SD3_RST__UART3_RTS_B         0x1b0b1
 563                         >;
 564                 };
 565
 566                 pinctrl_usbh1_vbus: usbh1-vbusgrp {
 567                         fsl,pins = <
 568                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x1b0b0 /* USBH1_VBUSEN */
 569                         >;
 570                 };
 571
 572                 pinctrl_usbotg: usbotggrp {
 573                         fsl,pins = <
 574                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x17059
 575                         >;
 576                 };
 577
 578                 pinctrl_usbotg_vbus: usbotg-vbusgrp {
 579                         fsl,pins = <
 580                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0 /* USBOTG_VBUSEN */
 581                         >;
 582                 };
 583
 584                 pinctrl_usdhc1: usdhc1grp {
 585                         fsl,pins = <
 586                                 MX6QDL_PAD_SD1_CMD__SD1_CMD             0x070b1
 587                                 MX6QDL_PAD_SD1_CLK__SD1_CLK             0x070b1
 588                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x070b1
 589                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x070b1
 590                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x070b1
 591                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x070b1
 592                                 MX6QDL_PAD_SD3_CMD__GPIO7_IO02          0x170b0 /* SD1 CD */
 593                         >;
 594                 };
 595
 596                 pinctrl_usdhc2: usdhc2grp {
 597                         fsl,pins = <
 598                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x070b1
 599                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x070b1
 600                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x070b1
 601                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x070b1
 602                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x070b1
 603                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x070b1
 604                                 MX6QDL_PAD_SD3_CLK__GPIO7_IO03          0x170b0 /* SD2 CD */
 605                         >;
 606                 };
 607         };
 608 };
 609
 610 #if 0
 611 &kpp {
 612         pinctrl-names = "default";
 613         pinctrl-0 = <&pinctrl_kpp>;
 614         /* sample keymap */
 615         /* row/col 0,1 are mapped to KPP row/col 6,7 */
 616         linux,keymap = <
 617                 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
 618                 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
 619                 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
 620                 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
 621                 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
 622                 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
 623                 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
 624                 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
 625                 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
 626                 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
 627                 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
 628         >;
 629 };
 630 #endif
 631
 632 &pwm1 {
 633         pinctrl-names = "default";
 634         pinctrl-0 = <&pinctrl_pwm1>;
 635         #pwm-cells = <2>;
 636         status = "disabled";
 637 };
 638
 639 &pwm2 {
 640         pinctrl-names = "default";
 641         pinctrl-0 = <&pinctrl_pwm2>;
 642         #pwm-cells = <2>;
 643         status = "okay";
 644 };
 645
 646 &ssi1 {
 647         fsl,mode = "i2s-slave";
 648         status = "okay";
 649 };
 650
 651 &uart1 {
 652         pinctrl-names = "default";
 653         pinctrl-0 = <&pinctrl_uart1>;
 654         status = "okay";
 655 };
 656
 657 &uart2 {
 658         pinctrl-names = "default";
 659         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
 660         status = "okay";
 661 };
 662
 663 &uart3 {
 664         pinctrl-names = "default";
 665         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
 666         status = "okay";
 667 };
 668
 669 &usbh1 {
 670         vbus-supply = <&reg_usbh1_vbus>;
 671         dr_mode = "host";
 672         disable-over-current;
 673         status = "okay";
 674 };
 675
 676 &usbotg {
 677         vbus-supply = <&reg_usbotg_vbus>;
 678         pinctrl-names = "default";
 679         pinctrl-0 = <&pinctrl_usbotg>;
 680         dr_mode = "peripheral";
 681         disable-over-current;
 682         status = "okay";
 683 };
 684
 685 &usdhc1 {
 686         pinctrl-names = "default";
 687         pinctrl-0 = <&pinctrl_usdhc1>;
 688         bus-width = <4>;
 689         no-1-8-v;
 690         cd-gpios = <&gpio7 2 0>;
 691         fsl,wp-controller;
 692         status = "okay";
 693 };
 694
 695 &usdhc2 {
 696         pinctrl-names = "default";
 697         pinctrl-0 = <&pinctrl_usdhc2>;
 698         bus-width = <4>;
 699         no-1-8-v;
 700         cd-gpios = <&gpio7 3 0>;
 701         fsl,wp-controller;
 702         status = "okay";
 703 };