drivers/dma/sun6i-dma.c

   1 /*
   2  * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
   3  * Author: Sugar <shuge@allwinnertech.com>
   4  *
   5  * Copyright (C) 2014 Maxime Ripard
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/of_dma.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/reset.h>
  24 #include <linux/slab.h>
  25 #include <linux/types.h>
  26
  27 #include "virt-dma.h"
  28
  29 /*
  30  * Common registers
  31  */
  32 #define DMA_IRQ_EN(x)           ((x) * 0x04)
  33 #define DMA_IRQ_HALF                    BIT(0)
  34 #define DMA_IRQ_PKG                     BIT(1)
  35 #define DMA_IRQ_QUEUE                   BIT(2)
  36
  37 #define DMA_IRQ_CHAN_NR                 8
  38 #define DMA_IRQ_CHAN_WIDTH              4
  39
  40
  41 #define DMA_IRQ_STAT(x)         ((x) * 0x04 + 0x10)
  42
  43 #define DMA_STAT                0x30
  44
  45 /*
  46  * sun8i specific registers
  47  */
  48 #define SUN8I_DMA_GATE          0x20
  49 #define SUN8I_DMA_GATE_ENABLE   0x4
  50
  51 /*
  52  * Channels specific registers
  53  */
  54 #define DMA_CHAN_ENABLE         0x00
  55 #define DMA_CHAN_ENABLE_START           BIT(0)
  56 #define DMA_CHAN_ENABLE_STOP            0
  57
  58 #define DMA_CHAN_PAUSE          0x04
  59 #define DMA_CHAN_PAUSE_PAUSE            BIT(1)
  60 #define DMA_CHAN_PAUSE_RESUME           0
  61
  62 #define DMA_CHAN_LLI_ADDR       0x08
  63
  64 #define DMA_CHAN_CUR_CFG        0x0c
  65 #define DMA_CHAN_CFG_SRC_DRQ(x)         ((x) & 0x1f)
  66 #define DMA_CHAN_CFG_SRC_IO_MODE        BIT(5)
  67 #define DMA_CHAN_CFG_SRC_LINEAR_MODE    (0 << 5)
  68 #define DMA_CHAN_CFG_SRC_BURST(x)       (((x) & 0x3) << 7)
  69 #define DMA_CHAN_CFG_SRC_WIDTH(x)       (((x) & 0x3) << 9)
  70
  71 #define DMA_CHAN_CFG_DST_DRQ(x)         (DMA_CHAN_CFG_SRC_DRQ(x) << 16)
  72 #define DMA_CHAN_CFG_DST_IO_MODE        (DMA_CHAN_CFG_SRC_IO_MODE << 16)
  73 #define DMA_CHAN_CFG_DST_LINEAR_MODE    (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
  74 #define DMA_CHAN_CFG_DST_BURST(x)       (DMA_CHAN_CFG_SRC_BURST(x) << 16)
  75 #define DMA_CHAN_CFG_DST_WIDTH(x)       (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
  76
  77 #define DMA_CHAN_CUR_SRC        0x10
  78
  79 #define DMA_CHAN_CUR_DST        0x14
  80
  81 #define DMA_CHAN_CUR_CNT        0x18
  82
  83 #define DMA_CHAN_CUR_PARA       0x1c
  84
  85
  86 /*
  87  * Various hardware related defines
  88  */
  89 #define LLI_LAST_ITEM   0xfffff800
  90 #define NORMAL_WAIT     8
  91 #define DRQ_SDRAM       1
  92
  93 /*
  94  * Hardware channels / ports representation
  95  *
  96  * The hardware is used in several SoCs, with differing numbers
  97  * of channels and endpoints. This structure ties those numbers
  98  * to a certain compatible string.
  99  */
 100 struct sun6i_dma_config {
 101         u32 nr_max_channels;
 102         u32 nr_max_requests;
 103         u32 nr_max_vchans;
 104 };
 105
 106 /*
 107  * Hardware representation of the LLI
 108  *
 109  * The hardware will be fed the physical address of this structure,
 110  * and read its content in order to start the transfer.
 111  */
 112 struct sun6i_dma_lli {
 113         u32                     cfg;
 114         u32                     src;
 115         u32                     dst;
 116         u32                     len;
 117         u32                     para;
 118         u32                     p_lli_next;
 119
 120         /*
 121          * This field is not used by the DMA controller, but will be
 122          * used by the CPU to go through the list (mostly for dumping
 123          * or freeing it).
 124          */
 125         struct sun6i_dma_lli    *v_lli_next;
 126 };
 127
 128
 129 struct sun6i_desc {
 130         struct virt_dma_desc    vd;
 131         dma_addr_t              p_lli;
 132         struct sun6i_dma_lli    *v_lli;
 133 };
 134
 135 struct sun6i_pchan {
 136         u32                     idx;
 137         void __iomem            *base;
 138         struct sun6i_vchan      *vchan;
 139         struct sun6i_desc       *desc;
 140         struct sun6i_desc       *done;
 141 };
 142
 143 struct sun6i_vchan {
 144         struct virt_dma_chan    vc;
 145         struct list_head        node;
 146         struct dma_slave_config cfg;
 147         struct sun6i_pchan      *phy;
 148         u8                      port;
 149 };
 150
 151 struct sun6i_dma_dev {
 152         struct dma_device       slave;
 153         void __iomem            *base;
 154         struct clk              *clk;
 155         int                     irq;
 156         spinlock_t              lock;
 157         struct reset_control    *rstc;
 158         struct tasklet_struct   task;
 159         atomic_t                tasklet_shutdown;
 160         struct list_head        pending;
 161         struct dma_pool         *pool;
 162         struct sun6i_pchan      *pchans;
 163         struct sun6i_vchan      *vchans;
 164         const struct sun6i_dma_config *cfg;
 165 };
 166
 167 static struct device *chan2dev(struct dma_chan *chan)
 168 {
 169         return &chan->dev->device;
 170 }
 171
 172 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
 173 {
 174         return container_of(d, struct sun6i_dma_dev, slave);
 175 }
 176
 177 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
 178 {
 179         return container_of(chan, struct sun6i_vchan, vc.chan);
 180 }
 181
 182 static inline struct sun6i_desc *
 183 to_sun6i_desc(struct dma_async_tx_descriptor *tx)
 184 {
 185         return container_of(tx, struct sun6i_desc, vd.tx);
 186 }
 187
 188 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
 189 {
 190         dev_dbg(sdev->slave.dev, "Common register:\n"
 191                 "\tmask0(%04x): 0x%08x\n"
 192                 "\tmask1(%04x): 0x%08x\n"
 193                 "\tpend0(%04x): 0x%08x\n"
 194                 "\tpend1(%04x): 0x%08x\n"
 195                 "\tstats(%04x): 0x%08x\n",
 196                 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
 197                 DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
 198                 DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
 199                 DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
 200                 DMA_STAT, readl(sdev->base + DMA_STAT));
 201 }
 202
 203 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
 204                                             struct sun6i_pchan *pchan)
 205 {
 206         phys_addr_t reg = virt_to_phys(pchan->base);
 207
 208         dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n"
 209                 "\t___en(%04x): \t0x%08x\n"
 210                 "\tpause(%04x): \t0x%08x\n"
 211                 "\tstart(%04x): \t0x%08x\n"
 212                 "\t__cfg(%04x): \t0x%08x\n"
 213                 "\t__src(%04x): \t0x%08x\n"
 214                 "\t__dst(%04x): \t0x%08x\n"
 215                 "\tcount(%04x): \t0x%08x\n"
 216                 "\t_para(%04x): \t0x%08x\n\n",
 217                 pchan->idx, &reg,
 218                 DMA_CHAN_ENABLE,
 219                 readl(pchan->base + DMA_CHAN_ENABLE),
 220                 DMA_CHAN_PAUSE,
 221                 readl(pchan->base + DMA_CHAN_PAUSE),
 222                 DMA_CHAN_LLI_ADDR,
 223                 readl(pchan->base + DMA_CHAN_LLI_ADDR),
 224                 DMA_CHAN_CUR_CFG,
 225                 readl(pchan->base + DMA_CHAN_CUR_CFG),
 226                 DMA_CHAN_CUR_SRC,
 227                 readl(pchan->base + DMA_CHAN_CUR_SRC),
 228                 DMA_CHAN_CUR_DST,
 229                 readl(pchan->base + DMA_CHAN_CUR_DST),
 230                 DMA_CHAN_CUR_CNT,
 231                 readl(pchan->base + DMA_CHAN_CUR_CNT),
 232                 DMA_CHAN_CUR_PARA,
 233                 readl(pchan->base + DMA_CHAN_CUR_PARA));
 234 }
 235
 236 static inline s8 convert_burst(u32 maxburst)
 237 {
 238         switch (maxburst) {
 239         case 1:
 240                 return 0;
 241         case 8:
 242                 return 2;
 243         default:
 244                 return -EINVAL;
 245         }
 246 }
 247
 248 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
 249 {
 250         if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
 251             (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
 252                 return -EINVAL;
 253
 254         return addr_width >> 1;
 255 }
 256
 257 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
 258                                struct sun6i_dma_lli *next,
 259                                dma_addr_t next_phy,
 260                                struct sun6i_desc *txd)
 261 {
 262         if ((!prev && !txd) || !next)
 263                 return NULL;
 264
 265         if (!prev) {
 266                 txd->p_lli = next_phy;
 267                 txd->v_lli = next;
 268         } else {
 269                 prev->p_lli_next = next_phy;
 270                 prev->v_lli_next = next;
 271         }
 272
 273         next->p_lli_next = LLI_LAST_ITEM;
 274         next->v_lli_next = NULL;
 275
 276         return next;
 277 }
 278
 279 static inline int sun6i_dma_cfg_lli(struct sun6i_dma_lli *lli,
 280                                     dma_addr_t src,
 281                                     dma_addr_t dst, u32 len,
 282                                     struct dma_slave_config *config)
 283 {
 284         u8 src_width, dst_width, src_burst, dst_burst;
 285
 286         if (!config)
 287                 return -EINVAL;
 288
 289         src_burst = convert_burst(config->src_maxburst);
 290         if (src_burst)
 291                 return src_burst;
 292
 293         dst_burst = convert_burst(config->dst_maxburst);
 294         if (dst_burst)
 295                 return dst_burst;
 296
 297         src_width = convert_buswidth(config->src_addr_width);
 298         if (src_width)
 299                 return src_width;
 300
 301         dst_width = convert_buswidth(config->dst_addr_width);
 302         if (dst_width)
 303                 return dst_width;
 304
 305         lli->cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |
 306                 DMA_CHAN_CFG_SRC_WIDTH(src_width) |
 307                 DMA_CHAN_CFG_DST_BURST(dst_burst) |
 308                 DMA_CHAN_CFG_DST_WIDTH(dst_width);
 309
 310         lli->src = src;
 311         lli->dst = dst;
 312         lli->len = len;
 313         lli->para = NORMAL_WAIT;
 314
 315         return 0;
 316 }
 317
 318 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
 319                                       struct sun6i_dma_lli *lli)
 320 {
 321         phys_addr_t p_lli = virt_to_phys(lli);
 322
 323         dev_dbg(chan2dev(&vchan->vc.chan),
 324                 "\n\tdesc:   p - %pa v - 0x%p\n"
 325                 "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
 326                 "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
 327                 &p_lli, lli,
 328                 lli->cfg, lli->src, lli->dst,
 329                 lli->len, lli->para, lli->p_lli_next);
 330 }
 331
 332 static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
 333 {
 334         struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
 335         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
 336         struct sun6i_dma_lli *v_lli, *v_next;
 337         dma_addr_t p_lli, p_next;
 338
 339         if (unlikely(!txd))
 340                 return;
 341
 342         p_lli = txd->p_lli;
 343         v_lli = txd->v_lli;
 344
 345         while (v_lli) {
 346                 v_next = v_lli->v_lli_next;
 347                 p_next = v_lli->p_lli_next;
 348
 349                 dma_pool_free(sdev->pool, v_lli, p_lli);
 350
 351                 v_lli = v_next;
 352                 p_lli = p_next;
 353         }
 354
 355         kfree(txd);
 356 }
 357
 358 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
 359 {
 360         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
 361         struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
 362         struct sun6i_pchan *pchan = vchan->phy;
 363         u32 irq_val, irq_reg, irq_offset;
 364
 365         if (!pchan)
 366                 return -EAGAIN;
 367
 368         if (!desc) {
 369                 pchan->desc = NULL;
 370                 pchan->done = NULL;
 371                 return -EAGAIN;
 372         }
 373
 374         list_del(&desc->node);
 375
 376         pchan->desc = to_sun6i_desc(&desc->tx);
 377         pchan->done = NULL;
 378
 379         sun6i_dma_dump_lli(vchan, pchan->desc->v_lli);
 380
 381         irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
 382         irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
 383
 384         irq_val = readl(sdev->base + DMA_IRQ_EN(irq_offset));
 385         irq_val |= DMA_IRQ_QUEUE << (irq_offset * DMA_IRQ_CHAN_WIDTH);
 386         writel(irq_val, sdev->base + DMA_IRQ_EN(irq_offset));
 387
 388         writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
 389         writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
 390
 391         sun6i_dma_dump_com_regs(sdev);
 392         sun6i_dma_dump_chan_regs(sdev, pchan);
 393
 394         return 0;
 395 }
 396
 397 static void sun6i_dma_tasklet(unsigned long data)
 398 {
 399         struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data;
 400         const struct sun6i_dma_config *cfg = sdev->cfg;
 401         struct sun6i_vchan *vchan;
 402         struct sun6i_pchan *pchan;
 403         unsigned int pchan_alloc = 0;
 404         unsigned int pchan_idx;
 405
 406         list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
 407                 spin_lock_irq(&vchan->vc.lock);
 408
 409                 pchan = vchan->phy;
 410
 411                 if (pchan && pchan->done) {
 412                         if (sun6i_dma_start_desc(vchan)) {
 413                                 /*
 414                                  * No current txd associated with this channel
 415                                  */
 416                                 dev_dbg(sdev->slave.dev, "pchan %u: free\n",
 417                                         pchan->idx);
 418
 419                                 /* Mark this channel free */
 420                                 vchan->phy = NULL;
 421                                 pchan->vchan = NULL;
 422                         }
 423                 }
 424                 spin_unlock_irq(&vchan->vc.lock);
 425         }
 426
 427         spin_lock_irq(&sdev->lock);
 428         for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) {
 429                 pchan = &sdev->pchans[pchan_idx];
 430
 431                 if (pchan->vchan || list_empty(&sdev->pending))
 432                         continue;
 433
 434                 vchan = list_first_entry(&sdev->pending,
 435                                          struct sun6i_vchan, node);
 436
 437                 /* Remove from pending channels */
 438                 list_del_init(&vchan->node);
 439                 pchan_alloc |= BIT(pchan_idx);
 440
 441                 /* Mark this channel allocated */
 442                 pchan->vchan = vchan;
 443                 vchan->phy = pchan;
 444                 dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
 445                         pchan->idx, &vchan->vc);
 446         }
 447         spin_unlock_irq(&sdev->lock);
 448
 449         for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) {
 450                 if (!(pchan_alloc & BIT(pchan_idx)))
 451                         continue;
 452
 453                 pchan = sdev->pchans + pchan_idx;
 454                 vchan = pchan->vchan;
 455                 if (vchan) {
 456                         spin_lock_irq(&vchan->vc.lock);
 457                         sun6i_dma_start_desc(vchan);
 458                         spin_unlock_irq(&vchan->vc.lock);
 459                 }
 460         }
 461 }
 462
 463 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
 464 {
 465         struct sun6i_dma_dev *sdev = dev_id;
 466         struct sun6i_vchan *vchan;
 467         struct sun6i_pchan *pchan;
 468         int i, j, ret = IRQ_NONE;
 469         u32 status;
 470
 471         for (i = 0; i < sdev->cfg->nr_max_channels / DMA_IRQ_CHAN_NR; i++) {
 472                 status = readl(sdev->base + DMA_IRQ_STAT(i));
 473                 if (!status)
 474                         continue;
 475
 476                 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
 477                         i ? "high" : "low", status);
 478
 479                 writel(status, sdev->base + DMA_IRQ_STAT(i));
 480
 481                 for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
 482                         if (status & DMA_IRQ_QUEUE) {
 483                                 pchan = sdev->pchans + j;
 484                                 vchan = pchan->vchan;
 485
 486                                 if (vchan) {
 487                                         spin_lock(&vchan->vc.lock);
 488                                         vchan_cookie_complete(&pchan->desc->vd);
 489                                         pchan->done = pchan->desc;
 490                                         spin_unlock(&vchan->vc.lock);
 491                                 }
 492                         }
 493
 494                         status = status >> DMA_IRQ_CHAN_WIDTH;
 495                 }
 496
 497                 if (!atomic_read(&sdev->tasklet_shutdown))
 498                         tasklet_schedule(&sdev->task);
 499                 ret = IRQ_HANDLED;
 500         }
 501
 502         return ret;
 503 }
 504
 505 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
 506                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 507                 size_t len, unsigned long flags)
 508 {
 509         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 510         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 511         struct sun6i_dma_lli *v_lli;
 512         struct sun6i_desc *txd;
 513         dma_addr_t p_lli;
 514         s8 burst, width;
 515
 516         dev_dbg(chan2dev(chan),
 517                 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
 518                 __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
 519
 520         if (!len)
 521                 return NULL;
 522
 523         txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
 524         if (!txd)
 525                 return NULL;
 526
 527         v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
 528         if (!v_lli) {
 529                 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
 530                 goto err_txd_free;
 531         }
 532
 533         v_lli->src = src;
 534         v_lli->dst = dest;
 535         v_lli->len = len;
 536         v_lli->para = NORMAL_WAIT;
 537
 538         burst = convert_burst(8);
 539         width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
 540         v_lli->cfg |= DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
 541                 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
 542                 DMA_CHAN_CFG_DST_LINEAR_MODE |
 543                 DMA_CHAN_CFG_SRC_LINEAR_MODE |
 544                 DMA_CHAN_CFG_SRC_BURST(burst) |
 545                 DMA_CHAN_CFG_SRC_WIDTH(width) |
 546                 DMA_CHAN_CFG_DST_BURST(burst) |
 547                 DMA_CHAN_CFG_DST_WIDTH(width);
 548
 549         sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
 550
 551         sun6i_dma_dump_lli(vchan, v_lli);
 552
 553         return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
 554
 555 err_txd_free:
 556         kfree(txd);
 557         return NULL;
 558 }
 559
 560 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
 561                 struct dma_chan *chan, struct scatterlist *sgl,
 562                 unsigned int sg_len, enum dma_transfer_direction dir,
 563                 unsigned long flags, void *context)
 564 {
 565         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 566         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 567         struct dma_slave_config *sconfig = &vchan->cfg;
 568         struct sun6i_dma_lli *v_lli, *prev = NULL;
 569         struct sun6i_desc *txd;
 570         struct scatterlist *sg;
 571         dma_addr_t p_lli;
 572         int i, ret;
 573
 574         if (!sgl)
 575                 return NULL;
 576
 577         if (!is_slave_direction(dir)) {
 578                 dev_err(chan2dev(chan), "Invalid DMA direction\n");
 579                 return NULL;
 580         }
 581
 582         txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
 583         if (!txd)
 584                 return NULL;
 585
 586         for_each_sg(sgl, sg, sg_len, i) {
 587                 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli);
 588                 if (!v_lli)
 589                         goto err_lli_free;
 590
 591                 if (dir == DMA_MEM_TO_DEV) {
 592                         ret = sun6i_dma_cfg_lli(v_lli, sg_dma_address(sg),
 593                                                 sconfig->dst_addr, sg_dma_len(sg),
 594                                                 sconfig);
 595                         if (ret)
 596                                 goto err_cur_lli_free;
 597
 598                         v_lli->cfg |= DMA_CHAN_CFG_DST_IO_MODE |
 599                                 DMA_CHAN_CFG_SRC_LINEAR_MODE |
 600                                 DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
 601                                 DMA_CHAN_CFG_DST_DRQ(vchan->port);
 602
 603                         dev_dbg(chan2dev(chan),
 604                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
 605                                 __func__, vchan->vc.chan.chan_id,
 606                                 &sconfig->dst_addr, &sg_dma_address(sg),
 607                                 sg_dma_len(sg), flags);
 608
 609                 } else {
 610                         ret = sun6i_dma_cfg_lli(v_lli, sconfig->src_addr,
 611                                                 sg_dma_address(sg), sg_dma_len(sg),
 612                                                 sconfig);
 613                         if (ret)
 614                                 goto err_cur_lli_free;
 615
 616                         v_lli->cfg |= DMA_CHAN_CFG_DST_LINEAR_MODE |
 617                                 DMA_CHAN_CFG_SRC_IO_MODE |
 618                                 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
 619                                 DMA_CHAN_CFG_SRC_DRQ(vchan->port);
 620
 621                         dev_dbg(chan2dev(chan),
 622                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
 623                                 __func__, vchan->vc.chan.chan_id,
 624                                 &sg_dma_address(sg), &sconfig->src_addr,
 625                                 sg_dma_len(sg), flags);
 626                 }
 627
 628                 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
 629         }
 630
 631         dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
 632         for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
 633                 sun6i_dma_dump_lli(vchan, prev);
 634
 635         return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
 636
 637 err_cur_lli_free:
 638         dma_pool_free(sdev->pool, v_lli, p_lli);
 639 err_lli_free:
 640         for (prev = txd->v_lli; prev; prev = prev->v_lli_next)
 641                 dma_pool_free(sdev->pool, prev, virt_to_phys(prev));
 642         kfree(txd);
 643         return NULL;
 644 }
 645
 646 static int sun6i_dma_config(struct dma_chan *chan,
 647                             struct dma_slave_config *config)
 648 {
 649         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 650
 651         memcpy(&vchan->cfg, config, sizeof(*config));
 652
 653         return 0;
 654 }
 655
 656 static int sun6i_dma_pause(struct dma_chan *chan)
 657 {
 658         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 659         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 660         struct sun6i_pchan *pchan = vchan->phy;
 661
 662         dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
 663
 664         if (pchan) {
 665                 writel(DMA_CHAN_PAUSE_PAUSE,
 666                        pchan->base + DMA_CHAN_PAUSE);
 667         } else {
 668                 spin_lock(&sdev->lock);
 669                 list_del_init(&vchan->node);
 670                 spin_unlock(&sdev->lock);
 671         }
 672
 673         return 0;
 674 }
 675
 676 static int sun6i_dma_resume(struct dma_chan *chan)
 677 {
 678         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 679         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 680         struct sun6i_pchan *pchan = vchan->phy;
 681         unsigned long flags;
 682
 683         dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
 684
 685         spin_lock_irqsave(&vchan->vc.lock, flags);
 686
 687         if (pchan) {
 688                 writel(DMA_CHAN_PAUSE_RESUME,
 689                        pchan->base + DMA_CHAN_PAUSE);
 690         } else if (!list_empty(&vchan->vc.desc_issued)) {
 691                 spin_lock(&sdev->lock);
 692                 list_add_tail(&vchan->node, &sdev->pending);
 693                 spin_unlock(&sdev->lock);
 694         }
 695
 696         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 697
 698         return 0;
 699 }
 700
 701 static int sun6i_dma_terminate_all(struct dma_chan *chan)
 702 {
 703         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 704         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 705         struct sun6i_pchan *pchan = vchan->phy;
 706         unsigned long flags;
 707         LIST_HEAD(head);
 708
 709         spin_lock(&sdev->lock);
 710         list_del_init(&vchan->node);
 711         spin_unlock(&sdev->lock);
 712
 713         spin_lock_irqsave(&vchan->vc.lock, flags);
 714
 715         vchan_get_all_descriptors(&vchan->vc, &head);
 716
 717         if (pchan) {
 718                 writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
 719                 writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
 720
 721                 vchan->phy = NULL;
 722                 pchan->vchan = NULL;
 723                 pchan->desc = NULL;
 724                 pchan->done = NULL;
 725         }
 726
 727         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 728
 729         vchan_dma_desc_free_list(&vchan->vc, &head);
 730
 731         return 0;
 732 }
 733
 734 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
 735                                            dma_cookie_t cookie,
 736                                            struct dma_tx_state *state)
 737 {
 738         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 739         struct sun6i_pchan *pchan = vchan->phy;
 740         struct sun6i_dma_lli *lli;
 741         struct virt_dma_desc *vd;
 742         struct sun6i_desc *txd;
 743         enum dma_status ret;
 744         unsigned long flags;
 745         size_t bytes = 0;
 746
 747         ret = dma_cookie_status(chan, cookie, state);
 748         if (ret == DMA_COMPLETE)
 749                 return ret;
 750
 751         spin_lock_irqsave(&vchan->vc.lock, flags);
 752
 753         vd = vchan_find_desc(&vchan->vc, cookie);
 754         txd = to_sun6i_desc(&vd->tx);
 755
 756         if (vd) {
 757                 for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
 758                         bytes += lli->len;
 759         } else if (!pchan || !pchan->desc) {
 760                 bytes = 0;
 761         } else {
 762                 bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
 763         }
 764
 765         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 766
 767         dma_set_residue(state, bytes);
 768
 769         return ret;
 770 }
 771
 772 static void sun6i_dma_issue_pending(struct dma_chan *chan)
 773 {
 774         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 775         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 776         unsigned long flags;
 777
 778         spin_lock_irqsave(&vchan->vc.lock, flags);
 779
 780         if (vchan_issue_pending(&vchan->vc)) {
 781                 spin_lock(&sdev->lock);
 782
 783                 if (!vchan->phy && list_empty(&vchan->node)) {
 784                         list_add_tail(&vchan->node, &sdev->pending);
 785                         tasklet_schedule(&sdev->task);
 786                         dev_dbg(chan2dev(chan), "vchan %p: issued\n",
 787                                 &vchan->vc);
 788                 }
 789
 790                 spin_unlock(&sdev->lock);
 791         } else {
 792                 dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
 793                         &vchan->vc);
 794         }
 795
 796         spin_unlock_irqrestore(&vchan->vc.lock, flags);
 797 }
 798
 799 static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
 800 {
 801         struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
 802         struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
 803         unsigned long flags;
 804
 805         spin_lock_irqsave(&sdev->lock, flags);
 806         list_del_init(&vchan->node);
 807         spin_unlock_irqrestore(&sdev->lock, flags);
 808
 809         vchan_free_chan_resources(&vchan->vc);
 810 }
 811
 812 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
 813                                            struct of_dma *ofdma)
 814 {
 815         struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
 816         struct sun6i_vchan *vchan;
 817         struct dma_chan *chan;
 818         u8 port = dma_spec->args[0];
 819
 820         if (port > sdev->cfg->nr_max_requests)
 821                 return NULL;
 822
 823         chan = dma_get_any_slave_channel(&sdev->slave);
 824         if (!chan)
 825                 return NULL;
 826
 827         vchan = to_sun6i_vchan(chan);
 828         vchan->port = port;
 829
 830         return chan;
 831 }
 832
 833 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
 834 {
 835         /* Disable all interrupts from DMA */
 836         writel(0, sdev->base + DMA_IRQ_EN(0));
 837         writel(0, sdev->base + DMA_IRQ_EN(1));
 838
 839         /* Prevent spurious interrupts from scheduling the tasklet */
 840         atomic_inc(&sdev->tasklet_shutdown);
 841
 842         /* Make sure we won't have any further interrupts */
 843         devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
 844
 845         /* Actually prevent the tasklet from being scheduled */
 846         tasklet_kill(&sdev->task);
 847 }
 848
 849 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
 850 {
 851         int i;
 852
 853         for (i = 0; i < sdev->cfg->nr_max_vchans; i++) {
 854                 struct sun6i_vchan *vchan = &sdev->vchans[i];
 855
 856                 list_del(&vchan->vc.chan.device_node);
 857                 tasklet_kill(&vchan->vc.task);
 858         }
 859 }
 860
 861 /*
 862  * For A31:
 863  *
 864  * There's 16 physical channels that can work in parallel.
 865  *
 866  * However we have 30 different endpoints for our requests.
 867  *
 868  * Since the channels are able to handle only an unidirectional
 869  * transfer, we need to allocate more virtual channels so that
 870  * everyone can grab one channel.
 871  *
 872  * Some devices can't work in both direction (mostly because it
 873  * wouldn't make sense), so we have a bit fewer virtual channels than
 874  * 2 channels per endpoints.
 875  */
 876
 877 static struct sun6i_dma_config sun6i_a31_dma_cfg = {
 878         .nr_max_channels = 16,
 879         .nr_max_requests = 30,
 880         .nr_max_vchans   = 53,
 881 };
 882
 883 /*
 884  * The A23 only has 8 physical channels, a maximum DRQ port id of 24,
 885  * and a total of 37 usable source and destination endpoints.
 886  */
 887
 888 static struct sun6i_dma_config sun8i_a23_dma_cfg = {
 889         .nr_max_channels = 8,
 890         .nr_max_requests = 24,
 891         .nr_max_vchans   = 37,
 892 };
 893
 894 /*
 895  * The H3 has 12 physical channels, a maximum DRQ port id of 27,
 896  * and a total of 34 usable source and destination endpoints.
 897  */
 898
 899 static struct sun6i_dma_config sun8i_h3_dma_cfg = {
 900         .nr_max_channels = 12,
 901         .nr_max_requests = 27,
 902         .nr_max_vchans   = 34,
 903 };
 904
 905 static const struct of_device_id sun6i_dma_match[] = {
 906         { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
 907         { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
 908         { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
 909         { /* sentinel */ }
 910 };
 911 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
 912
 913 static int sun6i_dma_probe(struct platform_device *pdev)
 914 {
 915         const struct of_device_id *device;
 916         struct sun6i_dma_dev *sdc;
 917         struct resource *res;
 918         int ret, i;
 919
 920         sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
 921         if (!sdc)
 922                 return -ENOMEM;
 923
 924         device = of_match_device(sun6i_dma_match, &pdev->dev);
 925         if (!device)
 926                 return -ENODEV;
 927         sdc->cfg = device->data;
 928
 929         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 930         sdc->base = devm_ioremap_resource(&pdev->dev, res);
 931         if (IS_ERR(sdc->base))
 932                 return PTR_ERR(sdc->base);
 933
 934         sdc->irq = platform_get_irq(pdev, 0);
 935         if (sdc->irq < 0) {
 936                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 937                 return sdc->irq;
 938         }
 939
 940         sdc->clk = devm_clk_get(&pdev->dev, NULL);
 941         if (IS_ERR(sdc->clk)) {
 942                 dev_err(&pdev->dev, "No clock specified\n");
 943                 return PTR_ERR(sdc->clk);
 944         }
 945
 946         sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
 947         if (IS_ERR(sdc->rstc)) {
 948                 dev_err(&pdev->dev, "No reset controller specified\n");
 949                 return PTR_ERR(sdc->rstc);
 950         }
 951
 952         sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
 953                                      sizeof(struct sun6i_dma_lli), 4, 0);
 954         if (!sdc->pool) {
 955                 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
 956                 return -ENOMEM;
 957         }
 958
 959         platform_set_drvdata(pdev, sdc);
 960         INIT_LIST_HEAD(&sdc->pending);
 961         spin_lock_init(&sdc->lock);
 962
 963         dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
 964         dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
 965         dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
 966
 967         INIT_LIST_HEAD(&sdc->slave.channels);
 968         sdc->slave.device_free_chan_resources   = sun6i_dma_free_chan_resources;
 969         sdc->slave.device_tx_status             = sun6i_dma_tx_status;
 970         sdc->slave.device_issue_pending         = sun6i_dma_issue_pending;
 971         sdc->slave.device_prep_slave_sg         = sun6i_dma_prep_slave_sg;
 972         sdc->slave.device_prep_dma_memcpy       = sun6i_dma_prep_dma_memcpy;
 973         sdc->slave.copy_align                   = DMAENGINE_ALIGN_4_BYTES;
 974         sdc->slave.device_config                = sun6i_dma_config;
 975         sdc->slave.device_pause                 = sun6i_dma_pause;
 976         sdc->slave.device_resume                = sun6i_dma_resume;
 977         sdc->slave.device_terminate_all         = sun6i_dma_terminate_all;
 978         sdc->slave.src_addr_widths              = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
 979                                                   BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
 980                                                   BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 981         sdc->slave.dst_addr_widths              = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
 982                                                   BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
 983                                                   BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 984         sdc->slave.directions                   = BIT(DMA_DEV_TO_MEM) |
 985                                                   BIT(DMA_MEM_TO_DEV);
 986         sdc->slave.residue_granularity          = DMA_RESIDUE_GRANULARITY_BURST;
 987         sdc->slave.dev = &pdev->dev;
 988
 989         sdc->pchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_channels,
 990                                    sizeof(struct sun6i_pchan), GFP_KERNEL);
 991         if (!sdc->pchans)
 992                 return -ENOMEM;
 993
 994         sdc->vchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_vchans,
 995                                    sizeof(struct sun6i_vchan), GFP_KERNEL);
 996         if (!sdc->vchans)
 997                 return -ENOMEM;
 998
 999         tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc);
1000
1001         for (i = 0; i < sdc->cfg->nr_max_channels; i++) {
1002                 struct sun6i_pchan *pchan = &sdc->pchans[i];
1003
1004                 pchan->idx = i;
1005                 pchan->base = sdc->base + 0x100 + i * 0x40;
1006         }
1007
1008         for (i = 0; i < sdc->cfg->nr_max_vchans; i++) {
1009                 struct sun6i_vchan *vchan = &sdc->vchans[i];
1010
1011                 INIT_LIST_HEAD(&vchan->node);
1012                 vchan->vc.desc_free = sun6i_dma_free_desc;
1013                 vchan_init(&vchan->vc, &sdc->slave);
1014         }
1015
1016         ret = reset_control_deassert(sdc->rstc);
1017         if (ret) {
1018                 dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
1019                 goto err_chan_free;
1020         }
1021
1022         ret = clk_prepare_enable(sdc->clk);
1023         if (ret) {
1024                 dev_err(&pdev->dev, "Couldn't enable the clock\n");
1025                 goto err_reset_assert;
1026         }
1027
1028         ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
1029                                dev_name(&pdev->dev), sdc);
1030         if (ret) {
1031                 dev_err(&pdev->dev, "Cannot request IRQ\n");
1032                 goto err_clk_disable;
1033         }
1034
1035         ret = dma_async_device_register(&sdc->slave);
1036         if (ret) {
1037                 dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
1038                 goto err_irq_disable;
1039         }
1040
1041         ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
1042                                          sdc);
1043         if (ret) {
1044                 dev_err(&pdev->dev, "of_dma_controller_register failed\n");
1045                 goto err_dma_unregister;
1046         }
1047
1048         /*
1049          * sun8i variant requires us to toggle a dma gating register,
1050          * as seen in Allwinner's SDK. This register is not documented
1051          * in the A23 user manual.
1052          */
1053         if (of_device_is_compatible(pdev->dev.of_node,
1054                                     "allwinner,sun8i-a23-dma"))
1055                 writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);
1056
1057         return 0;
1058
1059 err_dma_unregister:
1060         dma_async_device_unregister(&sdc->slave);
1061 err_irq_disable:
1062         sun6i_kill_tasklet(sdc);
1063 err_clk_disable:
1064         clk_disable_unprepare(sdc->clk);
1065 err_reset_assert:
1066         reset_control_assert(sdc->rstc);
1067 err_chan_free:
1068         sun6i_dma_free(sdc);
1069         return ret;
1070 }
1071
1072 static int sun6i_dma_remove(struct platform_device *pdev)
1073 {
1074         struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
1075
1076         of_dma_controller_free(pdev->dev.of_node);
1077         dma_async_device_unregister(&sdc->slave);
1078
1079         sun6i_kill_tasklet(sdc);
1080
1081         clk_disable_unprepare(sdc->clk);
1082         reset_control_assert(sdc->rstc);
1083
1084         sun6i_dma_free(sdc);
1085
1086         return 0;
1087 }
1088
1089 static struct platform_driver sun6i_dma_driver = {
1090         .probe          = sun6i_dma_probe,
1091         .remove         = sun6i_dma_remove,
1092         .driver = {
1093                 .name           = "sun6i-dma",
1094                 .of_match_table = sun6i_dma_match,
1095         },
1096 };
1097 module_platform_driver(sun6i_dma_driver);
1098
1099 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
1100 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
1101 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1102 MODULE_LICENSE("GPL");