drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_legacy_encoder.c */
  41 extern void
  42 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  43                           uint32_t supported_device);
  44
  45 /* old legacy ATI BIOS routines */
  46
  47 /* COMBIOS table offsets */
  48 enum radeon_combios_table_offset {
  49         /* absolute offset tables */
  50         COMBIOS_ASIC_INIT_1_TABLE,
  51         COMBIOS_BIOS_SUPPORT_TABLE,
  52         COMBIOS_DAC_PROGRAMMING_TABLE,
  53         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  54         COMBIOS_CRTC_INFO_TABLE,
  55         COMBIOS_PLL_INFO_TABLE,
  56         COMBIOS_TV_INFO_TABLE,
  57         COMBIOS_DFP_INFO_TABLE,
  58         COMBIOS_HW_CONFIG_INFO_TABLE,
  59         COMBIOS_MULTIMEDIA_INFO_TABLE,
  60         COMBIOS_TV_STD_PATCH_TABLE,
  61         COMBIOS_LCD_INFO_TABLE,
  62         COMBIOS_MOBILE_INFO_TABLE,
  63         COMBIOS_PLL_INIT_TABLE,
  64         COMBIOS_MEM_CONFIG_TABLE,
  65         COMBIOS_SAVE_MASK_TABLE,
  66         COMBIOS_HARDCODED_EDID_TABLE,
  67         COMBIOS_ASIC_INIT_2_TABLE,
  68         COMBIOS_CONNECTOR_INFO_TABLE,
  69         COMBIOS_DYN_CLK_1_TABLE,
  70         COMBIOS_RESERVED_MEM_TABLE,
  71         COMBIOS_EXT_TMDS_INFO_TABLE,
  72         COMBIOS_MEM_CLK_INFO_TABLE,
  73         COMBIOS_EXT_DAC_INFO_TABLE,
  74         COMBIOS_MISC_INFO_TABLE,
  75         COMBIOS_CRT_INFO_TABLE,
  76         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  77         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  78         COMBIOS_FAN_SPEED_INFO_TABLE,
  79         COMBIOS_OVERDRIVE_INFO_TABLE,
  80         COMBIOS_OEM_INFO_TABLE,
  81         COMBIOS_DYN_CLK_2_TABLE,
  82         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  83         COMBIOS_I2C_INFO_TABLE,
  84         /* relative offset tables */
  85         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
  86         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
  87         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
  88         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
  89         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
  90         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
  91         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
  92         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
  93         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
  94         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
  95         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
  96 };
  97
  98 enum radeon_combios_ddc {
  99         DDC_NONE_DETECTED,
 100         DDC_MONID,
 101         DDC_DVI,
 102         DDC_VGA,
 103         DDC_CRT2,
 104         DDC_LCD,
 105         DDC_GPIO,
 106 };
 107
 108 enum radeon_combios_connector {
 109         CONNECTOR_NONE_LEGACY,
 110         CONNECTOR_PROPRIETARY_LEGACY,
 111         CONNECTOR_CRT_LEGACY,
 112         CONNECTOR_DVI_I_LEGACY,
 113         CONNECTOR_DVI_D_LEGACY,
 114         CONNECTOR_CTV_LEGACY,
 115         CONNECTOR_STV_LEGACY,
 116         CONNECTOR_UNSUPPORTED_LEGACY
 117 };
 118
 119 static const int legacy_connector_convert[] = {
 120         DRM_MODE_CONNECTOR_Unknown,
 121         DRM_MODE_CONNECTOR_DVID,
 122         DRM_MODE_CONNECTOR_VGA,
 123         DRM_MODE_CONNECTOR_DVII,
 124         DRM_MODE_CONNECTOR_DVID,
 125         DRM_MODE_CONNECTOR_Composite,
 126         DRM_MODE_CONNECTOR_SVIDEO,
 127         DRM_MODE_CONNECTOR_Unknown,
 128 };
 129
 130 static uint16_t combios_get_table_offset(struct drm_device *dev,
 131                                          enum radeon_combios_table_offset table)
 132 {
 133         struct radeon_device *rdev = dev->dev_private;
 134         int rev, size;
 135         uint16_t offset = 0, check_offset;
 136
 137         if (!rdev->bios)
 138                 return 0;
 139
 140         switch (table) {
 141                 /* absolute offset tables */
 142         case COMBIOS_ASIC_INIT_1_TABLE:
 143                 check_offset = 0xc;
 144                 break;
 145         case COMBIOS_BIOS_SUPPORT_TABLE:
 146                 check_offset = 0x14;
 147                 break;
 148         case COMBIOS_DAC_PROGRAMMING_TABLE:
 149                 check_offset = 0x2a;
 150                 break;
 151         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 152                 check_offset = 0x2c;
 153                 break;
 154         case COMBIOS_CRTC_INFO_TABLE:
 155                 check_offset = 0x2e;
 156                 break;
 157         case COMBIOS_PLL_INFO_TABLE:
 158                 check_offset = 0x30;
 159                 break;
 160         case COMBIOS_TV_INFO_TABLE:
 161                 check_offset = 0x32;
 162                 break;
 163         case COMBIOS_DFP_INFO_TABLE:
 164                 check_offset = 0x34;
 165                 break;
 166         case COMBIOS_HW_CONFIG_INFO_TABLE:
 167                 check_offset = 0x36;
 168                 break;
 169         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 170                 check_offset = 0x38;
 171                 break;
 172         case COMBIOS_TV_STD_PATCH_TABLE:
 173                 check_offset = 0x3e;
 174                 break;
 175         case COMBIOS_LCD_INFO_TABLE:
 176                 check_offset = 0x40;
 177                 break;
 178         case COMBIOS_MOBILE_INFO_TABLE:
 179                 check_offset = 0x42;
 180                 break;
 181         case COMBIOS_PLL_INIT_TABLE:
 182                 check_offset = 0x46;
 183                 break;
 184         case COMBIOS_MEM_CONFIG_TABLE:
 185                 check_offset = 0x48;
 186                 break;
 187         case COMBIOS_SAVE_MASK_TABLE:
 188                 check_offset = 0x4a;
 189                 break;
 190         case COMBIOS_HARDCODED_EDID_TABLE:
 191                 check_offset = 0x4c;
 192                 break;
 193         case COMBIOS_ASIC_INIT_2_TABLE:
 194                 check_offset = 0x4e;
 195                 break;
 196         case COMBIOS_CONNECTOR_INFO_TABLE:
 197                 check_offset = 0x50;
 198                 break;
 199         case COMBIOS_DYN_CLK_1_TABLE:
 200                 check_offset = 0x52;
 201                 break;
 202         case COMBIOS_RESERVED_MEM_TABLE:
 203                 check_offset = 0x54;
 204                 break;
 205         case COMBIOS_EXT_TMDS_INFO_TABLE:
 206                 check_offset = 0x58;
 207                 break;
 208         case COMBIOS_MEM_CLK_INFO_TABLE:
 209                 check_offset = 0x5a;
 210                 break;
 211         case COMBIOS_EXT_DAC_INFO_TABLE:
 212                 check_offset = 0x5c;
 213                 break;
 214         case COMBIOS_MISC_INFO_TABLE:
 215                 check_offset = 0x5e;
 216                 break;
 217         case COMBIOS_CRT_INFO_TABLE:
 218                 check_offset = 0x60;
 219                 break;
 220         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 221                 check_offset = 0x62;
 222                 break;
 223         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 224                 check_offset = 0x64;
 225                 break;
 226         case COMBIOS_FAN_SPEED_INFO_TABLE:
 227                 check_offset = 0x66;
 228                 break;
 229         case COMBIOS_OVERDRIVE_INFO_TABLE:
 230                 check_offset = 0x68;
 231                 break;
 232         case COMBIOS_OEM_INFO_TABLE:
 233                 check_offset = 0x6a;
 234                 break;
 235         case COMBIOS_DYN_CLK_2_TABLE:
 236                 check_offset = 0x6c;
 237                 break;
 238         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 239                 check_offset = 0x6e;
 240                 break;
 241         case COMBIOS_I2C_INFO_TABLE:
 242                 check_offset = 0x70;
 243                 break;
 244                 /* relative offset tables */
 245         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 246                 check_offset =
 247                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 248                 if (check_offset) {
 249                         rev = RBIOS8(check_offset);
 250                         if (rev > 0) {
 251                                 check_offset = RBIOS16(check_offset + 0x3);
 252                                 if (check_offset)
 253                                         offset = check_offset;
 254                         }
 255                 }
 256                 break;
 257         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 258                 check_offset =
 259                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 260                 if (check_offset) {
 261                         rev = RBIOS8(check_offset);
 262                         if (rev > 0) {
 263                                 check_offset = RBIOS16(check_offset + 0x5);
 264                                 if (check_offset)
 265                                         offset = check_offset;
 266                         }
 267                 }
 268                 break;
 269         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 270                 check_offset =
 271                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 272                 if (check_offset) {
 273                         rev = RBIOS8(check_offset);
 274                         if (rev > 0) {
 275                                 check_offset = RBIOS16(check_offset + 0x7);
 276                                 if (check_offset)
 277                                         offset = check_offset;
 278                         }
 279                 }
 280                 break;
 281         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 282                 check_offset =
 283                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 284                 if (check_offset) {
 285                         rev = RBIOS8(check_offset);
 286                         if (rev == 2) {
 287                                 check_offset = RBIOS16(check_offset + 0x9);
 288                                 if (check_offset)
 289                                         offset = check_offset;
 290                         }
 291                 }
 292                 break;
 293         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 294                 check_offset =
 295                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 296                 if (check_offset) {
 297                         while (RBIOS8(check_offset++));
 298                         check_offset += 2;
 299                         if (check_offset)
 300                                 offset = check_offset;
 301                 }
 302                 break;
 303         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 304                 check_offset =
 305                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 306                 if (check_offset) {
 307                         check_offset = RBIOS16(check_offset + 0x11);
 308                         if (check_offset)
 309                                 offset = check_offset;
 310                 }
 311                 break;
 312         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 313                 check_offset =
 314                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 315                 if (check_offset) {
 316                         check_offset = RBIOS16(check_offset + 0x13);
 317                         if (check_offset)
 318                                 offset = check_offset;
 319                 }
 320                 break;
 321         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 322                 check_offset =
 323                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 324                 if (check_offset) {
 325                         check_offset = RBIOS16(check_offset + 0x15);
 326                         if (check_offset)
 327                                 offset = check_offset;
 328                 }
 329                 break;
 330         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 331                 check_offset =
 332                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 333                 if (check_offset) {
 334                         check_offset = RBIOS16(check_offset + 0x17);
 335                         if (check_offset)
 336                                 offset = check_offset;
 337                 }
 338                 break;
 339         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 340                 check_offset =
 341                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 342                 if (check_offset) {
 343                         check_offset = RBIOS16(check_offset + 0x2);
 344                         if (check_offset)
 345                                 offset = check_offset;
 346                 }
 347                 break;
 348         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 349                 check_offset =
 350                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 351                 if (check_offset) {
 352                         check_offset = RBIOS16(check_offset + 0x4);
 353                         if (check_offset)
 354                                 offset = check_offset;
 355                 }
 356                 break;
 357         default:
 358                 check_offset = 0;
 359                 break;
 360         }
 361
 362         size = RBIOS8(rdev->bios_header_start + 0x6);
 363         /* check absolute offset tables */
 364         if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
 365                 offset = RBIOS16(rdev->bios_header_start + check_offset);
 366
 367         return offset;
 368 }
 369
 370 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 371 {
 372         int edid_info, size;
 373         struct edid *edid;
 374         unsigned char *raw;
 375         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 376         if (!edid_info)
 377                 return false;
 378
 379         raw = rdev->bios + edid_info;
 380         size = EDID_LENGTH * (raw[0x7e] + 1);
 381         edid = kmalloc(size, GFP_KERNEL);
 382         if (edid == NULL)
 383                 return false;
 384
 385         memcpy((unsigned char *)edid, raw, size);
 386
 387         if (!drm_edid_is_valid(edid)) {
 388                 kfree(edid);
 389                 return false;
 390         }
 391
 392         rdev->mode_info.bios_hardcoded_edid = edid;
 393         rdev->mode_info.bios_hardcoded_edid_size = size;
 394         return true;
 395 }
 396
 397 /* this is used for atom LCDs as well */
 398 struct edid *
 399 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 400 {
 401         struct edid *edid;
 402
 403         if (rdev->mode_info.bios_hardcoded_edid) {
 404                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 405                 if (edid) {
 406                         memcpy((unsigned char *)edid,
 407                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 408                                rdev->mode_info.bios_hardcoded_edid_size);
 409                         return edid;
 410                 }
 411         }
 412         return NULL;
 413 }
 414
 415 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 416                                                        enum radeon_combios_ddc ddc,
 417                                                        u32 clk_mask,
 418                                                        u32 data_mask)
 419 {
 420         struct radeon_i2c_bus_rec i2c;
 421         int ddc_line = 0;
 422
 423         /* ddc id            = mask reg
 424          * DDC_NONE_DETECTED = none
 425          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 426          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 427          * DDC_LCD           = RADEON_GPIOPAD_MASK
 428          * DDC_GPIO          = RADEON_MDGPIO_MASK
 429          * r1xx
 430          * DDC_MONID         = RADEON_GPIO_MONID
 431          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 432          * r200
 433          * DDC_MONID         = RADEON_GPIO_MONID
 434          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 435          * r300/r350
 436          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 437          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 438          * rv2xx/rv3xx
 439          * DDC_MONID         = RADEON_GPIO_MONID
 440          * DDC_CRT2          = RADEON_GPIO_MONID
 441          * rs3xx/rs4xx
 442          * DDC_MONID         = RADEON_GPIOPAD_MASK
 443          * DDC_CRT2          = RADEON_GPIO_MONID
 444          */
 445         switch (ddc) {
 446         case DDC_NONE_DETECTED:
 447         default:
 448                 ddc_line = 0;
 449                 break;
 450         case DDC_DVI:
 451                 ddc_line = RADEON_GPIO_DVI_DDC;
 452                 break;
 453         case DDC_VGA:
 454                 ddc_line = RADEON_GPIO_VGA_DDC;
 455                 break;
 456         case DDC_LCD:
 457                 ddc_line = RADEON_GPIOPAD_MASK;
 458                 break;
 459         case DDC_GPIO:
 460                 ddc_line = RADEON_MDGPIO_MASK;
 461                 break;
 462         case DDC_MONID:
 463                 if (rdev->family == CHIP_RS300 ||
 464                     rdev->family == CHIP_RS400 ||
 465                     rdev->family == CHIP_RS480)
 466                         ddc_line = RADEON_GPIOPAD_MASK;
 467                 else if (rdev->family == CHIP_R300 ||
 468                          rdev->family == CHIP_R350) {
 469                         ddc_line = RADEON_GPIO_DVI_DDC;
 470                         ddc = DDC_DVI;
 471                 } else
 472                         ddc_line = RADEON_GPIO_MONID;
 473                 break;
 474         case DDC_CRT2:
 475                 if (rdev->family == CHIP_R200 ||
 476                     rdev->family == CHIP_R300 ||
 477                     rdev->family == CHIP_R350) {
 478                         ddc_line = RADEON_GPIO_DVI_DDC;
 479                         ddc = DDC_DVI;
 480                 } else if (rdev->family == CHIP_RS300 ||
 481                            rdev->family == CHIP_RS400 ||
 482                            rdev->family == CHIP_RS480)
 483                         ddc_line = RADEON_GPIO_MONID;
 484                 else if (rdev->family >= CHIP_RV350) {
 485                         ddc_line = RADEON_GPIO_MONID;
 486                         ddc = DDC_MONID;
 487                 } else
 488                         ddc_line = RADEON_GPIO_CRT2_DDC;
 489                 break;
 490         }
 491
 492         if (ddc_line == RADEON_GPIOPAD_MASK) {
 493                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 494                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 495                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 496                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 497                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 498                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 499                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 500                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 501         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 502                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 503                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 504                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 505                 i2c.a_data_reg = RADEON_MDGPIO_A;
 506                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 507                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 508                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 509                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 510         } else {
 511                 i2c.mask_clk_reg = ddc_line;
 512                 i2c.mask_data_reg = ddc_line;
 513                 i2c.a_clk_reg = ddc_line;
 514                 i2c.a_data_reg = ddc_line;
 515                 i2c.en_clk_reg = ddc_line;
 516                 i2c.en_data_reg = ddc_line;
 517                 i2c.y_clk_reg = ddc_line;
 518                 i2c.y_data_reg = ddc_line;
 519         }
 520
 521         if (clk_mask && data_mask) {
 522                 /* system specific masks */
 523                 i2c.mask_clk_mask = clk_mask;
 524                 i2c.mask_data_mask = data_mask;
 525                 i2c.a_clk_mask = clk_mask;
 526                 i2c.a_data_mask = data_mask;
 527                 i2c.en_clk_mask = clk_mask;
 528                 i2c.en_data_mask = data_mask;
 529                 i2c.y_clk_mask = clk_mask;
 530                 i2c.y_data_mask = data_mask;
 531         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 532                    (ddc_line == RADEON_MDGPIO_MASK)) {
 533                 /* default gpiopad masks */
 534                 i2c.mask_clk_mask = (0x20 << 8);
 535                 i2c.mask_data_mask = 0x80;
 536                 i2c.a_clk_mask = (0x20 << 8);
 537                 i2c.a_data_mask = 0x80;
 538                 i2c.en_clk_mask = (0x20 << 8);
 539                 i2c.en_data_mask = 0x80;
 540                 i2c.y_clk_mask = (0x20 << 8);
 541                 i2c.y_data_mask = 0x80;
 542         } else {
 543                 /* default masks for ddc pads */
 544                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 545                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 546                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 547                 i2c.a_data_mask = RADEON_GPIO_A_0;
 548                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 549                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 550                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 551                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 552         }
 553
 554         switch (rdev->family) {
 555         case CHIP_R100:
 556         case CHIP_RV100:
 557         case CHIP_RS100:
 558         case CHIP_RV200:
 559         case CHIP_RS200:
 560         case CHIP_RS300:
 561                 switch (ddc_line) {
 562                 case RADEON_GPIO_DVI_DDC:
 563                         i2c.hw_capable = true;
 564                         break;
 565                 default:
 566                         i2c.hw_capable = false;
 567                         break;
 568                 }
 569                 break;
 570         case CHIP_R200:
 571                 switch (ddc_line) {
 572                 case RADEON_GPIO_DVI_DDC:
 573                 case RADEON_GPIO_MONID:
 574                         i2c.hw_capable = true;
 575                         break;
 576                 default:
 577                         i2c.hw_capable = false;
 578                         break;
 579                 }
 580                 break;
 581         case CHIP_RV250:
 582         case CHIP_RV280:
 583                 switch (ddc_line) {
 584                 case RADEON_GPIO_VGA_DDC:
 585                 case RADEON_GPIO_DVI_DDC:
 586                 case RADEON_GPIO_CRT2_DDC:
 587                         i2c.hw_capable = true;
 588                         break;
 589                 default:
 590                         i2c.hw_capable = false;
 591                         break;
 592                 }
 593                 break;
 594         case CHIP_R300:
 595         case CHIP_R350:
 596                 switch (ddc_line) {
 597                 case RADEON_GPIO_VGA_DDC:
 598                 case RADEON_GPIO_DVI_DDC:
 599                         i2c.hw_capable = true;
 600                         break;
 601                 default:
 602                         i2c.hw_capable = false;
 603                         break;
 604                 }
 605                 break;
 606         case CHIP_RV350:
 607         case CHIP_RV380:
 608         case CHIP_RS400:
 609         case CHIP_RS480:
 610                 switch (ddc_line) {
 611                 case RADEON_GPIO_VGA_DDC:
 612                 case RADEON_GPIO_DVI_DDC:
 613                         i2c.hw_capable = true;
 614                         break;
 615                 case RADEON_GPIO_MONID:
 616                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 617                          * reliably on some pre-r4xx hardware; not sure why.
 618                          */
 619                         i2c.hw_capable = false;
 620                         break;
 621                 default:
 622                         i2c.hw_capable = false;
 623                         break;
 624                 }
 625                 break;
 626         default:
 627                 i2c.hw_capable = false;
 628                 break;
 629         }
 630         i2c.mm_i2c = false;
 631
 632         i2c.i2c_id = ddc;
 633         i2c.hpd = RADEON_HPD_NONE;
 634
 635         if (ddc_line)
 636                 i2c.valid = true;
 637         else
 638                 i2c.valid = false;
 639
 640         return i2c;
 641 }
 642
 643 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
 644 {
 645         struct drm_device *dev = rdev->ddev;
 646         struct radeon_i2c_bus_rec i2c;
 647         u16 offset;
 648         u8 id, blocks, clk, data;
 649         int i;
 650
 651         i2c.valid = false;
 652
 653         offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 654         if (offset) {
 655                 blocks = RBIOS8(offset + 2);
 656                 for (i = 0; i < blocks; i++) {
 657                         id = RBIOS8(offset + 3 + (i * 5) + 0);
 658                         if (id == 136) {
 659                                 clk = RBIOS8(offset + 3 + (i * 5) + 3);
 660                                 data = RBIOS8(offset + 3 + (i * 5) + 4);
 661                                 /* gpiopad */
 662                                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 663                                                             (1 << clk), (1 << data));
 664                                 break;
 665                         }
 666                 }
 667         }
 668         return i2c;
 669 }
 670
 671 void radeon_combios_i2c_init(struct radeon_device *rdev)
 672 {
 673         struct drm_device *dev = rdev->ddev;
 674         struct radeon_i2c_bus_rec i2c;
 675
 676         /* actual hw pads
 677          * r1xx/rs2xx/rs3xx
 678          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 679          * r200
 680          * 0x60, 0x64, 0x68, mm
 681          * r300/r350
 682          * 0x60, 0x64, mm
 683          * rv2xx/rv3xx/rs4xx
 684          * 0x60, 0x64, 0x68, gpiopads, mm
 685          */
 686
 687         /* 0x60 */
 688         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 689         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 690         /* 0x64 */
 691         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 692         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 693
 694         /* mm i2c */
 695         i2c.valid = true;
 696         i2c.hw_capable = true;
 697         i2c.mm_i2c = true;
 698         i2c.i2c_id = 0xa0;
 699         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 700
 701         if (rdev->family == CHIP_R300 ||
 702             rdev->family == CHIP_R350) {
 703                 /* only 2 sw i2c pads */
 704         } else if (rdev->family == CHIP_RS300 ||
 705                    rdev->family == CHIP_RS400 ||
 706                    rdev->family == CHIP_RS480) {
 707                 /* 0x68 */
 708                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 709                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 710
 711                 /* gpiopad */
 712                 i2c = radeon_combios_get_i2c_info_from_table(rdev);
 713                 if (i2c.valid)
 714                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 715         } else if ((rdev->family == CHIP_R200) ||
 716                    (rdev->family >= CHIP_R300)) {
 717                 /* 0x68 */
 718                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 719                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 720         } else {
 721                 /* 0x68 */
 722                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 723                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 724                 /* 0x6c */
 725                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 726                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 727         }
 728 }
 729
 730 bool radeon_combios_get_clock_info(struct drm_device *dev)
 731 {
 732         struct radeon_device *rdev = dev->dev_private;
 733         uint16_t pll_info;
 734         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 735         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 736         struct radeon_pll *spll = &rdev->clock.spll;
 737         struct radeon_pll *mpll = &rdev->clock.mpll;
 738         int8_t rev;
 739         uint16_t sclk, mclk;
 740
 741         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 742         if (pll_info) {
 743                 rev = RBIOS8(pll_info);
 744
 745                 /* pixel clocks */
 746                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 747                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 748                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 749                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 750                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 751                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 752
 753                 if (rev > 9) {
 754                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 755                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 756                 } else {
 757                         p1pll->pll_in_min = 40;
 758                         p1pll->pll_in_max = 500;
 759                 }
 760                 *p2pll = *p1pll;
 761
 762                 /* system clock */
 763                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 764                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 765                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 766                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 767
 768                 if (rev > 10) {
 769                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 770                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 771                 } else {
 772                         /* ??? */
 773                         spll->pll_in_min = 40;
 774                         spll->pll_in_max = 500;
 775                 }
 776
 777                 /* memory clock */
 778                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 779                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 780                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 781                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 782
 783                 if (rev > 10) {
 784                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 785                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 786                 } else {
 787                         /* ??? */
 788                         mpll->pll_in_min = 40;
 789                         mpll->pll_in_max = 500;
 790                 }
 791
 792                 /* default sclk/mclk */
 793                 sclk = RBIOS16(pll_info + 0xa);
 794                 mclk = RBIOS16(pll_info + 0x8);
 795                 if (sclk == 0)
 796                         sclk = 200 * 100;
 797                 if (mclk == 0)
 798                         mclk = 200 * 100;
 799
 800                 rdev->clock.default_sclk = sclk;
 801                 rdev->clock.default_mclk = mclk;
 802
 803                 if (RBIOS32(pll_info + 0x16))
 804                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 805                 else
 806                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 807
 808                 return true;
 809         }
 810         return false;
 811 }
 812
 813 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 814 {
 815         struct drm_device *dev = rdev->ddev;
 816         u16 igp_info;
 817
 818         /* sideport is AMD only */
 819         if (rdev->family == CHIP_RS400)
 820                 return false;
 821
 822         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 823
 824         if (igp_info) {
 825                 if (RBIOS16(igp_info + 0x4))
 826                         return true;
 827         }
 828         return false;
 829 }
 830
 831 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 832         0x00000808,             /* r100  */
 833         0x00000808,             /* rv100 */
 834         0x00000808,             /* rs100 */
 835         0x00000808,             /* rv200 */
 836         0x00000808,             /* rs200 */
 837         0x00000808,             /* r200  */
 838         0x00000808,             /* rv250 */
 839         0x00000000,             /* rs300 */
 840         0x00000808,             /* rv280 */
 841         0x00000808,             /* r300  */
 842         0x00000808,             /* r350  */
 843         0x00000808,             /* rv350 */
 844         0x00000808,             /* rv380 */
 845         0x00000808,             /* r420  */
 846         0x00000808,             /* r423  */
 847         0x00000808,             /* rv410 */
 848         0x00000000,             /* rs400 */
 849         0x00000000,             /* rs480 */
 850 };
 851
 852 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 853                                                           struct radeon_encoder_primary_dac *p_dac)
 854 {
 855         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 856         return;
 857 }
 858
 859 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 860                                                                        radeon_encoder
 861                                                                        *encoder)
 862 {
 863         struct drm_device *dev = encoder->base.dev;
 864         struct radeon_device *rdev = dev->dev_private;
 865         uint16_t dac_info;
 866         uint8_t rev, bg, dac;
 867         struct radeon_encoder_primary_dac *p_dac = NULL;
 868         int found = 0;
 869
 870         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 871                         GFP_KERNEL);
 872
 873         if (!p_dac)
 874                 return NULL;
 875
 876         /* check CRT table */
 877         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 878         if (dac_info) {
 879                 rev = RBIOS8(dac_info) & 0x3;
 880                 if (rev < 2) {
 881                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 882                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 883                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 884                 } else {
 885                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 886                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 887                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 888                 }
 889                 /* if the values are zeros, use the table */
 890                 if ((dac == 0) || (bg == 0))
 891                         found = 0;
 892                 else
 893                         found = 1;
 894         }
 895
 896         /* quirks */
 897         /* Radeon 7000 (RV100) */
 898         if (((dev->pdev->device == 0x5159) &&
 899             (dev->pdev->subsystem_vendor == 0x174B) &&
 900             (dev->pdev->subsystem_device == 0x7c28)) ||
 901         /* Radeon 9100 (R200) */
 902            ((dev->pdev->device == 0x514D) &&
 903             (dev->pdev->subsystem_vendor == 0x174B) &&
 904             (dev->pdev->subsystem_device == 0x7149))) {
 905                 /* vbios value is bad, use the default */
 906                 found = 0;
 907         }
 908
 909         if (!found) /* fallback to defaults */
 910                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 911
 912         return p_dac;
 913 }
 914
 915 enum radeon_tv_std
 916 radeon_combios_get_tv_info(struct radeon_device *rdev)
 917 {
 918         struct drm_device *dev = rdev->ddev;
 919         uint16_t tv_info;
 920         enum radeon_tv_std tv_std = TV_STD_NTSC;
 921
 922         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 923         if (tv_info) {
 924                 if (RBIOS8(tv_info + 6) == 'T') {
 925                         switch (RBIOS8(tv_info + 7) & 0xf) {
 926                         case 1:
 927                                 tv_std = TV_STD_NTSC;
 928                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 929                                 break;
 930                         case 2:
 931                                 tv_std = TV_STD_PAL;
 932                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 933                                 break;
 934                         case 3:
 935                                 tv_std = TV_STD_PAL_M;
 936                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 937                                 break;
 938                         case 4:
 939                                 tv_std = TV_STD_PAL_60;
 940                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 941                                 break;
 942                         case 5:
 943                                 tv_std = TV_STD_NTSC_J;
 944                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
 945                                 break;
 946                         case 6:
 947                                 tv_std = TV_STD_SCART_PAL;
 948                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
 949                                 break;
 950                         default:
 951                                 tv_std = TV_STD_NTSC;
 952                                 DRM_DEBUG_KMS
 953                                     ("Unknown TV standard; defaulting to NTSC\n");
 954                                 break;
 955                         }
 956
 957                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 958                         case 0:
 959                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
 960                                 break;
 961                         case 1:
 962                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
 963                                 break;
 964                         case 2:
 965                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
 966                                 break;
 967                         case 3:
 968                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
 969                                 break;
 970                         default:
 971                                 break;
 972                         }
 973                 }
 974         }
 975         return tv_std;
 976 }
 977
 978 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 979         0x00000000,             /* r100  */
 980         0x00280000,             /* rv100 */
 981         0x00000000,             /* rs100 */
 982         0x00880000,             /* rv200 */
 983         0x00000000,             /* rs200 */
 984         0x00000000,             /* r200  */
 985         0x00770000,             /* rv250 */
 986         0x00290000,             /* rs300 */
 987         0x00560000,             /* rv280 */
 988         0x00780000,             /* r300  */
 989         0x00770000,             /* r350  */
 990         0x00780000,             /* rv350 */
 991         0x00780000,             /* rv380 */
 992         0x01080000,             /* r420  */
 993         0x01080000,             /* r423  */
 994         0x01080000,             /* rv410 */
 995         0x00780000,             /* rs400 */
 996         0x00780000,             /* rs480 */
 997 };
 998
 999 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1000                                                      struct radeon_encoder_tv_dac *tv_dac)
1001 {
1002         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1003         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1004                 tv_dac->ps2_tvdac_adj = 0x00880000;
1005         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1006         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1007         return;
1008 }
1009
1010 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1011                                                              radeon_encoder
1012                                                              *encoder)
1013 {
1014         struct drm_device *dev = encoder->base.dev;
1015         struct radeon_device *rdev = dev->dev_private;
1016         uint16_t dac_info;
1017         uint8_t rev, bg, dac;
1018         struct radeon_encoder_tv_dac *tv_dac = NULL;
1019         int found = 0;
1020
1021         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1022         if (!tv_dac)
1023                 return NULL;
1024
1025         /* first check TV table */
1026         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1027         if (dac_info) {
1028                 rev = RBIOS8(dac_info + 0x3);
1029                 if (rev > 4) {
1030                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1031                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1032                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1033
1034                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1035                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1036                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1037
1038                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1039                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1040                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1041                         /* if the values are all zeros, use the table */
1042                         if (tv_dac->ps2_tvdac_adj)
1043                                 found = 1;
1044                 } else if (rev > 1) {
1045                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1046                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1047                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1048
1049                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1050                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1051                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1052
1053                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1054                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1055                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1056                         /* if the values are all zeros, use the table */
1057                         if (tv_dac->ps2_tvdac_adj)
1058                                 found = 1;
1059                 }
1060                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1061         }
1062         if (!found) {
1063                 /* then check CRT table */
1064                 dac_info =
1065                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1066                 if (dac_info) {
1067                         rev = RBIOS8(dac_info) & 0x3;
1068                         if (rev < 2) {
1069                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1070                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1071                                 tv_dac->ps2_tvdac_adj =
1072                                     (bg << 16) | (dac << 20);
1073                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1074                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1075                                 /* if the values are all zeros, use the table */
1076                                 if (tv_dac->ps2_tvdac_adj)
1077                                         found = 1;
1078                         } else {
1079                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1080                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1081                                 tv_dac->ps2_tvdac_adj =
1082                                     (bg << 16) | (dac << 20);
1083                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1084                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1085                                 /* if the values are all zeros, use the table */
1086                                 if (tv_dac->ps2_tvdac_adj)
1087                                         found = 1;
1088                         }
1089                 } else {
1090                         DRM_INFO("No TV DAC info found in BIOS\n");
1091                 }
1092         }
1093
1094         if (!found) /* fallback to defaults */
1095                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1096
1097         return tv_dac;
1098 }
1099
1100 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1101                                                                          radeon_device
1102                                                                          *rdev)
1103 {
1104         struct radeon_encoder_lvds *lvds = NULL;
1105         uint32_t fp_vert_stretch, fp_horz_stretch;
1106         uint32_t ppll_div_sel, ppll_val;
1107         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1108
1109         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1110
1111         if (!lvds)
1112                 return NULL;
1113
1114         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1115         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1116
1117         /* These should be fail-safe defaults, fingers crossed */
1118         lvds->panel_pwr_delay = 200;
1119         lvds->panel_vcc_delay = 2000;
1120
1121         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1122         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1123         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1124
1125         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1126                 lvds->native_mode.vdisplay =
1127                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1128                      RADEON_VERT_PANEL_SHIFT) + 1;
1129         else
1130                 lvds->native_mode.vdisplay =
1131                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1132
1133         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1134                 lvds->native_mode.hdisplay =
1135                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1136                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1137         else
1138                 lvds->native_mode.hdisplay =
1139                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1140
1141         if ((lvds->native_mode.hdisplay < 640) ||
1142             (lvds->native_mode.vdisplay < 480)) {
1143                 lvds->native_mode.hdisplay = 640;
1144                 lvds->native_mode.vdisplay = 480;
1145         }
1146
1147         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1148         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1149         if ((ppll_val & 0x000707ff) == 0x1bb)
1150                 lvds->use_bios_dividers = false;
1151         else {
1152                 lvds->panel_ref_divider =
1153                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1154                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1155                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1156
1157                 if ((lvds->panel_ref_divider != 0) &&
1158                     (lvds->panel_fb_divider > 3))
1159                         lvds->use_bios_dividers = true;
1160         }
1161         lvds->panel_vcc_delay = 200;
1162
1163         DRM_INFO("Panel info derived from registers\n");
1164         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1165                  lvds->native_mode.vdisplay);
1166
1167         return lvds;
1168 }
1169
1170 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1171                                                          *encoder)
1172 {
1173         struct drm_device *dev = encoder->base.dev;
1174         struct radeon_device *rdev = dev->dev_private;
1175         uint16_t lcd_info;
1176         uint32_t panel_setup;
1177         char stmp[30];
1178         int tmp, i;
1179         struct radeon_encoder_lvds *lvds = NULL;
1180
1181         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1182
1183         if (lcd_info) {
1184                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1185
1186                 if (!lvds)
1187                         return NULL;
1188
1189                 for (i = 0; i < 24; i++)
1190                         stmp[i] = RBIOS8(lcd_info + i + 1);
1191                 stmp[24] = 0;
1192
1193                 DRM_INFO("Panel ID String: %s\n", stmp);
1194
1195                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1196                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1197
1198                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1199                          lvds->native_mode.vdisplay);
1200
1201                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1202                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1203
1204                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1205                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1206                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1207
1208                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1209                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1210                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1211                 if ((lvds->panel_ref_divider != 0) &&
1212                     (lvds->panel_fb_divider > 3))
1213                         lvds->use_bios_dividers = true;
1214
1215                 panel_setup = RBIOS32(lcd_info + 0x39);
1216                 lvds->lvds_gen_cntl = 0xff00;
1217                 if (panel_setup & 0x1)
1218                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1219
1220                 if ((panel_setup >> 4) & 0x1)
1221                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1222
1223                 switch ((panel_setup >> 8) & 0x7) {
1224                 case 0:
1225                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1226                         break;
1227                 case 1:
1228                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1229                         break;
1230                 case 2:
1231                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1232                         break;
1233                 default:
1234                         break;
1235                 }
1236
1237                 if ((panel_setup >> 16) & 0x1)
1238                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1239
1240                 if ((panel_setup >> 17) & 0x1)
1241                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1242
1243                 if ((panel_setup >> 18) & 0x1)
1244                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1245
1246                 if ((panel_setup >> 23) & 0x1)
1247                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1248
1249                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1250
1251                 for (i = 0; i < 32; i++) {
1252                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1253                         if (tmp == 0)
1254                                 break;
1255
1256                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1257                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1258                                 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1259
1260                                 if (hss > lvds->native_mode.hdisplay)
1261                                         hss = (10 - 1) * 8;
1262
1263                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1264                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1265                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1266                                         hss;
1267                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1268                                         (RBIOS8(tmp + 23) * 8);
1269
1270                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1271                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1272                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1273                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1274                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1275                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1276
1277                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1278                                 lvds->native_mode.flags = 0;
1279                                 /* set crtc values */
1280                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1281
1282                         }
1283                 }
1284         } else {
1285                 DRM_INFO("No panel info found in BIOS\n");
1286                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1287         }
1288
1289         if (lvds)
1290                 encoder->native_mode = lvds->native_mode;
1291         return lvds;
1292 }
1293
1294 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1295         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1296         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1297         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1298         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1299         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1300         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1301         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1302         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1303         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1304         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1305         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1306         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1307         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1308         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1309         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1310         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1311         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1312         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1313 };
1314
1315 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1316                                             struct radeon_encoder_int_tmds *tmds)
1317 {
1318         struct drm_device *dev = encoder->base.dev;
1319         struct radeon_device *rdev = dev->dev_private;
1320         int i;
1321
1322         for (i = 0; i < 4; i++) {
1323                 tmds->tmds_pll[i].value =
1324                         default_tmds_pll[rdev->family][i].value;
1325                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1326         }
1327
1328         return true;
1329 }
1330
1331 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1332                                               struct radeon_encoder_int_tmds *tmds)
1333 {
1334         struct drm_device *dev = encoder->base.dev;
1335         struct radeon_device *rdev = dev->dev_private;
1336         uint16_t tmds_info;
1337         int i, n;
1338         uint8_t ver;
1339
1340         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1341
1342         if (tmds_info) {
1343                 ver = RBIOS8(tmds_info);
1344                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1345                 if (ver == 3) {
1346                         n = RBIOS8(tmds_info + 5) + 1;
1347                         if (n > 4)
1348                                 n = 4;
1349                         for (i = 0; i < n; i++) {
1350                                 tmds->tmds_pll[i].value =
1351                                     RBIOS32(tmds_info + i * 10 + 0x08);
1352                                 tmds->tmds_pll[i].freq =
1353                                     RBIOS16(tmds_info + i * 10 + 0x10);
1354                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1355                                           tmds->tmds_pll[i].freq,
1356                                           tmds->tmds_pll[i].value);
1357                         }
1358                 } else if (ver == 4) {
1359                         int stride = 0;
1360                         n = RBIOS8(tmds_info + 5) + 1;
1361                         if (n > 4)
1362                                 n = 4;
1363                         for (i = 0; i < n; i++) {
1364                                 tmds->tmds_pll[i].value =
1365                                     RBIOS32(tmds_info + stride + 0x08);
1366                                 tmds->tmds_pll[i].freq =
1367                                     RBIOS16(tmds_info + stride + 0x10);
1368                                 if (i == 0)
1369                                         stride += 10;
1370                                 else
1371                                         stride += 6;
1372                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1373                                           tmds->tmds_pll[i].freq,
1374                                           tmds->tmds_pll[i].value);
1375                         }
1376                 }
1377         } else {
1378                 DRM_INFO("No TMDS info found in BIOS\n");
1379                 return false;
1380         }
1381         return true;
1382 }
1383
1384 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1385                                                 struct radeon_encoder_ext_tmds *tmds)
1386 {
1387         struct drm_device *dev = encoder->base.dev;
1388         struct radeon_device *rdev = dev->dev_private;
1389         struct radeon_i2c_bus_rec i2c_bus;
1390
1391         /* default for macs */
1392         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1393         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1394
1395         /* XXX some macs have duallink chips */
1396         switch (rdev->mode_info.connector_table) {
1397         case CT_POWERBOOK_EXTERNAL:
1398         case CT_MINI_EXTERNAL:
1399         default:
1400                 tmds->dvo_chip = DVO_SIL164;
1401                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1402                 break;
1403         }
1404
1405         return true;
1406 }
1407
1408 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1409                                                   struct radeon_encoder_ext_tmds *tmds)
1410 {
1411         struct drm_device *dev = encoder->base.dev;
1412         struct radeon_device *rdev = dev->dev_private;
1413         uint16_t offset;
1414         uint8_t ver;
1415         enum radeon_combios_ddc gpio;
1416         struct radeon_i2c_bus_rec i2c_bus;
1417
1418         tmds->i2c_bus = NULL;
1419         if (rdev->flags & RADEON_IS_IGP) {
1420                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1421                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1422                 tmds->dvo_chip = DVO_SIL164;
1423                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1424         } else {
1425                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1426                 if (offset) {
1427                         ver = RBIOS8(offset);
1428                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1429                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1430                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1431                         gpio = RBIOS8(offset + 4 + 3);
1432                         if (gpio == DDC_LCD) {
1433                                 /* MM i2c */
1434                                 i2c_bus.valid = true;
1435                                 i2c_bus.hw_capable = true;
1436                                 i2c_bus.mm_i2c = true;
1437                                 i2c_bus.i2c_id = 0xa0;
1438                         } else
1439                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1440                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1441                 }
1442         }
1443
1444         if (!tmds->i2c_bus) {
1445                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1446                 return false;
1447         }
1448
1449         return true;
1450 }
1451
1452 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1453 {
1454         struct radeon_device *rdev = dev->dev_private;
1455         struct radeon_i2c_bus_rec ddc_i2c;
1456         struct radeon_hpd hpd;
1457
1458         rdev->mode_info.connector_table = radeon_connector_table;
1459         if (rdev->mode_info.connector_table == CT_NONE) {
1460 #ifdef CONFIG_PPC_PMAC
1461                 if (of_machine_is_compatible("PowerBook3,3")) {
1462                         /* powerbook with VGA */
1463                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1464                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1465                            of_machine_is_compatible("PowerBook3,5")) {
1466                         /* powerbook with internal tmds */
1467                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1468                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1469                            of_machine_is_compatible("PowerBook5,2") ||
1470                            of_machine_is_compatible("PowerBook5,3") ||
1471                            of_machine_is_compatible("PowerBook5,4") ||
1472                            of_machine_is_compatible("PowerBook5,5")) {
1473                         /* powerbook with external single link tmds (sil164) */
1474                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1475                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1476                         /* powerbook with external dual or single link tmds */
1477                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1478                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1479                            of_machine_is_compatible("PowerBook5,8") ||
1480                            of_machine_is_compatible("PowerBook5,9")) {
1481                         /* PowerBook6,2 ? */
1482                         /* powerbook with external dual link tmds (sil1178?) */
1483                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1484                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1485                            of_machine_is_compatible("PowerBook4,2") ||
1486                            of_machine_is_compatible("PowerBook4,3") ||
1487                            of_machine_is_compatible("PowerBook6,3") ||
1488                            of_machine_is_compatible("PowerBook6,5") ||
1489                            of_machine_is_compatible("PowerBook6,7")) {
1490                         /* ibook */
1491                         rdev->mode_info.connector_table = CT_IBOOK;
1492                 } else if (of_machine_is_compatible("PowerMac3,5")) {
1493                         /* PowerMac G4 Silver radeon 7500 */
1494                         rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1495                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1496                         /* emac */
1497                         rdev->mode_info.connector_table = CT_EMAC;
1498                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1499                         /* mini with internal tmds */
1500                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1501                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1502                         /* mini with external tmds */
1503                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1504                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1505                         /* PowerMac8,1 ? */
1506                         /* imac g5 isight */
1507                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1508                 } else if ((rdev->pdev->device == 0x4a48) &&
1509                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1510                            (rdev->pdev->subsystem_device == 0x4a48)) {
1511                         /* Mac X800 */
1512                         rdev->mode_info.connector_table = CT_MAC_X800;
1513                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1514                             of_machine_is_compatible("PowerMac7,3")) &&
1515                            (rdev->pdev->device == 0x4150) &&
1516                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1517                            (rdev->pdev->subsystem_device == 0x4150)) {
1518                         /* Mac G5 tower 9600 */
1519                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1520                 } else if ((rdev->pdev->device == 0x4c66) &&
1521                            (rdev->pdev->subsystem_vendor == 0x1002) &&
1522                            (rdev->pdev->subsystem_device == 0x4c66)) {
1523                         /* SAM440ep RV250 embedded board */
1524                         rdev->mode_info.connector_table = CT_SAM440EP;
1525                 } else
1526 #endif /* CONFIG_PPC_PMAC */
1527 #ifdef CONFIG_PPC64
1528                 if (ASIC_IS_RN50(rdev))
1529                         rdev->mode_info.connector_table = CT_RN50_POWER;
1530                 else
1531 #endif
1532                         rdev->mode_info.connector_table = CT_GENERIC;
1533         }
1534
1535         switch (rdev->mode_info.connector_table) {
1536         case CT_GENERIC:
1537                 DRM_INFO("Connector Table: %d (generic)\n",
1538                          rdev->mode_info.connector_table);
1539                 /* these are the most common settings */
1540                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1541                         /* VGA - primary dac */
1542                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1543                         hpd.hpd = RADEON_HPD_NONE;
1544                         radeon_add_legacy_encoder(dev,
1545                                                   radeon_get_encoder_enum(dev,
1546                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1547                                                                         1),
1548                                                   ATOM_DEVICE_CRT1_SUPPORT);
1549                         radeon_add_legacy_connector(dev, 0,
1550                                                     ATOM_DEVICE_CRT1_SUPPORT,
1551                                                     DRM_MODE_CONNECTOR_VGA,
1552                                                     &ddc_i2c,
1553                                                     CONNECTOR_OBJECT_ID_VGA,
1554                                                     &hpd);
1555                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1556                         /* LVDS */
1557                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1558                         hpd.hpd = RADEON_HPD_NONE;
1559                         radeon_add_legacy_encoder(dev,
1560                                                   radeon_get_encoder_enum(dev,
1561                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1562                                                                         0),
1563                                                   ATOM_DEVICE_LCD1_SUPPORT);
1564                         radeon_add_legacy_connector(dev, 0,
1565                                                     ATOM_DEVICE_LCD1_SUPPORT,
1566                                                     DRM_MODE_CONNECTOR_LVDS,
1567                                                     &ddc_i2c,
1568                                                     CONNECTOR_OBJECT_ID_LVDS,
1569                                                     &hpd);
1570
1571                         /* VGA - primary dac */
1572                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1573                         hpd.hpd = RADEON_HPD_NONE;
1574                         radeon_add_legacy_encoder(dev,
1575                                                   radeon_get_encoder_enum(dev,
1576                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1577                                                                         1),
1578                                                   ATOM_DEVICE_CRT1_SUPPORT);
1579                         radeon_add_legacy_connector(dev, 1,
1580                                                     ATOM_DEVICE_CRT1_SUPPORT,
1581                                                     DRM_MODE_CONNECTOR_VGA,
1582                                                     &ddc_i2c,
1583                                                     CONNECTOR_OBJECT_ID_VGA,
1584                                                     &hpd);
1585                 } else {
1586                         /* DVI-I - tv dac, int tmds */
1587                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1588                         hpd.hpd = RADEON_HPD_1;
1589                         radeon_add_legacy_encoder(dev,
1590                                                   radeon_get_encoder_enum(dev,
1591                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1592                                                                         0),
1593                                                   ATOM_DEVICE_DFP1_SUPPORT);
1594                         radeon_add_legacy_encoder(dev,
1595                                                   radeon_get_encoder_enum(dev,
1596                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1597                                                                         2),
1598                                                   ATOM_DEVICE_CRT2_SUPPORT);
1599                         radeon_add_legacy_connector(dev, 0,
1600                                                     ATOM_DEVICE_DFP1_SUPPORT |
1601                                                     ATOM_DEVICE_CRT2_SUPPORT,
1602                                                     DRM_MODE_CONNECTOR_DVII,
1603                                                     &ddc_i2c,
1604                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1605                                                     &hpd);
1606
1607                         /* VGA - primary dac */
1608                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1609                         hpd.hpd = RADEON_HPD_NONE;
1610                         radeon_add_legacy_encoder(dev,
1611                                                   radeon_get_encoder_enum(dev,
1612                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1613                                                                         1),
1614                                                   ATOM_DEVICE_CRT1_SUPPORT);
1615                         radeon_add_legacy_connector(dev, 1,
1616                                                     ATOM_DEVICE_CRT1_SUPPORT,
1617                                                     DRM_MODE_CONNECTOR_VGA,
1618                                                     &ddc_i2c,
1619                                                     CONNECTOR_OBJECT_ID_VGA,
1620                                                     &hpd);
1621                 }
1622
1623                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1624                         /* TV - tv dac */
1625                         ddc_i2c.valid = false;
1626                         hpd.hpd = RADEON_HPD_NONE;
1627                         radeon_add_legacy_encoder(dev,
1628                                                   radeon_get_encoder_enum(dev,
1629                                                                         ATOM_DEVICE_TV1_SUPPORT,
1630                                                                         2),
1631                                                   ATOM_DEVICE_TV1_SUPPORT);
1632                         radeon_add_legacy_connector(dev, 2,
1633                                                     ATOM_DEVICE_TV1_SUPPORT,
1634                                                     DRM_MODE_CONNECTOR_SVIDEO,
1635                                                     &ddc_i2c,
1636                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1637                                                     &hpd);
1638                 }
1639                 break;
1640         case CT_IBOOK:
1641                 DRM_INFO("Connector Table: %d (ibook)\n",
1642                          rdev->mode_info.connector_table);
1643                 /* LVDS */
1644                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1645                 hpd.hpd = RADEON_HPD_NONE;
1646                 radeon_add_legacy_encoder(dev,
1647                                           radeon_get_encoder_enum(dev,
1648                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1649                                                                 0),
1650                                           ATOM_DEVICE_LCD1_SUPPORT);
1651                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1652                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1653                                             CONNECTOR_OBJECT_ID_LVDS,
1654                                             &hpd);
1655                 /* VGA - TV DAC */
1656                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1657                 hpd.hpd = RADEON_HPD_NONE;
1658                 radeon_add_legacy_encoder(dev,
1659                                           radeon_get_encoder_enum(dev,
1660                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1661                                                                 2),
1662                                           ATOM_DEVICE_CRT2_SUPPORT);
1663                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1664                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1665                                             CONNECTOR_OBJECT_ID_VGA,
1666                                             &hpd);
1667                 /* TV - TV DAC */
1668                 ddc_i2c.valid = false;
1669                 hpd.hpd = RADEON_HPD_NONE;
1670                 radeon_add_legacy_encoder(dev,
1671                                           radeon_get_encoder_enum(dev,
1672                                                                 ATOM_DEVICE_TV1_SUPPORT,
1673                                                                 2),
1674                                           ATOM_DEVICE_TV1_SUPPORT);
1675                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1676                                             DRM_MODE_CONNECTOR_SVIDEO,
1677                                             &ddc_i2c,
1678                                             CONNECTOR_OBJECT_ID_SVIDEO,
1679                                             &hpd);
1680                 break;
1681         case CT_POWERBOOK_EXTERNAL:
1682                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1683                          rdev->mode_info.connector_table);
1684                 /* LVDS */
1685                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1686                 hpd.hpd = RADEON_HPD_NONE;
1687                 radeon_add_legacy_encoder(dev,
1688                                           radeon_get_encoder_enum(dev,
1689                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1690                                                                 0),
1691                                           ATOM_DEVICE_LCD1_SUPPORT);
1692                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1693                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1694                                             CONNECTOR_OBJECT_ID_LVDS,
1695                                             &hpd);
1696                 /* DVI-I - primary dac, ext tmds */
1697                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1698                 hpd.hpd = RADEON_HPD_2; /* ??? */
1699                 radeon_add_legacy_encoder(dev,
1700                                           radeon_get_encoder_enum(dev,
1701                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1702                                                                 0),
1703                                           ATOM_DEVICE_DFP2_SUPPORT);
1704                 radeon_add_legacy_encoder(dev,
1705                                           radeon_get_encoder_enum(dev,
1706                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1707                                                                 1),
1708                                           ATOM_DEVICE_CRT1_SUPPORT);
1709                 /* XXX some are SL */
1710                 radeon_add_legacy_connector(dev, 1,
1711                                             ATOM_DEVICE_DFP2_SUPPORT |
1712                                             ATOM_DEVICE_CRT1_SUPPORT,
1713                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1714                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1715                                             &hpd);
1716                 /* TV - TV DAC */
1717                 ddc_i2c.valid = false;
1718                 hpd.hpd = RADEON_HPD_NONE;
1719                 radeon_add_legacy_encoder(dev,
1720                                           radeon_get_encoder_enum(dev,
1721                                                                 ATOM_DEVICE_TV1_SUPPORT,
1722                                                                 2),
1723                                           ATOM_DEVICE_TV1_SUPPORT);
1724                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1725                                             DRM_MODE_CONNECTOR_SVIDEO,
1726                                             &ddc_i2c,
1727                                             CONNECTOR_OBJECT_ID_SVIDEO,
1728                                             &hpd);
1729                 break;
1730         case CT_POWERBOOK_INTERNAL:
1731                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1732                          rdev->mode_info.connector_table);
1733                 /* LVDS */
1734                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1735                 hpd.hpd = RADEON_HPD_NONE;
1736                 radeon_add_legacy_encoder(dev,
1737                                           radeon_get_encoder_enum(dev,
1738                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1739                                                                 0),
1740                                           ATOM_DEVICE_LCD1_SUPPORT);
1741                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1742                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1743                                             CONNECTOR_OBJECT_ID_LVDS,
1744                                             &hpd);
1745                 /* DVI-I - primary dac, int tmds */
1746                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1747                 hpd.hpd = RADEON_HPD_1; /* ??? */
1748                 radeon_add_legacy_encoder(dev,
1749                                           radeon_get_encoder_enum(dev,
1750                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1751                                                                 0),
1752                                           ATOM_DEVICE_DFP1_SUPPORT);
1753                 radeon_add_legacy_encoder(dev,
1754                                           radeon_get_encoder_enum(dev,
1755                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1756                                                                 1),
1757                                           ATOM_DEVICE_CRT1_SUPPORT);
1758                 radeon_add_legacy_connector(dev, 1,
1759                                             ATOM_DEVICE_DFP1_SUPPORT |
1760                                             ATOM_DEVICE_CRT1_SUPPORT,
1761                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1762                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1763                                             &hpd);
1764                 /* TV - TV DAC */
1765                 ddc_i2c.valid = false;
1766                 hpd.hpd = RADEON_HPD_NONE;
1767                 radeon_add_legacy_encoder(dev,
1768                                           radeon_get_encoder_enum(dev,
1769                                                                 ATOM_DEVICE_TV1_SUPPORT,
1770                                                                 2),
1771                                           ATOM_DEVICE_TV1_SUPPORT);
1772                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1773                                             DRM_MODE_CONNECTOR_SVIDEO,
1774                                             &ddc_i2c,
1775                                             CONNECTOR_OBJECT_ID_SVIDEO,
1776                                             &hpd);
1777                 break;
1778         case CT_POWERBOOK_VGA:
1779                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1780                          rdev->mode_info.connector_table);
1781                 /* LVDS */
1782                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1783                 hpd.hpd = RADEON_HPD_NONE;
1784                 radeon_add_legacy_encoder(dev,
1785                                           radeon_get_encoder_enum(dev,
1786                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1787                                                                 0),
1788                                           ATOM_DEVICE_LCD1_SUPPORT);
1789                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1790                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1791                                             CONNECTOR_OBJECT_ID_LVDS,
1792                                             &hpd);
1793                 /* VGA - primary dac */
1794                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1795                 hpd.hpd = RADEON_HPD_NONE;
1796                 radeon_add_legacy_encoder(dev,
1797                                           radeon_get_encoder_enum(dev,
1798                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1799                                                                 1),
1800                                           ATOM_DEVICE_CRT1_SUPPORT);
1801                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1802                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1803                                             CONNECTOR_OBJECT_ID_VGA,
1804                                             &hpd);
1805                 /* TV - TV DAC */
1806                 ddc_i2c.valid = false;
1807                 hpd.hpd = RADEON_HPD_NONE;
1808                 radeon_add_legacy_encoder(dev,
1809                                           radeon_get_encoder_enum(dev,
1810                                                                 ATOM_DEVICE_TV1_SUPPORT,
1811                                                                 2),
1812                                           ATOM_DEVICE_TV1_SUPPORT);
1813                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1814                                             DRM_MODE_CONNECTOR_SVIDEO,
1815                                             &ddc_i2c,
1816                                             CONNECTOR_OBJECT_ID_SVIDEO,
1817                                             &hpd);
1818                 break;
1819         case CT_MINI_EXTERNAL:
1820                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1821                          rdev->mode_info.connector_table);
1822                 /* DVI-I - tv dac, ext tmds */
1823                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1824                 hpd.hpd = RADEON_HPD_2; /* ??? */
1825                 radeon_add_legacy_encoder(dev,
1826                                           radeon_get_encoder_enum(dev,
1827                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1828                                                                 0),
1829                                           ATOM_DEVICE_DFP2_SUPPORT);
1830                 radeon_add_legacy_encoder(dev,
1831                                           radeon_get_encoder_enum(dev,
1832                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1833                                                                 2),
1834                                           ATOM_DEVICE_CRT2_SUPPORT);
1835                 /* XXX are any DL? */
1836                 radeon_add_legacy_connector(dev, 0,
1837                                             ATOM_DEVICE_DFP2_SUPPORT |
1838                                             ATOM_DEVICE_CRT2_SUPPORT,
1839                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1840                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1841                                             &hpd);
1842                 /* TV - TV DAC */
1843                 ddc_i2c.valid = false;
1844                 hpd.hpd = RADEON_HPD_NONE;
1845                 radeon_add_legacy_encoder(dev,
1846                                           radeon_get_encoder_enum(dev,
1847                                                                 ATOM_DEVICE_TV1_SUPPORT,
1848                                                                 2),
1849                                           ATOM_DEVICE_TV1_SUPPORT);
1850                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1851                                             DRM_MODE_CONNECTOR_SVIDEO,
1852                                             &ddc_i2c,
1853                                             CONNECTOR_OBJECT_ID_SVIDEO,
1854                                             &hpd);
1855                 break;
1856         case CT_MINI_INTERNAL:
1857                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1858                          rdev->mode_info.connector_table);
1859                 /* DVI-I - tv dac, int tmds */
1860                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1861                 hpd.hpd = RADEON_HPD_1; /* ??? */
1862                 radeon_add_legacy_encoder(dev,
1863                                           radeon_get_encoder_enum(dev,
1864                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1865                                                                 0),
1866                                           ATOM_DEVICE_DFP1_SUPPORT);
1867                 radeon_add_legacy_encoder(dev,
1868                                           radeon_get_encoder_enum(dev,
1869                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1870                                                                 2),
1871                                           ATOM_DEVICE_CRT2_SUPPORT);
1872                 radeon_add_legacy_connector(dev, 0,
1873                                             ATOM_DEVICE_DFP1_SUPPORT |
1874                                             ATOM_DEVICE_CRT2_SUPPORT,
1875                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1876                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1877                                             &hpd);
1878                 /* TV - TV DAC */
1879                 ddc_i2c.valid = false;
1880                 hpd.hpd = RADEON_HPD_NONE;
1881                 radeon_add_legacy_encoder(dev,
1882                                           radeon_get_encoder_enum(dev,
1883                                                                 ATOM_DEVICE_TV1_SUPPORT,
1884                                                                 2),
1885                                           ATOM_DEVICE_TV1_SUPPORT);
1886                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1887                                             DRM_MODE_CONNECTOR_SVIDEO,
1888                                             &ddc_i2c,
1889                                             CONNECTOR_OBJECT_ID_SVIDEO,
1890                                             &hpd);
1891                 break;
1892         case CT_IMAC_G5_ISIGHT:
1893                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1894                          rdev->mode_info.connector_table);
1895                 /* DVI-D - int tmds */
1896                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1897                 hpd.hpd = RADEON_HPD_1; /* ??? */
1898                 radeon_add_legacy_encoder(dev,
1899                                           radeon_get_encoder_enum(dev,
1900                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1901                                                                 0),
1902                                           ATOM_DEVICE_DFP1_SUPPORT);
1903                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1904                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1905                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1906                                             &hpd);
1907                 /* VGA - tv dac */
1908                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1909                 hpd.hpd = RADEON_HPD_NONE;
1910                 radeon_add_legacy_encoder(dev,
1911                                           radeon_get_encoder_enum(dev,
1912                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1913                                                                 2),
1914                                           ATOM_DEVICE_CRT2_SUPPORT);
1915                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1916                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1917                                             CONNECTOR_OBJECT_ID_VGA,
1918                                             &hpd);
1919                 /* TV - TV DAC */
1920                 ddc_i2c.valid = false;
1921                 hpd.hpd = RADEON_HPD_NONE;
1922                 radeon_add_legacy_encoder(dev,
1923                                           radeon_get_encoder_enum(dev,
1924                                                                 ATOM_DEVICE_TV1_SUPPORT,
1925                                                                 2),
1926                                           ATOM_DEVICE_TV1_SUPPORT);
1927                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1928                                             DRM_MODE_CONNECTOR_SVIDEO,
1929                                             &ddc_i2c,
1930                                             CONNECTOR_OBJECT_ID_SVIDEO,
1931                                             &hpd);
1932                 break;
1933         case CT_EMAC:
1934                 DRM_INFO("Connector Table: %d (emac)\n",
1935                          rdev->mode_info.connector_table);
1936                 /* VGA - primary dac */
1937                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1938                 hpd.hpd = RADEON_HPD_NONE;
1939                 radeon_add_legacy_encoder(dev,
1940                                           radeon_get_encoder_enum(dev,
1941                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1942                                                                 1),
1943                                           ATOM_DEVICE_CRT1_SUPPORT);
1944                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1945                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1946                                             CONNECTOR_OBJECT_ID_VGA,
1947                                             &hpd);
1948                 /* VGA - tv dac */
1949                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1950                 hpd.hpd = RADEON_HPD_NONE;
1951                 radeon_add_legacy_encoder(dev,
1952                                           radeon_get_encoder_enum(dev,
1953                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1954                                                                 2),
1955                                           ATOM_DEVICE_CRT2_SUPPORT);
1956                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1957                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1958                                             CONNECTOR_OBJECT_ID_VGA,
1959                                             &hpd);
1960                 /* TV - TV DAC */
1961                 ddc_i2c.valid = false;
1962                 hpd.hpd = RADEON_HPD_NONE;
1963                 radeon_add_legacy_encoder(dev,
1964                                           radeon_get_encoder_enum(dev,
1965                                                                 ATOM_DEVICE_TV1_SUPPORT,
1966                                                                 2),
1967                                           ATOM_DEVICE_TV1_SUPPORT);
1968                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1969                                             DRM_MODE_CONNECTOR_SVIDEO,
1970                                             &ddc_i2c,
1971                                             CONNECTOR_OBJECT_ID_SVIDEO,
1972                                             &hpd);
1973                 break;
1974         case CT_RN50_POWER:
1975                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1976                          rdev->mode_info.connector_table);
1977                 /* VGA - primary dac */
1978                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1979                 hpd.hpd = RADEON_HPD_NONE;
1980                 radeon_add_legacy_encoder(dev,
1981                                           radeon_get_encoder_enum(dev,
1982                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1983                                                                 1),
1984                                           ATOM_DEVICE_CRT1_SUPPORT);
1985                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1986                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1987                                             CONNECTOR_OBJECT_ID_VGA,
1988                                             &hpd);
1989                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1990                 hpd.hpd = RADEON_HPD_NONE;
1991                 radeon_add_legacy_encoder(dev,
1992                                           radeon_get_encoder_enum(dev,
1993                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1994                                                                 2),
1995                                           ATOM_DEVICE_CRT2_SUPPORT);
1996                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1997                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1998                                             CONNECTOR_OBJECT_ID_VGA,
1999                                             &hpd);
2000                 break;
2001         case CT_MAC_X800:
2002                 DRM_INFO("Connector Table: %d (mac x800)\n",
2003                          rdev->mode_info.connector_table);
2004                 /* DVI - primary dac, internal tmds */
2005                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2006                 hpd.hpd = RADEON_HPD_1; /* ??? */
2007                 radeon_add_legacy_encoder(dev,
2008                                           radeon_get_encoder_enum(dev,
2009                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2010                                                                   0),
2011                                           ATOM_DEVICE_DFP1_SUPPORT);
2012                 radeon_add_legacy_encoder(dev,
2013                                           radeon_get_encoder_enum(dev,
2014                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2015                                                                   1),
2016                                           ATOM_DEVICE_CRT1_SUPPORT);
2017                 radeon_add_legacy_connector(dev, 0,
2018                                             ATOM_DEVICE_DFP1_SUPPORT |
2019                                             ATOM_DEVICE_CRT1_SUPPORT,
2020                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2021                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2022                                             &hpd);
2023                 /* DVI - tv dac, dvo */
2024                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2025                 hpd.hpd = RADEON_HPD_2; /* ??? */
2026                 radeon_add_legacy_encoder(dev,
2027                                           radeon_get_encoder_enum(dev,
2028                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2029                                                                   0),
2030                                           ATOM_DEVICE_DFP2_SUPPORT);
2031                 radeon_add_legacy_encoder(dev,
2032                                           radeon_get_encoder_enum(dev,
2033                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2034                                                                   2),
2035                                           ATOM_DEVICE_CRT2_SUPPORT);
2036                 radeon_add_legacy_connector(dev, 1,
2037                                             ATOM_DEVICE_DFP2_SUPPORT |
2038                                             ATOM_DEVICE_CRT2_SUPPORT,
2039                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2040                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2041                                             &hpd);
2042                 break;
2043         case CT_MAC_G5_9600:
2044                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2045                          rdev->mode_info.connector_table);
2046                 /* DVI - tv dac, dvo */
2047                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2048                 hpd.hpd = RADEON_HPD_1; /* ??? */
2049                 radeon_add_legacy_encoder(dev,
2050                                           radeon_get_encoder_enum(dev,
2051                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2052                                                                   0),
2053                                           ATOM_DEVICE_DFP2_SUPPORT);
2054                 radeon_add_legacy_encoder(dev,
2055                                           radeon_get_encoder_enum(dev,
2056                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2057                                                                   2),
2058                                           ATOM_DEVICE_CRT2_SUPPORT);
2059                 radeon_add_legacy_connector(dev, 0,
2060                                             ATOM_DEVICE_DFP2_SUPPORT |
2061                                             ATOM_DEVICE_CRT2_SUPPORT,
2062                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2063                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2064                                             &hpd);
2065                 /* ADC - primary dac, internal tmds */
2066                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2067                 hpd.hpd = RADEON_HPD_2; /* ??? */
2068                 radeon_add_legacy_encoder(dev,
2069                                           radeon_get_encoder_enum(dev,
2070                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2071                                                                   0),
2072                                           ATOM_DEVICE_DFP1_SUPPORT);
2073                 radeon_add_legacy_encoder(dev,
2074                                           radeon_get_encoder_enum(dev,
2075                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2076                                                                   1),
2077                                           ATOM_DEVICE_CRT1_SUPPORT);
2078                 radeon_add_legacy_connector(dev, 1,
2079                                             ATOM_DEVICE_DFP1_SUPPORT |
2080                                             ATOM_DEVICE_CRT1_SUPPORT,
2081                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2082                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2083                                             &hpd);
2084                 /* TV - TV DAC */
2085                 ddc_i2c.valid = false;
2086                 hpd.hpd = RADEON_HPD_NONE;
2087                 radeon_add_legacy_encoder(dev,
2088                                           radeon_get_encoder_enum(dev,
2089                                                                 ATOM_DEVICE_TV1_SUPPORT,
2090                                                                 2),
2091                                           ATOM_DEVICE_TV1_SUPPORT);
2092                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2093                                             DRM_MODE_CONNECTOR_SVIDEO,
2094                                             &ddc_i2c,
2095                                             CONNECTOR_OBJECT_ID_SVIDEO,
2096                                             &hpd);
2097                 break;
2098         case CT_SAM440EP:
2099                 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2100                          rdev->mode_info.connector_table);
2101                 /* LVDS */
2102                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2103                 hpd.hpd = RADEON_HPD_NONE;
2104                 radeon_add_legacy_encoder(dev,
2105                                           radeon_get_encoder_enum(dev,
2106                                                                 ATOM_DEVICE_LCD1_SUPPORT,
2107                                                                 0),
2108                                           ATOM_DEVICE_LCD1_SUPPORT);
2109                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2110                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2111                                             CONNECTOR_OBJECT_ID_LVDS,
2112                                             &hpd);
2113                 /* DVI-I - secondary dac, int tmds */
2114                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2115                 hpd.hpd = RADEON_HPD_1; /* ??? */
2116                 radeon_add_legacy_encoder(dev,
2117                                           radeon_get_encoder_enum(dev,
2118                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2119                                                                 0),
2120                                           ATOM_DEVICE_DFP1_SUPPORT);
2121                 radeon_add_legacy_encoder(dev,
2122                                           radeon_get_encoder_enum(dev,
2123                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2124                                                                 2),
2125                                           ATOM_DEVICE_CRT2_SUPPORT);
2126                 radeon_add_legacy_connector(dev, 1,
2127                                             ATOM_DEVICE_DFP1_SUPPORT |
2128                                             ATOM_DEVICE_CRT2_SUPPORT,
2129                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2130                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2131                                             &hpd);
2132                 /* VGA - primary dac */
2133                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2134                 hpd.hpd = RADEON_HPD_NONE;
2135                 radeon_add_legacy_encoder(dev,
2136                                           radeon_get_encoder_enum(dev,
2137                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2138                                                                 1),
2139                                           ATOM_DEVICE_CRT1_SUPPORT);
2140                 radeon_add_legacy_connector(dev, 2,
2141                                             ATOM_DEVICE_CRT1_SUPPORT,
2142                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2143                                             CONNECTOR_OBJECT_ID_VGA,
2144                                             &hpd);
2145                 /* TV - TV DAC */
2146                 ddc_i2c.valid = false;
2147                 hpd.hpd = RADEON_HPD_NONE;
2148                 radeon_add_legacy_encoder(dev,
2149                                           radeon_get_encoder_enum(dev,
2150                                                                 ATOM_DEVICE_TV1_SUPPORT,
2151                                                                 2),
2152                                           ATOM_DEVICE_TV1_SUPPORT);
2153                 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2154                                             DRM_MODE_CONNECTOR_SVIDEO,
2155                                             &ddc_i2c,
2156                                             CONNECTOR_OBJECT_ID_SVIDEO,
2157                                             &hpd);
2158                 break;
2159         case CT_MAC_G4_SILVER:
2160                 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2161                          rdev->mode_info.connector_table);
2162                 /* DVI-I - tv dac, int tmds */
2163                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2164                 hpd.hpd = RADEON_HPD_1; /* ??? */
2165                 radeon_add_legacy_encoder(dev,
2166                                           radeon_get_encoder_enum(dev,
2167                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2168                                                                 0),
2169                                           ATOM_DEVICE_DFP1_SUPPORT);
2170                 radeon_add_legacy_encoder(dev,
2171                                           radeon_get_encoder_enum(dev,
2172                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2173                                                                 2),
2174                                           ATOM_DEVICE_CRT2_SUPPORT);
2175                 radeon_add_legacy_connector(dev, 0,
2176                                             ATOM_DEVICE_DFP1_SUPPORT |
2177                                             ATOM_DEVICE_CRT2_SUPPORT,
2178                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2179                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2180                                             &hpd);
2181                 /* VGA - primary dac */
2182                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2183                 hpd.hpd = RADEON_HPD_NONE;
2184                 radeon_add_legacy_encoder(dev,
2185                                           radeon_get_encoder_enum(dev,
2186                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2187                                                                 1),
2188                                           ATOM_DEVICE_CRT1_SUPPORT);
2189                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2190                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2191                                             CONNECTOR_OBJECT_ID_VGA,
2192                                             &hpd);
2193                 /* TV - TV DAC */
2194                 ddc_i2c.valid = false;
2195                 hpd.hpd = RADEON_HPD_NONE;
2196                 radeon_add_legacy_encoder(dev,
2197                                           radeon_get_encoder_enum(dev,
2198                                                                 ATOM_DEVICE_TV1_SUPPORT,
2199                                                                 2),
2200                                           ATOM_DEVICE_TV1_SUPPORT);
2201                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2202                                             DRM_MODE_CONNECTOR_SVIDEO,
2203                                             &ddc_i2c,
2204                                             CONNECTOR_OBJECT_ID_SVIDEO,
2205                                             &hpd);
2206                 break;
2207         default:
2208                 DRM_INFO("Connector table: %d (invalid)\n",
2209                          rdev->mode_info.connector_table);
2210                 return false;
2211         }
2212
2213         radeon_link_encoder_connector(dev);
2214
2215         return true;
2216 }
2217
2218 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2219                                        int bios_index,
2220                                        enum radeon_combios_connector
2221                                        *legacy_connector,
2222                                        struct radeon_i2c_bus_rec *ddc_i2c,
2223                                        struct radeon_hpd *hpd)
2224 {
2225
2226         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2227            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2228         if (dev->pdev->device == 0x515e &&
2229             dev->pdev->subsystem_vendor == 0x1014) {
2230                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2231                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2232                         return false;
2233         }
2234
2235         /* X300 card with extra non-existent DVI port */
2236         if (dev->pdev->device == 0x5B60 &&
2237             dev->pdev->subsystem_vendor == 0x17af &&
2238             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2239                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2240                         return false;
2241         }
2242
2243         return true;
2244 }
2245
2246 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2247 {
2248         /* Acer 5102 has non-existent TV port */
2249         if (dev->pdev->device == 0x5975 &&
2250             dev->pdev->subsystem_vendor == 0x1025 &&
2251             dev->pdev->subsystem_device == 0x009f)
2252                 return false;
2253
2254         /* HP dc5750 has non-existent TV port */
2255         if (dev->pdev->device == 0x5974 &&
2256             dev->pdev->subsystem_vendor == 0x103c &&
2257             dev->pdev->subsystem_device == 0x280a)
2258                 return false;
2259
2260         /* MSI S270 has non-existent TV port */
2261         if (dev->pdev->device == 0x5955 &&
2262             dev->pdev->subsystem_vendor == 0x1462 &&
2263             dev->pdev->subsystem_device == 0x0131)
2264                 return false;
2265
2266         return true;
2267 }
2268
2269 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2270 {
2271         struct radeon_device *rdev = dev->dev_private;
2272         uint32_t ext_tmds_info;
2273
2274         if (rdev->flags & RADEON_IS_IGP) {
2275                 if (is_dvi_d)
2276                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2277                 else
2278                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2279         }
2280         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2281         if (ext_tmds_info) {
2282                 uint8_t rev = RBIOS8(ext_tmds_info);
2283                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2284                 if (rev >= 3) {
2285                         if (is_dvi_d)
2286                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2287                         else
2288                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2289                 } else {
2290                         if (flags & 1) {
2291                                 if (is_dvi_d)
2292                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2293                                 else
2294                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2295                         }
2296                 }
2297         }
2298         if (is_dvi_d)
2299                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2300         else
2301                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2302 }
2303
2304 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2305 {
2306         struct radeon_device *rdev = dev->dev_private;
2307         uint32_t conn_info, entry, devices;
2308         uint16_t tmp, connector_object_id;
2309         enum radeon_combios_ddc ddc_type;
2310         enum radeon_combios_connector connector;
2311         int i = 0;
2312         struct radeon_i2c_bus_rec ddc_i2c;
2313         struct radeon_hpd hpd;
2314
2315         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2316         if (conn_info) {
2317                 for (i = 0; i < 4; i++) {
2318                         entry = conn_info + 2 + i * 2;
2319
2320                         if (!RBIOS16(entry))
2321                                 break;
2322
2323                         tmp = RBIOS16(entry);
2324
2325                         connector = (tmp >> 12) & 0xf;
2326
2327                         ddc_type = (tmp >> 8) & 0xf;
2328                         if (ddc_type == 5)
2329                                 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2330                         else
2331                                 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2332
2333                         switch (connector) {
2334                         case CONNECTOR_PROPRIETARY_LEGACY:
2335                         case CONNECTOR_DVI_I_LEGACY:
2336                         case CONNECTOR_DVI_D_LEGACY:
2337                                 if ((tmp >> 4) & 0x1)
2338                                         hpd.hpd = RADEON_HPD_2;
2339                                 else
2340                                         hpd.hpd = RADEON_HPD_1;
2341                                 break;
2342                         default:
2343                                 hpd.hpd = RADEON_HPD_NONE;
2344                                 break;
2345                         }
2346
2347                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2348                                                         &ddc_i2c, &hpd))
2349                                 continue;
2350
2351                         switch (connector) {
2352                         case CONNECTOR_PROPRIETARY_LEGACY:
2353                                 if ((tmp >> 4) & 0x1)
2354                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2355                                 else
2356                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2357                                 radeon_add_legacy_encoder(dev,
2358                                                           radeon_get_encoder_enum
2359                                                           (dev, devices, 0),
2360                                                           devices);
2361                                 radeon_add_legacy_connector(dev, i, devices,
2362                                                             legacy_connector_convert
2363                                                             [connector],
2364                                                             &ddc_i2c,
2365                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2366                                                             &hpd);
2367                                 break;
2368                         case CONNECTOR_CRT_LEGACY:
2369                                 if (tmp & 0x1) {
2370                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2371                                         radeon_add_legacy_encoder(dev,
2372                                                                   radeon_get_encoder_enum
2373                                                                   (dev,
2374                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2375                                                                    2),
2376                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2377                                 } else {
2378                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2379                                         radeon_add_legacy_encoder(dev,
2380                                                                   radeon_get_encoder_enum
2381                                                                   (dev,
2382                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2383                                                                    1),
2384                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2385                                 }
2386                                 radeon_add_legacy_connector(dev,
2387                                                             i,
2388                                                             devices,
2389                                                             legacy_connector_convert
2390                                                             [connector],
2391                                                             &ddc_i2c,
2392                                                             CONNECTOR_OBJECT_ID_VGA,
2393                                                             &hpd);
2394                                 break;
2395                         case CONNECTOR_DVI_I_LEGACY:
2396                                 devices = 0;
2397                                 if (tmp & 0x1) {
2398                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2399                                         radeon_add_legacy_encoder(dev,
2400                                                                   radeon_get_encoder_enum
2401                                                                   (dev,
2402                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2403                                                                    2),
2404                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2405                                 } else {
2406                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2407                                         radeon_add_legacy_encoder(dev,
2408                                                                   radeon_get_encoder_enum
2409                                                                   (dev,
2410                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2411                                                                    1),
2412                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2413                                 }
2414                                 /* RV100 board with external TDMS bit mis-set.
2415                                  * Actually uses internal TMDS, clear the bit.
2416                                  */
2417                                 if (dev->pdev->device == 0x5159 &&
2418                                     dev->pdev->subsystem_vendor == 0x1014 &&
2419                                     dev->pdev->subsystem_device == 0x029A) {
2420                                         tmp &= ~(1 << 4);
2421                                 }
2422                                 if ((tmp >> 4) & 0x1) {
2423                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2424                                         radeon_add_legacy_encoder(dev,
2425                                                                   radeon_get_encoder_enum
2426                                                                   (dev,
2427                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2428                                                                    0),
2429                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2430                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2431                                 } else {
2432                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2433                                         radeon_add_legacy_encoder(dev,
2434                                                                   radeon_get_encoder_enum
2435                                                                   (dev,
2436                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2437                                                                    0),
2438                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2439                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2440                                 }
2441                                 radeon_add_legacy_connector(dev,
2442                                                             i,
2443                                                             devices,
2444                                                             legacy_connector_convert
2445                                                             [connector],
2446                                                             &ddc_i2c,
2447                                                             connector_object_id,
2448                                                             &hpd);
2449                                 break;
2450                         case CONNECTOR_DVI_D_LEGACY:
2451                                 if ((tmp >> 4) & 0x1) {
2452                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2453                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2454                                 } else {
2455                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2456                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2457                                 }
2458                                 radeon_add_legacy_encoder(dev,
2459                                                           radeon_get_encoder_enum
2460                                                           (dev, devices, 0),
2461                                                           devices);
2462                                 radeon_add_legacy_connector(dev, i, devices,
2463                                                             legacy_connector_convert
2464                                                             [connector],
2465                                                             &ddc_i2c,
2466                                                             connector_object_id,
2467                                                             &hpd);
2468                                 break;
2469                         case CONNECTOR_CTV_LEGACY:
2470                         case CONNECTOR_STV_LEGACY:
2471                                 radeon_add_legacy_encoder(dev,
2472                                                           radeon_get_encoder_enum
2473                                                           (dev,
2474                                                            ATOM_DEVICE_TV1_SUPPORT,
2475                                                            2),
2476                                                           ATOM_DEVICE_TV1_SUPPORT);
2477                                 radeon_add_legacy_connector(dev, i,
2478                                                             ATOM_DEVICE_TV1_SUPPORT,
2479                                                             legacy_connector_convert
2480                                                             [connector],
2481                                                             &ddc_i2c,
2482                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2483                                                             &hpd);
2484                                 break;
2485                         default:
2486                                 DRM_ERROR("Unknown connector type: %d\n",
2487                                           connector);
2488                                 continue;
2489                         }
2490
2491                 }
2492         } else {
2493                 uint16_t tmds_info =
2494                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2495                 if (tmds_info) {
2496                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2497
2498                         radeon_add_legacy_encoder(dev,
2499                                                   radeon_get_encoder_enum(dev,
2500                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2501                                                                         1),
2502                                                   ATOM_DEVICE_CRT1_SUPPORT);
2503                         radeon_add_legacy_encoder(dev,
2504                                                   radeon_get_encoder_enum(dev,
2505                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2506                                                                         0),
2507                                                   ATOM_DEVICE_DFP1_SUPPORT);
2508
2509                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2510                         hpd.hpd = RADEON_HPD_1;
2511                         radeon_add_legacy_connector(dev,
2512                                                     0,
2513                                                     ATOM_DEVICE_CRT1_SUPPORT |
2514                                                     ATOM_DEVICE_DFP1_SUPPORT,
2515                                                     DRM_MODE_CONNECTOR_DVII,
2516                                                     &ddc_i2c,
2517                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2518                                                     &hpd);
2519                 } else {
2520                         uint16_t crt_info =
2521                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2522                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2523                         if (crt_info) {
2524                                 radeon_add_legacy_encoder(dev,
2525                                                           radeon_get_encoder_enum(dev,
2526                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2527                                                                                 1),
2528                                                           ATOM_DEVICE_CRT1_SUPPORT);
2529                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2530                                 hpd.hpd = RADEON_HPD_NONE;
2531                                 radeon_add_legacy_connector(dev,
2532                                                             0,
2533                                                             ATOM_DEVICE_CRT1_SUPPORT,
2534                                                             DRM_MODE_CONNECTOR_VGA,
2535                                                             &ddc_i2c,
2536                                                             CONNECTOR_OBJECT_ID_VGA,
2537                                                             &hpd);
2538                         } else {
2539                                 DRM_DEBUG_KMS("No connector info found\n");
2540                                 return false;
2541                         }
2542                 }
2543         }
2544
2545         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2546                 uint16_t lcd_info =
2547                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2548                 if (lcd_info) {
2549                         uint16_t lcd_ddc_info =
2550                             combios_get_table_offset(dev,
2551                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2552
2553                         radeon_add_legacy_encoder(dev,
2554                                                   radeon_get_encoder_enum(dev,
2555                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2556                                                                         0),
2557                                                   ATOM_DEVICE_LCD1_SUPPORT);
2558
2559                         if (lcd_ddc_info) {
2560                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2561                                 switch (ddc_type) {
2562                                 case DDC_LCD:
2563                                         ddc_i2c =
2564                                                 combios_setup_i2c_bus(rdev,
2565                                                                       DDC_LCD,
2566                                                                       RBIOS32(lcd_ddc_info + 3),
2567                                                                       RBIOS32(lcd_ddc_info + 7));
2568                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2569                                         break;
2570                                 case DDC_GPIO:
2571                                         ddc_i2c =
2572                                                 combios_setup_i2c_bus(rdev,
2573                                                                       DDC_GPIO,
2574                                                                       RBIOS32(lcd_ddc_info + 3),
2575                                                                       RBIOS32(lcd_ddc_info + 7));
2576                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2577                                         break;
2578                                 default:
2579                                         ddc_i2c =
2580                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2581                                         break;
2582                                 }
2583                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2584                         } else
2585                                 ddc_i2c.valid = false;
2586
2587                         hpd.hpd = RADEON_HPD_NONE;
2588                         radeon_add_legacy_connector(dev,
2589                                                     5,
2590                                                     ATOM_DEVICE_LCD1_SUPPORT,
2591                                                     DRM_MODE_CONNECTOR_LVDS,
2592                                                     &ddc_i2c,
2593                                                     CONNECTOR_OBJECT_ID_LVDS,
2594                                                     &hpd);
2595                 }
2596         }
2597
2598         /* check TV table */
2599         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2600                 uint32_t tv_info =
2601                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2602                 if (tv_info) {
2603                         if (RBIOS8(tv_info + 6) == 'T') {
2604                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2605                                         hpd.hpd = RADEON_HPD_NONE;
2606                                         ddc_i2c.valid = false;
2607                                         radeon_add_legacy_encoder(dev,
2608                                                                   radeon_get_encoder_enum
2609                                                                   (dev,
2610                                                                    ATOM_DEVICE_TV1_SUPPORT,
2611                                                                    2),
2612                                                                   ATOM_DEVICE_TV1_SUPPORT);
2613                                         radeon_add_legacy_connector(dev, 6,
2614                                                                     ATOM_DEVICE_TV1_SUPPORT,
2615                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2616                                                                     &ddc_i2c,
2617                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2618                                                                     &hpd);
2619                                 }
2620                         }
2621                 }
2622         }
2623
2624         radeon_link_encoder_connector(dev);
2625
2626         return true;
2627 }
2628
2629 static const char *thermal_controller_names[] = {
2630         "NONE",
2631         "lm63",
2632         "adm1032",
2633 };
2634
2635 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2636 {
2637         struct drm_device *dev = rdev->ddev;
2638         u16 offset, misc, misc2 = 0;
2639         u8 rev, blocks, tmp;
2640         int state_index = 0;
2641         struct radeon_i2c_bus_rec i2c_bus;
2642
2643         rdev->pm.default_power_state_index = -1;
2644
2645         /* allocate 2 power states */
2646         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2647         if (rdev->pm.power_state) {
2648                 /* allocate 1 clock mode per state */
2649                 rdev->pm.power_state[0].clock_info =
2650                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2651                 rdev->pm.power_state[1].clock_info =
2652                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2653                 if (!rdev->pm.power_state[0].clock_info ||
2654                     !rdev->pm.power_state[1].clock_info)
2655                         goto pm_failed;
2656         } else
2657                 goto pm_failed;
2658
2659         /* check for a thermal chip */
2660         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2661         if (offset) {
2662                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2663
2664                 rev = RBIOS8(offset);
2665
2666                 if (rev == 0) {
2667                         thermal_controller = RBIOS8(offset + 3);
2668                         gpio = RBIOS8(offset + 4) & 0x3f;
2669                         i2c_addr = RBIOS8(offset + 5);
2670                 } else if (rev == 1) {
2671                         thermal_controller = RBIOS8(offset + 4);
2672                         gpio = RBIOS8(offset + 5) & 0x3f;
2673                         i2c_addr = RBIOS8(offset + 6);
2674                 } else if (rev == 2) {
2675                         thermal_controller = RBIOS8(offset + 4);
2676                         gpio = RBIOS8(offset + 5) & 0x3f;
2677                         i2c_addr = RBIOS8(offset + 6);
2678                         clk_bit = RBIOS8(offset + 0xa);
2679                         data_bit = RBIOS8(offset + 0xb);
2680                 }
2681                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2682                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2683                                  thermal_controller_names[thermal_controller],
2684                                  i2c_addr >> 1);
2685                         if (gpio == DDC_LCD) {
2686                                 /* MM i2c */
2687                                 i2c_bus.valid = true;
2688                                 i2c_bus.hw_capable = true;
2689                                 i2c_bus.mm_i2c = true;
2690                                 i2c_bus.i2c_id = 0xa0;
2691                         } else if (gpio == DDC_GPIO)
2692                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2693                         else
2694                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2695                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2696                         if (rdev->pm.i2c_bus) {
2697                                 struct i2c_board_info info = { };
2698                                 const char *name = thermal_controller_names[thermal_controller];
2699                                 info.addr = i2c_addr >> 1;
2700                                 strlcpy(info.type, name, sizeof(info.type));
2701                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2702                         }
2703                 }
2704         } else {
2705                 /* boards with a thermal chip, but no overdrive table */
2706
2707                 /* Asus 9600xt has an f75375 on the monid bus */
2708                 if ((dev->pdev->device == 0x4152) &&
2709                     (dev->pdev->subsystem_vendor == 0x1043) &&
2710                     (dev->pdev->subsystem_device == 0xc002)) {
2711                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2712                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2713                         if (rdev->pm.i2c_bus) {
2714                                 struct i2c_board_info info = { };
2715                                 const char *name = "f75375";
2716                                 info.addr = 0x28;
2717                                 strlcpy(info.type, name, sizeof(info.type));
2718                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2719                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2720                                          name, info.addr);
2721                         }
2722                 }
2723         }
2724
2725         if (rdev->flags & RADEON_IS_MOBILITY) {
2726                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2727                 if (offset) {
2728                         rev = RBIOS8(offset);
2729                         blocks = RBIOS8(offset + 0x2);
2730                         /* power mode 0 tends to be the only valid one */
2731                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2732                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2733                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2734                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2735                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2736                                 goto default_mode;
2737                         rdev->pm.power_state[state_index].type =
2738                                 POWER_STATE_TYPE_BATTERY;
2739                         misc = RBIOS16(offset + 0x5 + 0x0);
2740                         if (rev > 4)
2741                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2742                         rdev->pm.power_state[state_index].misc = misc;
2743                         rdev->pm.power_state[state_index].misc2 = misc2;
2744                         if (misc & 0x4) {
2745                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2746                                 if (misc & 0x8)
2747                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2748                                                 true;
2749                                 else
2750                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2751                                                 false;
2752                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2753                                 if (rev < 6) {
2754                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2755                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2756                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2757                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2758                                 } else {
2759                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2760                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2761                                         if (entries && voltage_table_offset) {
2762                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2763                                                         RBIOS16(voltage_table_offset) * 4;
2764                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2765                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2766                                         } else
2767                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2768                                 }
2769                                 switch ((misc2 & 0x700) >> 8) {
2770                                 case 0:
2771                                 default:
2772                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2773                                         break;
2774                                 case 1:
2775                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2776                                         break;
2777                                 case 2:
2778                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2779                                         break;
2780                                 case 3:
2781                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2782                                         break;
2783                                 case 4:
2784                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2785                                         break;
2786                                 }
2787                         } else
2788                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2789                         if (rev > 6)
2790                                 rdev->pm.power_state[state_index].pcie_lanes =
2791                                         RBIOS8(offset + 0x5 + 0x10);
2792                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2793                         state_index++;
2794                 } else {
2795                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2796                 }
2797         } else {
2798                 /* XXX figure out some good default low power mode for desktop cards */
2799         }
2800
2801 default_mode:
2802         /* add the default mode */
2803         rdev->pm.power_state[state_index].type =
2804                 POWER_STATE_TYPE_DEFAULT;
2805         rdev->pm.power_state[state_index].num_clock_modes = 1;
2806         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2807         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2808         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2809         if ((state_index > 0) &&
2810             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2811                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2812                         rdev->pm.power_state[0].clock_info[0].voltage;
2813         else
2814                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2815         rdev->pm.power_state[state_index].pcie_lanes = 16;
2816         rdev->pm.power_state[state_index].flags = 0;
2817         rdev->pm.default_power_state_index = state_index;
2818         rdev->pm.num_power_states = state_index + 1;
2819
2820         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2821         rdev->pm.current_clock_mode_index = 0;
2822         return;
2823
2824 pm_failed:
2825         rdev->pm.default_power_state_index = state_index;
2826         rdev->pm.num_power_states = 0;
2827
2828         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2829         rdev->pm.current_clock_mode_index = 0;
2830 }
2831
2832 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2833 {
2834         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2835         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2836
2837         if (!tmds)
2838                 return;
2839
2840         switch (tmds->dvo_chip) {
2841         case DVO_SIL164:
2842                 /* sil 164 */
2843                 radeon_i2c_put_byte(tmds->i2c_bus,
2844                                     tmds->slave_addr,
2845                                     0x08, 0x30);
2846                 radeon_i2c_put_byte(tmds->i2c_bus,
2847                                        tmds->slave_addr,
2848                                        0x09, 0x00);
2849                 radeon_i2c_put_byte(tmds->i2c_bus,
2850                                     tmds->slave_addr,
2851                                     0x0a, 0x90);
2852                 radeon_i2c_put_byte(tmds->i2c_bus,
2853                                     tmds->slave_addr,
2854                                     0x0c, 0x89);
2855                 radeon_i2c_put_byte(tmds->i2c_bus,
2856                                        tmds->slave_addr,
2857                                        0x08, 0x3b);
2858                 break;
2859         case DVO_SIL1178:
2860                 /* sil 1178 - untested */
2861                 /*
2862                  * 0x0f, 0x44
2863                  * 0x0f, 0x4c
2864                  * 0x0e, 0x01
2865                  * 0x0a, 0x80
2866                  * 0x09, 0x30
2867                  * 0x0c, 0xc9
2868                  * 0x0d, 0x70
2869                  * 0x08, 0x32
2870                  * 0x08, 0x33
2871                  */
2872                 break;
2873         default:
2874                 break;
2875         }
2876
2877 }
2878
2879 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2880 {
2881         struct drm_device *dev = encoder->dev;
2882         struct radeon_device *rdev = dev->dev_private;
2883         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2884         uint16_t offset;
2885         uint8_t blocks, slave_addr, rev;
2886         uint32_t index, id;
2887         uint32_t reg, val, and_mask, or_mask;
2888         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2889
2890         if (!tmds)
2891                 return false;
2892
2893         if (rdev->flags & RADEON_IS_IGP) {
2894                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2895                 rev = RBIOS8(offset);
2896                 if (offset) {
2897                         rev = RBIOS8(offset);
2898                         if (rev > 1) {
2899                                 blocks = RBIOS8(offset + 3);
2900                                 index = offset + 4;
2901                                 while (blocks > 0) {
2902                                         id = RBIOS16(index);
2903                                         index += 2;
2904                                         switch (id >> 13) {
2905                                         case 0:
2906                                                 reg = (id & 0x1fff) * 4;
2907                                                 val = RBIOS32(index);
2908                                                 index += 4;
2909                                                 WREG32(reg, val);
2910                                                 break;
2911                                         case 2:
2912                                                 reg = (id & 0x1fff) * 4;
2913                                                 and_mask = RBIOS32(index);
2914                                                 index += 4;
2915                                                 or_mask = RBIOS32(index);
2916                                                 index += 4;
2917                                                 val = RREG32(reg);
2918                                                 val = (val & and_mask) | or_mask;
2919                                                 WREG32(reg, val);
2920                                                 break;
2921                                         case 3:
2922                                                 val = RBIOS16(index);
2923                                                 index += 2;
2924                                                 udelay(val);
2925                                                 break;
2926                                         case 4:
2927                                                 val = RBIOS16(index);
2928                                                 index += 2;
2929                                                 mdelay(val);
2930                                                 break;
2931                                         case 6:
2932                                                 slave_addr = id & 0xff;
2933                                                 slave_addr >>= 1; /* 7 bit addressing */
2934                                                 index++;
2935                                                 reg = RBIOS8(index);
2936                                                 index++;
2937                                                 val = RBIOS8(index);
2938                                                 index++;
2939                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2940                                                                     slave_addr,
2941                                                                     reg, val);
2942                                                 break;
2943                                         default:
2944                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2945                                                 break;
2946                                         }
2947                                         blocks--;
2948                                 }
2949                                 return true;
2950                         }
2951                 }
2952         } else {
2953                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2954                 if (offset) {
2955                         index = offset + 10;
2956                         id = RBIOS16(index);
2957                         while (id != 0xffff) {
2958                                 index += 2;
2959                                 switch (id >> 13) {
2960                                 case 0:
2961                                         reg = (id & 0x1fff) * 4;
2962                                         val = RBIOS32(index);
2963                                         WREG32(reg, val);
2964                                         break;
2965                                 case 2:
2966                                         reg = (id & 0x1fff) * 4;
2967                                         and_mask = RBIOS32(index);
2968                                         index += 4;
2969                                         or_mask = RBIOS32(index);
2970                                         index += 4;
2971                                         val = RREG32(reg);
2972                                         val = (val & and_mask) | or_mask;
2973                                         WREG32(reg, val);
2974                                         break;
2975                                 case 4:
2976                                         val = RBIOS16(index);
2977                                         index += 2;
2978                                         udelay(val);
2979                                         break;
2980                                 case 5:
2981                                         reg = id & 0x1fff;
2982                                         and_mask = RBIOS32(index);
2983                                         index += 4;
2984                                         or_mask = RBIOS32(index);
2985                                         index += 4;
2986                                         val = RREG32_PLL(reg);
2987                                         val = (val & and_mask) | or_mask;
2988                                         WREG32_PLL(reg, val);
2989                                         break;
2990                                 case 6:
2991                                         reg = id & 0x1fff;
2992                                         val = RBIOS8(index);
2993                                         index += 1;
2994                                         radeon_i2c_put_byte(tmds->i2c_bus,
2995                                                             tmds->slave_addr,
2996                                                             reg, val);
2997                                         break;
2998                                 default:
2999                                         DRM_ERROR("Unknown id %d\n", id >> 13);
3000                                         break;
3001                                 }
3002                                 id = RBIOS16(index);
3003                         }
3004                         return true;
3005                 }
3006         }
3007         return false;
3008 }
3009
3010 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3011 {
3012         struct radeon_device *rdev = dev->dev_private;
3013
3014         if (offset) {
3015                 while (RBIOS16(offset)) {
3016                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3017                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
3018                         uint32_t val, and_mask, or_mask;
3019                         uint32_t tmp;
3020
3021                         offset += 2;
3022                         switch (cmd) {
3023                         case 0:
3024                                 val = RBIOS32(offset);
3025                                 offset += 4;
3026                                 WREG32(addr, val);
3027                                 break;
3028                         case 1:
3029                                 val = RBIOS32(offset);
3030                                 offset += 4;
3031                                 WREG32(addr, val);
3032                                 break;
3033                         case 2:
3034                                 and_mask = RBIOS32(offset);
3035                                 offset += 4;
3036                                 or_mask = RBIOS32(offset);
3037                                 offset += 4;
3038                                 tmp = RREG32(addr);
3039                                 tmp &= and_mask;
3040                                 tmp |= or_mask;
3041                                 WREG32(addr, tmp);
3042                                 break;
3043                         case 3:
3044                                 and_mask = RBIOS32(offset);
3045                                 offset += 4;
3046                                 or_mask = RBIOS32(offset);
3047                                 offset += 4;
3048                                 tmp = RREG32(addr);
3049                                 tmp &= and_mask;
3050                                 tmp |= or_mask;
3051                                 WREG32(addr, tmp);
3052                                 break;
3053                         case 4:
3054                                 val = RBIOS16(offset);
3055                                 offset += 2;
3056                                 udelay(val);
3057                                 break;
3058                         case 5:
3059                                 val = RBIOS16(offset);
3060                                 offset += 2;
3061                                 switch (addr) {
3062                                 case 8:
3063                                         while (val--) {
3064                                                 if (!
3065                                                     (RREG32_PLL
3066                                                      (RADEON_CLK_PWRMGT_CNTL) &
3067                                                      RADEON_MC_BUSY))
3068                                                         break;
3069                                         }
3070                                         break;
3071                                 case 9:
3072                                         while (val--) {
3073                                                 if ((RREG32(RADEON_MC_STATUS) &
3074                                                      RADEON_MC_IDLE))
3075                                                         break;
3076                                         }
3077                                         break;
3078                                 default:
3079                                         break;
3080                                 }
3081                                 break;
3082                         default:
3083                                 break;
3084                         }
3085                 }
3086         }
3087 }
3088
3089 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3090 {
3091         struct radeon_device *rdev = dev->dev_private;
3092
3093         if (offset) {
3094                 while (RBIOS8(offset)) {
3095                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3096                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3097                         uint32_t val, shift, tmp;
3098                         uint32_t and_mask, or_mask;
3099
3100                         offset++;
3101                         switch (cmd) {
3102                         case 0:
3103                                 val = RBIOS32(offset);
3104                                 offset += 4;
3105                                 WREG32_PLL(addr, val);
3106                                 break;
3107                         case 1:
3108                                 shift = RBIOS8(offset) * 8;
3109                                 offset++;
3110                                 and_mask = RBIOS8(offset) << shift;
3111                                 and_mask |= ~(0xff << shift);
3112                                 offset++;
3113                                 or_mask = RBIOS8(offset) << shift;
3114                                 offset++;
3115                                 tmp = RREG32_PLL(addr);
3116                                 tmp &= and_mask;
3117                                 tmp |= or_mask;
3118                                 WREG32_PLL(addr, tmp);
3119                                 break;
3120                         case 2:
3121                         case 3:
3122                                 tmp = 1000;
3123                                 switch (addr) {
3124                                 case 1:
3125                                         udelay(150);
3126                                         break;
3127                                 case 2:
3128                                         mdelay(1);
3129                                         break;
3130                                 case 3:
3131                                         while (tmp--) {
3132                                                 if (!
3133                                                     (RREG32_PLL
3134                                                      (RADEON_CLK_PWRMGT_CNTL) &
3135                                                      RADEON_MC_BUSY))
3136                                                         break;
3137                                         }
3138                                         break;
3139                                 case 4:
3140                                         while (tmp--) {
3141                                                 if (RREG32_PLL
3142                                                     (RADEON_CLK_PWRMGT_CNTL) &
3143                                                     RADEON_DLL_READY)
3144                                                         break;
3145                                         }
3146                                         break;
3147                                 case 5:
3148                                         tmp =
3149                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3150                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3151 #if 0
3152                                                 uint32_t mclk_cntl =
3153                                                     RREG32_PLL
3154                                                     (RADEON_MCLK_CNTL);
3155                                                 mclk_cntl &= 0xffff0000;
3156                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3157                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3158                                                            mclk_cntl);
3159                                                 mdelay(10);
3160 #endif
3161                                                 WREG32_PLL
3162                                                     (RADEON_CLK_PWRMGT_CNTL,
3163                                                      tmp &
3164                                                      ~RADEON_CG_NO1_DEBUG_0);
3165                                                 mdelay(10);
3166                                         }
3167                                         break;
3168                                 default:
3169                                         break;
3170                                 }
3171                                 break;
3172                         default:
3173                                 break;
3174                         }
3175                 }
3176         }
3177 }
3178
3179 static void combios_parse_ram_reset_table(struct drm_device *dev,
3180                                           uint16_t offset)
3181 {
3182         struct radeon_device *rdev = dev->dev_private;
3183         uint32_t tmp;
3184
3185         if (offset) {
3186                 uint8_t val = RBIOS8(offset);
3187                 while (val != 0xff) {
3188                         offset++;
3189
3190                         if (val == 0x0f) {
3191                                 uint32_t channel_complete_mask;
3192
3193                                 if (ASIC_IS_R300(rdev))
3194                                         channel_complete_mask =
3195                                             R300_MEM_PWRUP_COMPLETE;
3196                                 else
3197                                         channel_complete_mask =
3198                                             RADEON_MEM_PWRUP_COMPLETE;
3199                                 tmp = 20000;
3200                                 while (tmp--) {
3201                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3202                                              channel_complete_mask) ==
3203                                             channel_complete_mask)
3204                                                 break;
3205                                 }
3206                         } else {
3207                                 uint32_t or_mask = RBIOS16(offset);
3208                                 offset += 2;
3209
3210                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3211                                 tmp &= RADEON_SDRAM_MODE_MASK;
3212                                 tmp |= or_mask;
3213                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3214
3215                                 or_mask = val << 24;
3216                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3217                                 tmp &= RADEON_B3MEM_RESET_MASK;
3218                                 tmp |= or_mask;
3219                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3220                         }
3221                         val = RBIOS8(offset);
3222                 }
3223         }
3224 }
3225
3226 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3227                                    int mem_addr_mapping)
3228 {
3229         struct radeon_device *rdev = dev->dev_private;
3230         uint32_t mem_cntl;
3231         uint32_t mem_size;
3232         uint32_t addr = 0;
3233
3234         mem_cntl = RREG32(RADEON_MEM_CNTL);
3235         if (mem_cntl & RV100_HALF_MODE)
3236                 ram /= 2;
3237         mem_size = ram;
3238         mem_cntl &= ~(0xff << 8);
3239         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3240         WREG32(RADEON_MEM_CNTL, mem_cntl);
3241         RREG32(RADEON_MEM_CNTL);
3242
3243         /* sdram reset ? */
3244
3245         /* something like this????  */
3246         while (ram--) {
3247                 addr = ram * 1024 * 1024;
3248                 /* write to each page */
3249                 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3250                 /* read back and verify */
3251                 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3252                         return 0;
3253         }
3254
3255         return mem_size;
3256 }
3257
3258 static void combios_write_ram_size(struct drm_device *dev)
3259 {
3260         struct radeon_device *rdev = dev->dev_private;
3261         uint8_t rev;
3262         uint16_t offset;
3263         uint32_t mem_size = 0;
3264         uint32_t mem_cntl = 0;
3265
3266         /* should do something smarter here I guess... */
3267         if (rdev->flags & RADEON_IS_IGP)
3268                 return;
3269
3270         /* first check detected mem table */
3271         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3272         if (offset) {
3273                 rev = RBIOS8(offset);
3274                 if (rev < 3) {
3275                         mem_cntl = RBIOS32(offset + 1);
3276                         mem_size = RBIOS16(offset + 5);
3277                         if ((rdev->family < CHIP_R200) &&
3278                             !ASIC_IS_RN50(rdev))
3279                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3280                 }
3281         }
3282
3283         if (!mem_size) {
3284                 offset =
3285                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3286                 if (offset) {
3287                         rev = RBIOS8(offset - 1);
3288                         if (rev < 1) {
3289                                 if ((rdev->family < CHIP_R200)
3290                                     && !ASIC_IS_RN50(rdev)) {
3291                                         int ram = 0;
3292                                         int mem_addr_mapping = 0;
3293
3294                                         while (RBIOS8(offset)) {
3295                                                 ram = RBIOS8(offset);
3296                                                 mem_addr_mapping =
3297                                                     RBIOS8(offset + 1);
3298                                                 if (mem_addr_mapping != 0x25)
3299                                                         ram *= 2;
3300                                                 mem_size =
3301                                                     combios_detect_ram(dev, ram,
3302                                                                        mem_addr_mapping);
3303                                                 if (mem_size)
3304                                                         break;
3305                                                 offset += 2;
3306                                         }
3307                                 } else
3308                                         mem_size = RBIOS8(offset);
3309                         } else {
3310                                 mem_size = RBIOS8(offset);
3311                                 mem_size *= 2;  /* convert to MB */
3312                         }
3313                 }
3314         }
3315
3316         mem_size *= (1024 * 1024);      /* convert to bytes */
3317         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3318 }
3319
3320 void radeon_combios_asic_init(struct drm_device *dev)
3321 {
3322         struct radeon_device *rdev = dev->dev_private;
3323         uint16_t table;
3324
3325         /* port hardcoded mac stuff from radeonfb */
3326         if (rdev->bios == NULL)
3327                 return;
3328
3329         /* ASIC INIT 1 */
3330         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3331         if (table)
3332                 combios_parse_mmio_table(dev, table);
3333
3334         /* PLL INIT */
3335         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3336         if (table)
3337                 combios_parse_pll_table(dev, table);
3338
3339         /* ASIC INIT 2 */
3340         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3341         if (table)
3342                 combios_parse_mmio_table(dev, table);
3343
3344         if (!(rdev->flags & RADEON_IS_IGP)) {
3345                 /* ASIC INIT 4 */
3346                 table =
3347                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3348                 if (table)
3349                         combios_parse_mmio_table(dev, table);
3350
3351                 /* RAM RESET */
3352                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3353                 if (table)
3354                         combios_parse_ram_reset_table(dev, table);
3355
3356                 /* ASIC INIT 3 */
3357                 table =
3358                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3359                 if (table)
3360                         combios_parse_mmio_table(dev, table);
3361
3362                 /* write CONFIG_MEMSIZE */
3363                 combios_write_ram_size(dev);
3364         }
3365
3366         /* quirk for rs4xx HP nx6125 laptop to make it resume
3367          * - it hangs on resume inside the dynclk 1 table.
3368          */
3369         if (rdev->family == CHIP_RS480 &&
3370             rdev->pdev->subsystem_vendor == 0x103c &&
3371             rdev->pdev->subsystem_device == 0x308b)
3372                 return;
3373
3374         /* quirk for rs4xx HP dv5000 laptop to make it resume
3375          * - it hangs on resume inside the dynclk 1 table.
3376          */
3377         if (rdev->family == CHIP_RS480 &&
3378             rdev->pdev->subsystem_vendor == 0x103c &&
3379             rdev->pdev->subsystem_device == 0x30a4)
3380                 return;
3381
3382         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3383          * - it hangs on resume inside the dynclk 1 table.
3384          */
3385         if (rdev->family == CHIP_RS480 &&
3386             rdev->pdev->subsystem_vendor == 0x103c &&
3387             rdev->pdev->subsystem_device == 0x30ae)
3388                 return;
3389
3390         /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3391          * - it hangs on resume inside the dynclk 1 table.
3392          */
3393         if (rdev->family == CHIP_RS480 &&
3394             rdev->pdev->subsystem_vendor == 0x103c &&
3395             rdev->pdev->subsystem_device == 0x280a)
3396                 return;
3397
3398         /* DYN CLK 1 */
3399         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3400         if (table)
3401                 combios_parse_pll_table(dev, table);
3402
3403 }
3404
3405 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3406 {
3407         struct radeon_device *rdev = dev->dev_private;
3408         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3409
3410         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3411         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3412         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3413
3414         /* let the bios control the backlight */
3415         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3416
3417         /* tell the bios not to handle mode switching */
3418         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3419                            RADEON_ACC_MODE_CHANGE);
3420
3421         /* tell the bios a driver is loaded */
3422         bios_7_scratch |= RADEON_DRV_LOADED;
3423
3424         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3425         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3426         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3427 }
3428
3429 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3430 {
3431         struct drm_device *dev = encoder->dev;
3432         struct radeon_device *rdev = dev->dev_private;
3433         uint32_t bios_6_scratch;
3434
3435         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3436
3437         if (lock)
3438                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3439         else
3440                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3441
3442         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3443 }
3444
3445 void
3446 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3447                                       struct drm_encoder *encoder,
3448                                       bool connected)
3449 {
3450         struct drm_device *dev = connector->dev;
3451         struct radeon_device *rdev = dev->dev_private;
3452         struct radeon_connector *radeon_connector =
3453             to_radeon_connector(connector);
3454         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3455         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3456         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3457
3458         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3459             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3460                 if (connected) {
3461                         DRM_DEBUG_KMS("TV1 connected\n");
3462                         /* fix me */
3463                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3464                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3465                         bios_5_scratch |= RADEON_TV1_ON;
3466                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3467                 } else {
3468                         DRM_DEBUG_KMS("TV1 disconnected\n");
3469                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3470                         bios_5_scratch &= ~RADEON_TV1_ON;
3471                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3472                 }
3473         }
3474         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3475             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3476                 if (connected) {
3477                         DRM_DEBUG_KMS("LCD1 connected\n");
3478                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3479                         bios_5_scratch |= RADEON_LCD1_ON;
3480                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3481                 } else {
3482                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3483                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3484                         bios_5_scratch &= ~RADEON_LCD1_ON;
3485                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3486                 }
3487         }
3488         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3489             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3490                 if (connected) {
3491                         DRM_DEBUG_KMS("CRT1 connected\n");
3492                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3493                         bios_5_scratch |= RADEON_CRT1_ON;
3494                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3495                 } else {
3496                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3497                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3498                         bios_5_scratch &= ~RADEON_CRT1_ON;
3499                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3500                 }
3501         }
3502         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3503             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3504                 if (connected) {
3505                         DRM_DEBUG_KMS("CRT2 connected\n");
3506                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3507                         bios_5_scratch |= RADEON_CRT2_ON;
3508                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3509                 } else {
3510                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3511                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3512                         bios_5_scratch &= ~RADEON_CRT2_ON;
3513                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3514                 }
3515         }
3516         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3517             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3518                 if (connected) {
3519                         DRM_DEBUG_KMS("DFP1 connected\n");
3520                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3521                         bios_5_scratch |= RADEON_DFP1_ON;
3522                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3523                 } else {
3524                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3525                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3526                         bios_5_scratch &= ~RADEON_DFP1_ON;
3527                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3528                 }
3529         }
3530         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3531             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3532                 if (connected) {
3533                         DRM_DEBUG_KMS("DFP2 connected\n");
3534                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3535                         bios_5_scratch |= RADEON_DFP2_ON;
3536                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3537                 } else {
3538                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3539                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3540                         bios_5_scratch &= ~RADEON_DFP2_ON;
3541                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3542                 }
3543         }
3544         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3545         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3546 }
3547
3548 void
3549 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3550 {
3551         struct drm_device *dev = encoder->dev;
3552         struct radeon_device *rdev = dev->dev_private;
3553         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3554         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3555
3556         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3557                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3558                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3559         }
3560         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3561                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3562                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3563         }
3564         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3565                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3566                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3567         }
3568         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3569                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3570                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3571         }
3572         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3573                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3574                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3575         }
3576         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3577                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3578                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3579         }
3580         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3581 }
3582
3583 void
3584 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3585 {
3586         struct drm_device *dev = encoder->dev;
3587         struct radeon_device *rdev = dev->dev_private;
3588         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3589         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3590
3591         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3592                 if (on)
3593                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3594                 else
3595                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3596         }
3597         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3598                 if (on)
3599                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3600                 else
3601                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3602         }
3603         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3604                 if (on)
3605                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3606                 else
3607                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3608         }
3609         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3610                 if (on)
3611                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3612                 else
3613                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3614         }
3615         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3616 }