drivers/mtd/nand/denali.h

   1 /*
   2  * NAND Flash Controller Device Driver
   3  * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  */
  19
  20 #ifndef __DENALI_H__
  21 #define __DENALI_H__
  22
  23 #include <linux/bitops.h>
  24 #include <linux/mtd/nand.h>
  25
  26 #define DEVICE_RESET                            0x0
  27 #define     DEVICE_RESET__BANK(bank)                    BIT(bank)
  28
  29 #define TRANSFER_SPARE_REG                      0x10
  30 #define     TRANSFER_SPARE_REG__FLAG                    BIT(0)
  31
  32 #define LOAD_WAIT_CNT                           0x20
  33 #define     LOAD_WAIT_CNT__VALUE                        GENMASK(15, 0)
  34
  35 #define PROGRAM_WAIT_CNT                        0x30
  36 #define     PROGRAM_WAIT_CNT__VALUE                     GENMASK(15, 0)
  37
  38 #define ERASE_WAIT_CNT                          0x40
  39 #define     ERASE_WAIT_CNT__VALUE                       GENMASK(15, 0)
  40
  41 #define INT_MON_CYCCNT                          0x50
  42 #define     INT_MON_CYCCNT__VALUE                       GENMASK(15, 0)
  43
  44 #define RB_PIN_ENABLED                          0x60
  45 #define     RB_PIN_ENABLED__BANK(bank)                  BIT(bank)
  46
  47 #define MULTIPLANE_OPERATION                    0x70
  48 #define     MULTIPLANE_OPERATION__FLAG                  BIT(0)
  49
  50 #define MULTIPLANE_READ_ENABLE                  0x80
  51 #define     MULTIPLANE_READ_ENABLE__FLAG                BIT(0)
  52
  53 #define COPYBACK_DISABLE                        0x90
  54 #define     COPYBACK_DISABLE__FLAG                      BIT(0)
  55
  56 #define CACHE_WRITE_ENABLE                      0xa0
  57 #define     CACHE_WRITE_ENABLE__FLAG                    BIT(0)
  58
  59 #define CACHE_READ_ENABLE                       0xb0
  60 #define     CACHE_READ_ENABLE__FLAG                     BIT(0)
  61
  62 #define PREFETCH_MODE                           0xc0
  63 #define     PREFETCH_MODE__PREFETCH_EN                  BIT(0)
  64 #define     PREFETCH_MODE__PREFETCH_BURST_LENGTH        GENMASK(15, 4)
  65
  66 #define CHIP_ENABLE_DONT_CARE                   0xd0
  67 #define     CHIP_EN_DONT_CARE__FLAG                     BIT(0)
  68
  69 #define ECC_ENABLE                              0xe0
  70 #define     ECC_ENABLE__FLAG                            BIT(0)
  71
  72 #define GLOBAL_INT_ENABLE                       0xf0
  73 #define     GLOBAL_INT_EN_FLAG                          BIT(0)
  74
  75 #define WE_2_RE                                 0x100
  76 #define     WE_2_RE__VALUE                              GENMASK(5, 0)
  77
  78 #define ADDR_2_DATA                             0x110
  79 #define     ADDR_2_DATA__VALUE                          GENMASK(5, 0)
  80
  81 #define RE_2_WE                                 0x120
  82 #define     RE_2_WE__VALUE                              GENMASK(5, 0)
  83
  84 #define ACC_CLKS                                0x130
  85 #define     ACC_CLKS__VALUE                             GENMASK(3, 0)
  86
  87 #define NUMBER_OF_PLANES                        0x140
  88 #define     NUMBER_OF_PLANES__VALUE                     GENMASK(2, 0)
  89
  90 #define PAGES_PER_BLOCK                         0x150
  91 #define     PAGES_PER_BLOCK__VALUE                      GENMASK(15, 0)
  92
  93 #define DEVICE_WIDTH                            0x160
  94 #define     DEVICE_WIDTH__VALUE                         GENMASK(1, 0)
  95
  96 #define DEVICE_MAIN_AREA_SIZE                   0x170
  97 #define     DEVICE_MAIN_AREA_SIZE__VALUE                GENMASK(15, 0)
  98
  99 #define DEVICE_SPARE_AREA_SIZE                  0x180
 100 #define     DEVICE_SPARE_AREA_SIZE__VALUE               GENMASK(15, 0)
 101
 102 #define TWO_ROW_ADDR_CYCLES                     0x190
 103 #define     TWO_ROW_ADDR_CYCLES__FLAG                   BIT(0)
 104
 105 #define MULTIPLANE_ADDR_RESTRICT                0x1a0
 106 #define     MULTIPLANE_ADDR_RESTRICT__FLAG              BIT(0)
 107
 108 #define ECC_CORRECTION                          0x1b0
 109 #define     ECC_CORRECTION__VALUE                       GENMASK(4, 0)
 110
 111 #define READ_MODE                               0x1c0
 112 #define     READ_MODE__VALUE                            GENMASK(3, 0)
 113
 114 #define WRITE_MODE                              0x1d0
 115 #define     WRITE_MODE__VALUE                           GENMASK(3, 0)
 116
 117 #define COPYBACK_MODE                           0x1e0
 118 #define     COPYBACK_MODE__VALUE                        GENMASK(3, 0)
 119
 120 #define RDWR_EN_LO_CNT                          0x1f0
 121 #define     RDWR_EN_LO_CNT__VALUE                       GENMASK(4, 0)
 122
 123 #define RDWR_EN_HI_CNT                          0x200
 124 #define     RDWR_EN_HI_CNT__VALUE                       GENMASK(4, 0)
 125
 126 #define MAX_RD_DELAY                            0x210
 127 #define     MAX_RD_DELAY__VALUE                         GENMASK(3, 0)
 128
 129 #define CS_SETUP_CNT                            0x220
 130 #define     CS_SETUP_CNT__VALUE                         GENMASK(4, 0)
 131
 132 #define SPARE_AREA_SKIP_BYTES                   0x230
 133 #define     SPARE_AREA_SKIP_BYTES__VALUE                GENMASK(5, 0)
 134
 135 #define SPARE_AREA_MARKER                       0x240
 136 #define     SPARE_AREA_MARKER__VALUE                    GENMASK(15, 0)
 137
 138 #define DEVICES_CONNECTED                       0x250
 139 #define     DEVICES_CONNECTED__VALUE                    GENMASK(2, 0)
 140
 141 #define DIE_MASK                                0x260
 142 #define     DIE_MASK__VALUE                             GENMASK(7, 0)
 143
 144 #define FIRST_BLOCK_OF_NEXT_PLANE               0x270
 145 #define     FIRST_BLOCK_OF_NEXT_PLANE__VALUE            GENMASK(15, 0)
 146
 147 #define WRITE_PROTECT                           0x280
 148 #define     WRITE_PROTECT__FLAG                         BIT(0)
 149
 150 #define RE_2_RE                                 0x290
 151 #define     RE_2_RE__VALUE                              GENMASK(5, 0)
 152
 153 #define MANUFACTURER_ID                         0x300
 154 #define     MANUFACTURER_ID__VALUE                      GENMASK(7, 0)
 155
 156 #define DEVICE_ID                               0x310
 157 #define     DEVICE_ID__VALUE                            GENMASK(7, 0)
 158
 159 #define DEVICE_PARAM_0                          0x320
 160 #define     DEVICE_PARAM_0__VALUE                       GENMASK(7, 0)
 161
 162 #define DEVICE_PARAM_1                          0x330
 163 #define     DEVICE_PARAM_1__VALUE                       GENMASK(7, 0)
 164
 165 #define DEVICE_PARAM_2                          0x340
 166 #define     DEVICE_PARAM_2__VALUE                       GENMASK(7, 0)
 167
 168 #define LOGICAL_PAGE_DATA_SIZE                  0x350
 169 #define     LOGICAL_PAGE_DATA_SIZE__VALUE               GENMASK(15, 0)
 170
 171 #define LOGICAL_PAGE_SPARE_SIZE                 0x360
 172 #define     LOGICAL_PAGE_SPARE_SIZE__VALUE              GENMASK(15, 0)
 173
 174 #define REVISION                                0x370
 175 #define     REVISION__VALUE                             GENMASK(15, 0)
 176
 177 #define ONFI_DEVICE_FEATURES                    0x380
 178 #define     ONFI_DEVICE_FEATURES__VALUE                 GENMASK(5, 0)
 179
 180 #define ONFI_OPTIONAL_COMMANDS                  0x390
 181 #define     ONFI_OPTIONAL_COMMANDS__VALUE               GENMASK(5, 0)
 182
 183 #define ONFI_TIMING_MODE                        0x3a0
 184 #define     ONFI_TIMING_MODE__VALUE                     GENMASK(5, 0)
 185
 186 #define ONFI_PGM_CACHE_TIMING_MODE              0x3b0
 187 #define     ONFI_PGM_CACHE_TIMING_MODE__VALUE           GENMASK(5, 0)
 188
 189 #define ONFI_DEVICE_NO_OF_LUNS                  0x3c0
 190 #define     ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS          GENMASK(7, 0)
 191 #define     ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE         BIT(8)
 192
 193 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L      0x3d0
 194 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE   GENMASK(15, 0)
 195
 196 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U      0x3e0
 197 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE   GENMASK(15, 0)
 198
 199 #define FEATURES                                0x3f0
 200 #define     FEATURES__N_BANKS                           GENMASK(1, 0)
 201 #define     FEATURES__ECC_MAX_ERR                       GENMASK(5, 2)
 202 #define     FEATURES__DMA                               BIT(6)
 203 #define     FEATURES__CMD_DMA                           BIT(7)
 204 #define     FEATURES__PARTITION                         BIT(8)
 205 #define     FEATURES__XDMA_SIDEBAND                     BIT(9)
 206 #define     FEATURES__GPREG                             BIT(10)
 207 #define     FEATURES__INDEX_ADDR                        BIT(11)
 208
 209 #define TRANSFER_MODE                           0x400
 210 #define     TRANSFER_MODE__VALUE                        GENMASK(1, 0)
 211
 212 #define INTR_STATUS(bank)                       (0x410 + (bank) * 0x50)
 213 #define INTR_EN(bank)                           (0x420 + (bank) * 0x50)
 214 /* bit[1:0] is used differently depending on IP version */
 215 #define     INTR__ECC_UNCOR_ERR                         BIT(0)  /* new IP */
 216 #define     INTR__ECC_TRANSACTION_DONE                  BIT(0)  /* old IP */
 217 #define     INTR__ECC_ERR                               BIT(1)  /* old IP */
 218 #define     INTR__DMA_CMD_COMP                          BIT(2)
 219 #define     INTR__TIME_OUT                              BIT(3)
 220 #define     INTR__PROGRAM_FAIL                          BIT(4)
 221 #define     INTR__ERASE_FAIL                            BIT(5)
 222 #define     INTR__LOAD_COMP                             BIT(6)
 223 #define     INTR__PROGRAM_COMP                          BIT(7)
 224 #define     INTR__ERASE_COMP                            BIT(8)
 225 #define     INTR__PIPE_CPYBCK_CMD_COMP                  BIT(9)
 226 #define     INTR__LOCKED_BLK                            BIT(10)
 227 #define     INTR__UNSUP_CMD                             BIT(11)
 228 #define     INTR__INT_ACT                               BIT(12)
 229 #define     INTR__RST_COMP                              BIT(13)
 230 #define     INTR__PIPE_CMD_ERR                          BIT(14)
 231 #define     INTR__PAGE_XFER_INC                         BIT(15)
 232
 233 #define PAGE_CNT(bank)                          (0x430 + (bank) * 0x50)
 234 #define ERR_PAGE_ADDR(bank)                     (0x440 + (bank) * 0x50)
 235 #define ERR_BLOCK_ADDR(bank)                    (0x450 + (bank) * 0x50)
 236
 237 #define ECC_THRESHOLD                           0x600
 238 #define     ECC_THRESHOLD__VALUE                        GENMASK(9, 0)
 239
 240 #define ECC_ERROR_BLOCK_ADDRESS                 0x610
 241 #define     ECC_ERROR_BLOCK_ADDRESS__VALUE              GENMASK(15, 0)
 242
 243 #define ECC_ERROR_PAGE_ADDRESS                  0x620
 244 #define     ECC_ERROR_PAGE_ADDRESS__VALUE               GENMASK(11, 0)
 245 #define     ECC_ERROR_PAGE_ADDRESS__BANK                GENMASK(15, 12)
 246
 247 #define ECC_ERROR_ADDRESS                       0x630
 248 #define     ECC_ERROR_ADDRESS__OFFSET                   GENMASK(11, 0)
 249 #define     ECC_ERROR_ADDRESS__SECTOR_NR                GENMASK(15, 12)
 250
 251 #define ERR_CORRECTION_INFO                     0x640
 252 #define     ERR_CORRECTION_INFO__BYTEMASK               GENMASK(7, 0)
 253 #define     ERR_CORRECTION_INFO__DEVICE_NR              GENMASK(11, 8)
 254 #define     ERR_CORRECTION_INFO__ERROR_TYPE             BIT(14)
 255 #define     ERR_CORRECTION_INFO__LAST_ERR_INFO          BIT(15)
 256
 257 #define ECC_COR_INFO(bank)                      (0x650 + (bank) / 2 * 0x10)
 258 #define     ECC_COR_INFO__SHIFT(bank)                   ((bank) % 2 * 8)
 259 #define     ECC_COR_INFO__MAX_ERRORS                    GENMASK(6, 0)
 260 #define     ECC_COR_INFO__UNCOR_ERR                     BIT(7)
 261
 262 #define CFG_DATA_BLOCK_SIZE                     0x6b0
 263
 264 #define CFG_LAST_DATA_BLOCK_SIZE                0x6c0
 265
 266 #define CFG_NUM_DATA_BLOCKS                     0x6d0
 267
 268 #define CFG_META_DATA_SIZE                      0x6e0
 269
 270 #define DMA_ENABLE                              0x700
 271 #define     DMA_ENABLE__FLAG                            BIT(0)
 272
 273 #define IGNORE_ECC_DONE                         0x710
 274 #define     IGNORE_ECC_DONE__FLAG                       BIT(0)
 275
 276 #define DMA_INTR                                0x720
 277 #define DMA_INTR_EN                             0x730
 278 #define     DMA_INTR__TARGET_ERROR                      BIT(0)
 279 #define     DMA_INTR__DESC_COMP_CHANNEL0                BIT(1)
 280 #define     DMA_INTR__DESC_COMP_CHANNEL1                BIT(2)
 281 #define     DMA_INTR__DESC_COMP_CHANNEL2                BIT(3)
 282 #define     DMA_INTR__DESC_COMP_CHANNEL3                BIT(4)
 283 #define     DMA_INTR__MEMCOPY_DESC_COMP                 BIT(5)
 284
 285 #define TARGET_ERR_ADDR_LO                      0x740
 286 #define     TARGET_ERR_ADDR_LO__VALUE                   GENMASK(15, 0)
 287
 288 #define TARGET_ERR_ADDR_HI                      0x750
 289 #define     TARGET_ERR_ADDR_HI__VALUE                   GENMASK(15, 0)
 290
 291 #define CHNL_ACTIVE                             0x760
 292 #define     CHNL_ACTIVE__CHANNEL0                       BIT(0)
 293 #define     CHNL_ACTIVE__CHANNEL1                       BIT(1)
 294 #define     CHNL_ACTIVE__CHANNEL2                       BIT(2)
 295 #define     CHNL_ACTIVE__CHANNEL3                       BIT(3)
 296
 297 #define FAIL 1                  /*failed flag*/
 298 #define PASS 0                  /*success flag*/
 299
 300 #define CLK_X  5
 301 #define CLK_MULTI 4
 302
 303 #define ONFI_BLOOM_TIME         1
 304 #define MODE5_WORKAROUND        0
 305
 306
 307 #define MODE_00    0x00000000
 308 #define MODE_01    0x04000000
 309 #define MODE_10    0x08000000
 310 #define MODE_11    0x0C000000
 311
 312 struct nand_buf {
 313         int head;
 314         int tail;
 315         uint8_t *buf;
 316         dma_addr_t dma_buf;
 317 };
 318
 319 #define INTEL_CE4100    1
 320 #define INTEL_MRST      2
 321 #define DT              3
 322
 323 struct denali_nand_info {
 324         struct nand_chip nand;
 325         int flash_bank; /* currently selected chip */
 326         int status;
 327         int platform;
 328         struct nand_buf buf;
 329         struct device *dev;
 330         int total_used_banks;
 331         int page;
 332         void __iomem *flash_reg;        /* Register Interface */
 333         void __iomem *flash_mem;        /* Host Data/Command Interface */
 334
 335         /* elements used by ISR */
 336         struct completion complete;
 337         spinlock_t irq_lock;
 338         uint32_t irq_status;
 339         int irq;
 340
 341         int devnum;     /* represent how many nands connected */
 342         int bbtskipbytes;
 343         int max_banks;
 344         unsigned int revision;
 345         unsigned int caps;
 346         const struct nand_ecc_caps *ecc_caps;
 347 };
 348
 349 #define DENALI_CAP_HW_ECC_FIXUP                 BIT(0)
 350 #define DENALI_CAP_DMA_64BIT                    BIT(1)
 351
 352 int denali_calc_ecc_bytes(int step_size, int strength);
 353 extern int denali_init(struct denali_nand_info *denali);
 354 extern void denali_remove(struct denali_nand_info *denali);
 355
 356 #endif /* __DENALI_H__ */