drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ECC support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct mtd_info *mtd, int new_state);
  97
  98 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  99                              struct mtd_oob_ops *ops);
 100
 101 /*
 102  * For devices which display every fart in the system on a separate LED. Is
 103  * compiled away when LED support is disabled.
 104  */
 105 DEFINE_LED_TRIGGER(nand_led_trigger);
 106
 107 static int check_offs_len(struct mtd_info *mtd,
 108                                         loff_t ofs, uint64_t len)
 109 {
 110         struct nand_chip *chip = mtd->priv;
 111         int ret = 0;
 112
 113         /* Start address must align on block boundary */
 114         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 115                 pr_debug("%s: unaligned address\n", __func__);
 116                 ret = -EINVAL;
 117         }
 118
 119         /* Length must align on block boundary */
 120         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 121                 pr_debug("%s: length not block aligned\n", __func__);
 122                 ret = -EINVAL;
 123         }
 124
 125         return ret;
 126 }
 127
 128 /**
 129  * nand_release_device - [GENERIC] release chip
 130  * @mtd: MTD device structure
 131  *
 132  * Release chip lock and wake up anyone waiting on the device.
 133  */
 134 static void nand_release_device(struct mtd_info *mtd)
 135 {
 136         struct nand_chip *chip = mtd->priv;
 137
 138         /* Release the controller and the chip */
 139         spin_lock(&chip->controller->lock);
 140         chip->controller->active = NULL;
 141         chip->state = FL_READY;
 142         wake_up(&chip->controller->wq);
 143         spin_unlock(&chip->controller->lock);
 144 }
 145
 146 /**
 147  * nand_read_byte - [DEFAULT] read one byte from the chip
 148  * @mtd: MTD device structure
 149  *
 150  * Default read function for 8bit buswidth
 151  */
 152 static uint8_t nand_read_byte(struct mtd_info *mtd)
 153 {
 154         struct nand_chip *chip = mtd->priv;
 155         return readb(chip->IO_ADDR_R);
 156 }
 157
 158 /**
 159  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 160  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 161  * @mtd: MTD device structure
 162  *
 163  * Default read function for 16bit buswidth with endianness conversion.
 164  *
 165  */
 166 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 167 {
 168         struct nand_chip *chip = mtd->priv;
 169         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 170 }
 171
 172 /**
 173  * nand_read_word - [DEFAULT] read one word from the chip
 174  * @mtd: MTD device structure
 175  *
 176  * Default read function for 16bit buswidth without endianness conversion.
 177  */
 178 static u16 nand_read_word(struct mtd_info *mtd)
 179 {
 180         struct nand_chip *chip = mtd->priv;
 181         return readw(chip->IO_ADDR_R);
 182 }
 183
 184 /**
 185  * nand_select_chip - [DEFAULT] control CE line
 186  * @mtd: MTD device structure
 187  * @chipnr: chipnumber to select, -1 for deselect
 188  *
 189  * Default select function for 1 chip devices.
 190  */
 191 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 192 {
 193         struct nand_chip *chip = mtd->priv;
 194
 195         switch (chipnr) {
 196         case -1:
 197                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 198                 break;
 199         case 0:
 200                 break;
 201
 202         default:
 203                 BUG();
 204         }
 205 }
 206
 207 /**
 208  * nand_write_buf - [DEFAULT] write buffer to chip
 209  * @mtd: MTD device structure
 210  * @buf: data buffer
 211  * @len: number of bytes to write
 212  *
 213  * Default write function for 8bit buswidth.
 214  */
 215 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 216 {
 217         int i;
 218         struct nand_chip *chip = mtd->priv;
 219
 220         for (i = 0; i < len; i++)
 221                 writeb(buf[i], chip->IO_ADDR_W);
 222 }
 223
 224 /**
 225  * nand_read_buf - [DEFAULT] read chip data into buffer
 226  * @mtd: MTD device structure
 227  * @buf: buffer to store date
 228  * @len: number of bytes to read
 229  *
 230  * Default read function for 8bit buswidth.
 231  */
 232 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 233 {
 234         int i;
 235         struct nand_chip *chip = mtd->priv;
 236
 237         for (i = 0; i < len; i++)
 238                 buf[i] = readb(chip->IO_ADDR_R);
 239 }
 240
 241 /**
 242  * nand_write_buf16 - [DEFAULT] write buffer to chip
 243  * @mtd: MTD device structure
 244  * @buf: data buffer
 245  * @len: number of bytes to write
 246  *
 247  * Default write function for 16bit buswidth.
 248  */
 249 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 250 {
 251         int i;
 252         struct nand_chip *chip = mtd->priv;
 253         u16 *p = (u16 *) buf;
 254         len >>= 1;
 255
 256         for (i = 0; i < len; i++)
 257                 writew(p[i], chip->IO_ADDR_W);
 258
 259 }
 260
 261 /**
 262  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 263  * @mtd: MTD device structure
 264  * @buf: buffer to store date
 265  * @len: number of bytes to read
 266  *
 267  * Default read function for 16bit buswidth.
 268  */
 269 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 270 {
 271         int i;
 272         struct nand_chip *chip = mtd->priv;
 273         u16 *p = (u16 *) buf;
 274         len >>= 1;
 275
 276         for (i = 0; i < len; i++)
 277                 p[i] = readw(chip->IO_ADDR_R);
 278 }
 279
 280 /**
 281  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 282  * @mtd: MTD device structure
 283  * @ofs: offset from device start
 284  * @getchip: 0, if the chip is already selected
 285  *
 286  * Check, if the block is bad.
 287  */
 288 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 289 {
 290         int page, chipnr, res = 0, i = 0;
 291         struct nand_chip *chip = mtd->priv;
 292         u16 bad;
 293
 294         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 295                 ofs += mtd->erasesize - mtd->writesize;
 296
 297         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 298
 299         if (getchip) {
 300                 chipnr = (int)(ofs >> chip->chip_shift);
 301
 302                 nand_get_device(mtd, FL_READING);
 303
 304                 /* Select the NAND device */
 305                 chip->select_chip(mtd, chipnr);
 306         }
 307
 308         do {
 309                 if (chip->options & NAND_BUSWIDTH_16) {
 310                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 311                                         chip->badblockpos & 0xFE, page);
 312                         bad = cpu_to_le16(chip->read_word(mtd));
 313                         if (chip->badblockpos & 0x1)
 314                                 bad >>= 8;
 315                         else
 316                                 bad &= 0xFF;
 317                 } else {
 318                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 319                                         page);
 320                         bad = chip->read_byte(mtd);
 321                 }
 322
 323                 if (likely(chip->badblockbits == 8))
 324                         res = bad != 0xFF;
 325                 else
 326                         res = hweight8(bad) < chip->badblockbits;
 327                 ofs += mtd->writesize;
 328                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 329                 i++;
 330         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 331
 332         if (getchip) {
 333                 chip->select_chip(mtd, -1);
 334                 nand_release_device(mtd);
 335         }
 336
 337         return res;
 338 }
 339
 340 /**
 341  * nand_default_block_markbad - [DEFAULT] mark a block bad
 342  * @mtd: MTD device structure
 343  * @ofs: offset from device start
 344  *
 345  * This is the default implementation, which can be overridden by a hardware
 346  * specific driver. We try operations in the following order, according to our
 347  * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
 348  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 349  *  (2) update in-memory BBT
 350  *  (3) write bad block marker to OOB area of affected block
 351  *  (4) update flash-based BBT
 352  * Note that we retain the first error encountered in (3) or (4), finish the
 353  * procedures, and dump the error in the end.
 354 */
 355 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 356 {
 357         struct nand_chip *chip = mtd->priv;
 358         uint8_t buf[2] = { 0, 0 };
 359         int block, res, ret = 0, i = 0;
 360         int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
 361
 362         if (write_oob) {
 363                 struct erase_info einfo;
 364
 365                 /* Attempt erase before marking OOB */
 366                 memset(&einfo, 0, sizeof(einfo));
 367                 einfo.mtd = mtd;
 368                 einfo.addr = ofs;
 369                 einfo.len = 1 << chip->phys_erase_shift;
 370                 nand_erase_nand(mtd, &einfo, 0);
 371         }
 372
 373         /* Get block number */
 374         block = (int)(ofs >> chip->bbt_erase_shift);
 375         /* Mark block bad in memory-based BBT */
 376         if (chip->bbt)
 377                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 378
 379         /* Write bad block marker to OOB */
 380         if (write_oob) {
 381                 struct mtd_oob_ops ops;
 382                 loff_t wr_ofs = ofs;
 383
 384                 nand_get_device(mtd, FL_WRITING);
 385
 386                 ops.datbuf = NULL;
 387                 ops.oobbuf = buf;
 388                 ops.ooboffs = chip->badblockpos;
 389                 if (chip->options & NAND_BUSWIDTH_16) {
 390                         ops.ooboffs &= ~0x01;
 391                         ops.len = ops.ooblen = 2;
 392                 } else {
 393                         ops.len = ops.ooblen = 1;
 394                 }
 395                 ops.mode = MTD_OPS_PLACE_OOB;
 396
 397                 /* Write to first/last page(s) if necessary */
 398                 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 399                         wr_ofs += mtd->erasesize - mtd->writesize;
 400                 do {
 401                         res = nand_do_write_oob(mtd, wr_ofs, &ops);
 402                         if (!ret)
 403                                 ret = res;
 404
 405                         i++;
 406                         wr_ofs += mtd->writesize;
 407                 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 408
 409                 nand_release_device(mtd);
 410         }
 411
 412         /* Update flash-based bad block table */
 413         if (chip->bbt_options & NAND_BBT_USE_FLASH) {
 414                 res = nand_update_bbt(mtd, ofs);
 415                 if (!ret)
 416                         ret = res;
 417         }
 418
 419         if (!ret)
 420                 mtd->ecc_stats.badblocks++;
 421
 422         return ret;
 423 }
 424
 425 /**
 426  * nand_check_wp - [GENERIC] check if the chip is write protected
 427  * @mtd: MTD device structure
 428  *
 429  * Check, if the device is write protected. The function expects, that the
 430  * device is already selected.
 431  */
 432 static int nand_check_wp(struct mtd_info *mtd)
 433 {
 434         struct nand_chip *chip = mtd->priv;
 435
 436         /* Broken xD cards report WP despite being writable */
 437         if (chip->options & NAND_BROKEN_XD)
 438                 return 0;
 439
 440         /* Check the WP bit */
 441         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 442         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 443 }
 444
 445 /**
 446  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 447  * @mtd: MTD device structure
 448  * @ofs: offset from device start
 449  * @getchip: 0, if the chip is already selected
 450  * @allowbbt: 1, if its allowed to access the bbt area
 451  *
 452  * Check, if the block is bad. Either by reading the bad block table or
 453  * calling of the scan function.
 454  */
 455 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 456                                int allowbbt)
 457 {
 458         struct nand_chip *chip = mtd->priv;
 459
 460         if (!chip->bbt)
 461                 return chip->block_bad(mtd, ofs, getchip);
 462
 463         /* Return info from the table */
 464         return nand_isbad_bbt(mtd, ofs, allowbbt);
 465 }
 466
 467 /**
 468  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 469  * @mtd: MTD device structure
 470  * @timeo: Timeout
 471  *
 472  * Helper function for nand_wait_ready used when needing to wait in interrupt
 473  * context.
 474  */
 475 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 476 {
 477         struct nand_chip *chip = mtd->priv;
 478         int i;
 479
 480         /* Wait for the device to get ready */
 481         for (i = 0; i < timeo; i++) {
 482                 if (chip->dev_ready(mtd))
 483                         break;
 484                 touch_softlockup_watchdog();
 485                 mdelay(1);
 486         }
 487 }
 488
 489 /* Wait for the ready pin, after a command. The timeout is caught later. */
 490 void nand_wait_ready(struct mtd_info *mtd)
 491 {
 492         struct nand_chip *chip = mtd->priv;
 493         unsigned long timeo = jiffies + msecs_to_jiffies(20);
 494
 495         /* 400ms timeout */
 496         if (in_interrupt() || oops_in_progress)
 497                 return panic_nand_wait_ready(mtd, 400);
 498
 499         led_trigger_event(nand_led_trigger, LED_FULL);
 500         /* Wait until command is processed or timeout occurs */
 501         do {
 502                 if (chip->dev_ready(mtd))
 503                         break;
 504                 touch_softlockup_watchdog();
 505         } while (time_before(jiffies, timeo));
 506         led_trigger_event(nand_led_trigger, LED_OFF);
 507 }
 508 EXPORT_SYMBOL_GPL(nand_wait_ready);
 509
 510 /**
 511  * nand_command - [DEFAULT] Send command to NAND device
 512  * @mtd: MTD device structure
 513  * @command: the command to be sent
 514  * @column: the column address for this command, -1 if none
 515  * @page_addr: the page address for this command, -1 if none
 516  *
 517  * Send command to NAND device. This function is used for small page devices
 518  * (256/512 Bytes per page).
 519  */
 520 static void nand_command(struct mtd_info *mtd, unsigned int command,
 521                          int column, int page_addr)
 522 {
 523         register struct nand_chip *chip = mtd->priv;
 524         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 525
 526         /* Write out the command to the device */
 527         if (command == NAND_CMD_SEQIN) {
 528                 int readcmd;
 529
 530                 if (column >= mtd->writesize) {
 531                         /* OOB area */
 532                         column -= mtd->writesize;
 533                         readcmd = NAND_CMD_READOOB;
 534                 } else if (column < 256) {
 535                         /* First 256 bytes --> READ0 */
 536                         readcmd = NAND_CMD_READ0;
 537                 } else {
 538                         column -= 256;
 539                         readcmd = NAND_CMD_READ1;
 540                 }
 541                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 542                 ctrl &= ~NAND_CTRL_CHANGE;
 543         }
 544         chip->cmd_ctrl(mtd, command, ctrl);
 545
 546         /* Address cycle, when necessary */
 547         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 548         /* Serially input address */
 549         if (column != -1) {
 550                 /* Adjust columns for 16 bit buswidth */
 551                 if (chip->options & NAND_BUSWIDTH_16)
 552                         column >>= 1;
 553                 chip->cmd_ctrl(mtd, column, ctrl);
 554                 ctrl &= ~NAND_CTRL_CHANGE;
 555         }
 556         if (page_addr != -1) {
 557                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 560                 /* One more address cycle for devices > 32MiB */
 561                 if (chip->chipsize > (32 << 20))
 562                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 563         }
 564         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 565
 566         /*
 567          * Program and erase have their own busy handlers status and sequential
 568          * in needs no delay
 569          */
 570         switch (command) {
 571
 572         case NAND_CMD_PAGEPROG:
 573         case NAND_CMD_ERASE1:
 574         case NAND_CMD_ERASE2:
 575         case NAND_CMD_SEQIN:
 576         case NAND_CMD_STATUS:
 577                 return;
 578
 579         case NAND_CMD_RESET:
 580                 if (chip->dev_ready)
 581                         break;
 582                 udelay(chip->chip_delay);
 583                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 584                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 585                 chip->cmd_ctrl(mtd,
 586                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 588                                 ;
 589                 return;
 590
 591                 /* This applies to read commands */
 592         default:
 593                 /*
 594                  * If we don't have access to the busy pin, we apply the given
 595                  * command delay
 596                  */
 597                 if (!chip->dev_ready) {
 598                         udelay(chip->chip_delay);
 599                         return;
 600                 }
 601         }
 602         /*
 603          * Apply this short delay always to ensure that we do wait tWB in
 604          * any case on any machine.
 605          */
 606         ndelay(100);
 607
 608         nand_wait_ready(mtd);
 609 }
 610
 611 /**
 612  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 613  * @mtd: MTD device structure
 614  * @command: the command to be sent
 615  * @column: the column address for this command, -1 if none
 616  * @page_addr: the page address for this command, -1 if none
 617  *
 618  * Send command to NAND device. This is the version for the new large page
 619  * devices. We don't have the separate regions as we have in the small page
 620  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 621  */
 622 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 623                             int column, int page_addr)
 624 {
 625         register struct nand_chip *chip = mtd->priv;
 626
 627         /* Emulate NAND_CMD_READOOB */
 628         if (command == NAND_CMD_READOOB) {
 629                 column += mtd->writesize;
 630                 command = NAND_CMD_READ0;
 631         }
 632
 633         /* Command latch cycle */
 634         chip->cmd_ctrl(mtd, command & 0xff,
 635                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 636
 637         if (column != -1 || page_addr != -1) {
 638                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 639
 640                 /* Serially input address */
 641                 if (column != -1) {
 642                         /* Adjust columns for 16 bit buswidth */
 643                         if (chip->options & NAND_BUSWIDTH_16)
 644                                 column >>= 1;
 645                         chip->cmd_ctrl(mtd, column, ctrl);
 646                         ctrl &= ~NAND_CTRL_CHANGE;
 647                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 648                 }
 649                 if (page_addr != -1) {
 650                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 651                         chip->cmd_ctrl(mtd, page_addr >> 8,
 652                                        NAND_NCE | NAND_ALE);
 653                         /* One more address cycle for devices > 128MiB */
 654                         if (chip->chipsize > (128 << 20))
 655                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 656                                                NAND_NCE | NAND_ALE);
 657                 }
 658         }
 659         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 660
 661         /*
 662          * Program and erase have their own busy handlers status, sequential
 663          * in, and deplete1 need no delay.
 664          */
 665         switch (command) {
 666
 667         case NAND_CMD_CACHEDPROG:
 668         case NAND_CMD_PAGEPROG:
 669         case NAND_CMD_ERASE1:
 670         case NAND_CMD_ERASE2:
 671         case NAND_CMD_SEQIN:
 672         case NAND_CMD_RNDIN:
 673         case NAND_CMD_STATUS:
 674         case NAND_CMD_DEPLETE1:
 675                 return;
 676
 677         case NAND_CMD_STATUS_ERROR:
 678         case NAND_CMD_STATUS_ERROR0:
 679         case NAND_CMD_STATUS_ERROR1:
 680         case NAND_CMD_STATUS_ERROR2:
 681         case NAND_CMD_STATUS_ERROR3:
 682                 /* Read error status commands require only a short delay */
 683                 udelay(chip->chip_delay);
 684                 return;
 685
 686         case NAND_CMD_RESET:
 687                 if (chip->dev_ready)
 688                         break;
 689                 udelay(chip->chip_delay);
 690                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 691                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 692                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 693                                NAND_NCE | NAND_CTRL_CHANGE);
 694                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 695                                 ;
 696                 return;
 697
 698         case NAND_CMD_RNDOUT:
 699                 /* No ready / busy check necessary */
 700                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 701                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 702                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 703                                NAND_NCE | NAND_CTRL_CHANGE);
 704                 return;
 705
 706         case NAND_CMD_READ0:
 707                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 708                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 709                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 710                                NAND_NCE | NAND_CTRL_CHANGE);
 711
 712                 /* This applies to read commands */
 713         default:
 714                 /*
 715                  * If we don't have access to the busy pin, we apply the given
 716                  * command delay.
 717                  */
 718                 if (!chip->dev_ready) {
 719                         udelay(chip->chip_delay);
 720                         return;
 721                 }
 722         }
 723
 724         /*
 725          * Apply this short delay always to ensure that we do wait tWB in
 726          * any case on any machine.
 727          */
 728         ndelay(100);
 729
 730         nand_wait_ready(mtd);
 731 }
 732
 733 /**
 734  * panic_nand_get_device - [GENERIC] Get chip for selected access
 735  * @chip: the nand chip descriptor
 736  * @mtd: MTD device structure
 737  * @new_state: the state which is requested
 738  *
 739  * Used when in panic, no locks are taken.
 740  */
 741 static void panic_nand_get_device(struct nand_chip *chip,
 742                       struct mtd_info *mtd, int new_state)
 743 {
 744         /* Hardware controller shared among independent devices */
 745         chip->controller->active = chip;
 746         chip->state = new_state;
 747 }
 748
 749 /**
 750  * nand_get_device - [GENERIC] Get chip for selected access
 751  * @mtd: MTD device structure
 752  * @new_state: the state which is requested
 753  *
 754  * Get the device and lock it for exclusive access
 755  */
 756 static int
 757 nand_get_device(struct mtd_info *mtd, int new_state)
 758 {
 759         struct nand_chip *chip = mtd->priv;
 760         spinlock_t *lock = &chip->controller->lock;
 761         wait_queue_head_t *wq = &chip->controller->wq;
 762         DECLARE_WAITQUEUE(wait, current);
 763 retry:
 764         spin_lock(lock);
 765
 766         /* Hardware controller shared among independent devices */
 767         if (!chip->controller->active)
 768                 chip->controller->active = chip;
 769
 770         if (chip->controller->active == chip && chip->state == FL_READY) {
 771                 chip->state = new_state;
 772                 spin_unlock(lock);
 773                 return 0;
 774         }
 775         if (new_state == FL_PM_SUSPENDED) {
 776                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 777                         chip->state = FL_PM_SUSPENDED;
 778                         spin_unlock(lock);
 779                         return 0;
 780                 }
 781         }
 782         set_current_state(TASK_UNINTERRUPTIBLE);
 783         add_wait_queue(wq, &wait);
 784         spin_unlock(lock);
 785         schedule();
 786         remove_wait_queue(wq, &wait);
 787         goto retry;
 788 }
 789
 790 /**
 791  * panic_nand_wait - [GENERIC] wait until the command is done
 792  * @mtd: MTD device structure
 793  * @chip: NAND chip structure
 794  * @timeo: timeout
 795  *
 796  * Wait for command done. This is a helper function for nand_wait used when
 797  * we are in interrupt context. May happen when in panic and trying to write
 798  * an oops through mtdoops.
 799  */
 800 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 801                             unsigned long timeo)
 802 {
 803         int i;
 804         for (i = 0; i < timeo; i++) {
 805                 if (chip->dev_ready) {
 806                         if (chip->dev_ready(mtd))
 807                                 break;
 808                 } else {
 809                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 810                                 break;
 811                 }
 812                 mdelay(1);
 813         }
 814 }
 815
 816 /**
 817  * nand_wait - [DEFAULT] wait until the command is done
 818  * @mtd: MTD device structure
 819  * @chip: NAND chip structure
 820  *
 821  * Wait for command done. This applies to erase and program only. Erase can
 822  * take up to 400ms and program up to 20ms according to general NAND and
 823  * SmartMedia specs.
 824  */
 825 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 826 {
 827
 828         unsigned long timeo = jiffies;
 829         int status, state = chip->state;
 830
 831         if (state == FL_ERASING)
 832                 timeo += (HZ * 400) / 1000;
 833         else
 834                 timeo += (HZ * 20) / 1000;
 835
 836         led_trigger_event(nand_led_trigger, LED_FULL);
 837
 838         /*
 839          * Apply this short delay always to ensure that we do wait tWB in any
 840          * case on any machine.
 841          */
 842         ndelay(100);
 843
 844         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 845                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 846         else
 847                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 848
 849         if (in_interrupt() || oops_in_progress)
 850                 panic_nand_wait(mtd, chip, timeo);
 851         else {
 852                 while (time_before(jiffies, timeo)) {
 853                         if (chip->dev_ready) {
 854                                 if (chip->dev_ready(mtd))
 855                                         break;
 856                         } else {
 857                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 858                                         break;
 859                         }
 860                         cond_resched();
 861                 }
 862         }
 863         led_trigger_event(nand_led_trigger, LED_OFF);
 864
 865         status = (int)chip->read_byte(mtd);
 866         /* This can happen if in case of timeout or buggy dev_ready */
 867         WARN_ON(!(status & NAND_STATUS_READY));
 868         return status;
 869 }
 870
 871 /**
 872  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 873  * @mtd: mtd info
 874  * @ofs: offset to start unlock from
 875  * @len: length to unlock
 876  * @invert: when = 0, unlock the range of blocks within the lower and
 877  *                    upper boundary address
 878  *          when = 1, unlock the range of blocks outside the boundaries
 879  *                    of the lower and upper boundary address
 880  *
 881  * Returs unlock status.
 882  */
 883 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 884                                         uint64_t len, int invert)
 885 {
 886         int ret = 0;
 887         int status, page;
 888         struct nand_chip *chip = mtd->priv;
 889
 890         /* Submit address of first page to unlock */
 891         page = ofs >> chip->page_shift;
 892         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 893
 894         /* Submit address of last page to unlock */
 895         page = (ofs + len) >> chip->page_shift;
 896         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 897                                 (page | invert) & chip->pagemask);
 898
 899         /* Call wait ready function */
 900         status = chip->waitfunc(mtd, chip);
 901         /* See if device thinks it succeeded */
 902         if (status & NAND_STATUS_FAIL) {
 903                 pr_debug("%s: error status = 0x%08x\n",
 904                                         __func__, status);
 905                 ret = -EIO;
 906         }
 907
 908         return ret;
 909 }
 910
 911 /**
 912  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 913  * @mtd: mtd info
 914  * @ofs: offset to start unlock from
 915  * @len: length to unlock
 916  *
 917  * Returns unlock status.
 918  */
 919 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 920 {
 921         int ret = 0;
 922         int chipnr;
 923         struct nand_chip *chip = mtd->priv;
 924
 925         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 926                         __func__, (unsigned long long)ofs, len);
 927
 928         if (check_offs_len(mtd, ofs, len))
 929                 ret = -EINVAL;
 930
 931         /* Align to last block address if size addresses end of the device */
 932         if (ofs + len == mtd->size)
 933                 len -= mtd->erasesize;
 934
 935         nand_get_device(mtd, FL_UNLOCKING);
 936
 937         /* Shift to get chip number */
 938         chipnr = ofs >> chip->chip_shift;
 939
 940         chip->select_chip(mtd, chipnr);
 941
 942         /* Check, if it is write protected */
 943         if (nand_check_wp(mtd)) {
 944                 pr_debug("%s: device is write protected!\n",
 945                                         __func__);
 946                 ret = -EIO;
 947                 goto out;
 948         }
 949
 950         ret = __nand_unlock(mtd, ofs, len, 0);
 951
 952 out:
 953         chip->select_chip(mtd, -1);
 954         nand_release_device(mtd);
 955
 956         return ret;
 957 }
 958 EXPORT_SYMBOL(nand_unlock);
 959
 960 /**
 961  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 962  * @mtd: mtd info
 963  * @ofs: offset to start unlock from
 964  * @len: length to unlock
 965  *
 966  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 967  * have this feature, but it allows only to lock all blocks, not for specified
 968  * range for block. Implementing 'lock' feature by making use of 'unlock', for
 969  * now.
 970  *
 971  * Returns lock status.
 972  */
 973 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 974 {
 975         int ret = 0;
 976         int chipnr, status, page;
 977         struct nand_chip *chip = mtd->priv;
 978
 979         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 980                         __func__, (unsigned long long)ofs, len);
 981
 982         if (check_offs_len(mtd, ofs, len))
 983                 ret = -EINVAL;
 984
 985         nand_get_device(mtd, FL_LOCKING);
 986
 987         /* Shift to get chip number */
 988         chipnr = ofs >> chip->chip_shift;
 989
 990         chip->select_chip(mtd, chipnr);
 991
 992         /* Check, if it is write protected */
 993         if (nand_check_wp(mtd)) {
 994                 pr_debug("%s: device is write protected!\n",
 995                                         __func__);
 996                 status = MTD_ERASE_FAILED;
 997                 ret = -EIO;
 998                 goto out;
 999         }
1000
1001         /* Submit address of first page to lock */
1002         page = ofs >> chip->page_shift;
1003         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1004
1005         /* Call wait ready function */
1006         status = chip->waitfunc(mtd, chip);
1007         /* See if device thinks it succeeded */
1008         if (status & NAND_STATUS_FAIL) {
1009                 pr_debug("%s: error status = 0x%08x\n",
1010                                         __func__, status);
1011                 ret = -EIO;
1012                 goto out;
1013         }
1014
1015         ret = __nand_unlock(mtd, ofs, len, 0x1);
1016
1017 out:
1018         chip->select_chip(mtd, -1);
1019         nand_release_device(mtd);
1020
1021         return ret;
1022 }
1023 EXPORT_SYMBOL(nand_lock);
1024
1025 /**
1026  * nand_read_page_raw - [INTERN] read raw page data without ecc
1027  * @mtd: mtd info structure
1028  * @chip: nand chip info structure
1029  * @buf: buffer to store read data
1030  * @oob_required: caller requires OOB data read to chip->oob_poi
1031  * @page: page number to read
1032  *
1033  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1034  */
1035 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1036                               uint8_t *buf, int oob_required, int page)
1037 {
1038         chip->read_buf(mtd, buf, mtd->writesize);
1039         if (oob_required)
1040                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1041         return 0;
1042 }
1043
1044 /**
1045  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1046  * @mtd: mtd info structure
1047  * @chip: nand chip info structure
1048  * @buf: buffer to store read data
1049  * @oob_required: caller requires OOB data read to chip->oob_poi
1050  * @page: page number to read
1051  *
1052  * We need a special oob layout and handling even when OOB isn't used.
1053  */
1054 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1055                                        struct nand_chip *chip, uint8_t *buf,
1056                                        int oob_required, int page)
1057 {
1058         int eccsize = chip->ecc.size;
1059         int eccbytes = chip->ecc.bytes;
1060         uint8_t *oob = chip->oob_poi;
1061         int steps, size;
1062
1063         for (steps = chip->ecc.steps; steps > 0; steps--) {
1064                 chip->read_buf(mtd, buf, eccsize);
1065                 buf += eccsize;
1066
1067                 if (chip->ecc.prepad) {
1068                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1069                         oob += chip->ecc.prepad;
1070                 }
1071
1072                 chip->read_buf(mtd, oob, eccbytes);
1073                 oob += eccbytes;
1074
1075                 if (chip->ecc.postpad) {
1076                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1077                         oob += chip->ecc.postpad;
1078                 }
1079         }
1080
1081         size = mtd->oobsize - (oob - chip->oob_poi);
1082         if (size)
1083                 chip->read_buf(mtd, oob, size);
1084
1085         return 0;
1086 }
1087
1088 /**
1089  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1090  * @mtd: mtd info structure
1091  * @chip: nand chip info structure
1092  * @buf: buffer to store read data
1093  * @oob_required: caller requires OOB data read to chip->oob_poi
1094  * @page: page number to read
1095  */
1096 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1097                                 uint8_t *buf, int oob_required, int page)
1098 {
1099         int i, eccsize = chip->ecc.size;
1100         int eccbytes = chip->ecc.bytes;
1101         int eccsteps = chip->ecc.steps;
1102         uint8_t *p = buf;
1103         uint8_t *ecc_calc = chip->buffers->ecccalc;
1104         uint8_t *ecc_code = chip->buffers->ecccode;
1105         uint32_t *eccpos = chip->ecc.layout->eccpos;
1106         unsigned int max_bitflips = 0;
1107
1108         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1109
1110         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1111                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1112
1113         for (i = 0; i < chip->ecc.total; i++)
1114                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1115
1116         eccsteps = chip->ecc.steps;
1117         p = buf;
1118
1119         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1120                 int stat;
1121
1122                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1123                 if (stat < 0) {
1124                         mtd->ecc_stats.failed++;
1125                 } else {
1126                         mtd->ecc_stats.corrected += stat;
1127                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1128                 }
1129         }
1130         return max_bitflips;
1131 }
1132
1133 /**
1134  * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1135  * @mtd: mtd info structure
1136  * @chip: nand chip info structure
1137  * @data_offs: offset of requested data within the page
1138  * @readlen: data length
1139  * @bufpoi: buffer to store read data
1140  */
1141 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1142                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1143 {
1144         int start_step, end_step, num_steps;
1145         uint32_t *eccpos = chip->ecc.layout->eccpos;
1146         uint8_t *p;
1147         int data_col_addr, i, gaps = 0;
1148         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1149         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1150         int index = 0;
1151         unsigned int max_bitflips = 0;
1152
1153         /* Column address within the page aligned to ECC size (256bytes) */
1154         start_step = data_offs / chip->ecc.size;
1155         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1156         num_steps = end_step - start_step + 1;
1157
1158         /* Data size aligned to ECC ecc.size */
1159         datafrag_len = num_steps * chip->ecc.size;
1160         eccfrag_len = num_steps * chip->ecc.bytes;
1161
1162         data_col_addr = start_step * chip->ecc.size;
1163         /* If we read not a page aligned data */
1164         if (data_col_addr != 0)
1165                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1166
1167         p = bufpoi + data_col_addr;
1168         chip->read_buf(mtd, p, datafrag_len);
1169
1170         /* Calculate ECC */
1171         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1172                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1173
1174         /*
1175          * The performance is faster if we position offsets according to
1176          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1177          */
1178         for (i = 0; i < eccfrag_len - 1; i++) {
1179                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1180                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1181                         gaps = 1;
1182                         break;
1183                 }
1184         }
1185         if (gaps) {
1186                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1187                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1188         } else {
1189                 /*
1190                  * Send the command to read the particular ECC bytes take care
1191                  * about buswidth alignment in read_buf.
1192                  */
1193                 index = start_step * chip->ecc.bytes;
1194
1195                 aligned_pos = eccpos[index] & ~(busw - 1);
1196                 aligned_len = eccfrag_len;
1197                 if (eccpos[index] & (busw - 1))
1198                         aligned_len++;
1199                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1200                         aligned_len++;
1201
1202                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1203                                         mtd->writesize + aligned_pos, -1);
1204                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1205         }
1206
1207         for (i = 0; i < eccfrag_len; i++)
1208                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1209
1210         p = bufpoi + data_col_addr;
1211         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1212                 int stat;
1213
1214                 stat = chip->ecc.correct(mtd, p,
1215                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1216                 if (stat < 0) {
1217                         mtd->ecc_stats.failed++;
1218                 } else {
1219                         mtd->ecc_stats.corrected += stat;
1220                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1221                 }
1222         }
1223         return max_bitflips;
1224 }
1225
1226 /**
1227  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1228  * @mtd: mtd info structure
1229  * @chip: nand chip info structure
1230  * @buf: buffer to store read data
1231  * @oob_required: caller requires OOB data read to chip->oob_poi
1232  * @page: page number to read
1233  *
1234  * Not for syndrome calculating ECC controllers which need a special oob layout.
1235  */
1236 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1237                                 uint8_t *buf, int oob_required, int page)
1238 {
1239         int i, eccsize = chip->ecc.size;
1240         int eccbytes = chip->ecc.bytes;
1241         int eccsteps = chip->ecc.steps;
1242         uint8_t *p = buf;
1243         uint8_t *ecc_calc = chip->buffers->ecccalc;
1244         uint8_t *ecc_code = chip->buffers->ecccode;
1245         uint32_t *eccpos = chip->ecc.layout->eccpos;
1246         unsigned int max_bitflips = 0;
1247
1248         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1249                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1250                 chip->read_buf(mtd, p, eccsize);
1251                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1252         }
1253         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1254
1255         for (i = 0; i < chip->ecc.total; i++)
1256                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1257
1258         eccsteps = chip->ecc.steps;
1259         p = buf;
1260
1261         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1262                 int stat;
1263
1264                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1265                 if (stat < 0) {
1266                         mtd->ecc_stats.failed++;
1267                 } else {
1268                         mtd->ecc_stats.corrected += stat;
1269                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1270                 }
1271         }
1272         return max_bitflips;
1273 }
1274
1275 /**
1276  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1277  * @mtd: mtd info structure
1278  * @chip: nand chip info structure
1279  * @buf: buffer to store read data
1280  * @oob_required: caller requires OOB data read to chip->oob_poi
1281  * @page: page number to read
1282  *
1283  * Hardware ECC for large page chips, require OOB to be read first. For this
1284  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1285  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1286  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1287  * the data area, by overwriting the NAND manufacturer bad block markings.
1288  */
1289 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1290         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1291 {
1292         int i, eccsize = chip->ecc.size;
1293         int eccbytes = chip->ecc.bytes;
1294         int eccsteps = chip->ecc.steps;
1295         uint8_t *p = buf;
1296         uint8_t *ecc_code = chip->buffers->ecccode;
1297         uint32_t *eccpos = chip->ecc.layout->eccpos;
1298         uint8_t *ecc_calc = chip->buffers->ecccalc;
1299         unsigned int max_bitflips = 0;
1300
1301         /* Read the OOB area first */
1302         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1303         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1304         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1305
1306         for (i = 0; i < chip->ecc.total; i++)
1307                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1308
1309         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1310                 int stat;
1311
1312                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1313                 chip->read_buf(mtd, p, eccsize);
1314                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1315
1316                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1317                 if (stat < 0) {
1318                         mtd->ecc_stats.failed++;
1319                 } else {
1320                         mtd->ecc_stats.corrected += stat;
1321                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1322                 }
1323         }
1324         return max_bitflips;
1325 }
1326
1327 /**
1328  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1329  * @mtd: mtd info structure
1330  * @chip: nand chip info structure
1331  * @buf: buffer to store read data
1332  * @oob_required: caller requires OOB data read to chip->oob_poi
1333  * @page: page number to read
1334  *
1335  * The hw generator calculates the error syndrome automatically. Therefore we
1336  * need a special oob layout and handling.
1337  */
1338 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1339                                    uint8_t *buf, int oob_required, int page)
1340 {
1341         int i, eccsize = chip->ecc.size;
1342         int eccbytes = chip->ecc.bytes;
1343         int eccsteps = chip->ecc.steps;
1344         uint8_t *p = buf;
1345         uint8_t *oob = chip->oob_poi;
1346         unsigned int max_bitflips = 0;
1347
1348         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1349                 int stat;
1350
1351                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1352                 chip->read_buf(mtd, p, eccsize);
1353
1354                 if (chip->ecc.prepad) {
1355                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1356                         oob += chip->ecc.prepad;
1357                 }
1358
1359                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1360                 chip->read_buf(mtd, oob, eccbytes);
1361                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1362
1363                 if (stat < 0) {
1364                         mtd->ecc_stats.failed++;
1365                 } else {
1366                         mtd->ecc_stats.corrected += stat;
1367                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1368                 }
1369
1370                 oob += eccbytes;
1371
1372                 if (chip->ecc.postpad) {
1373                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1374                         oob += chip->ecc.postpad;
1375                 }
1376         }
1377
1378         /* Calculate remaining oob bytes */
1379         i = mtd->oobsize - (oob - chip->oob_poi);
1380         if (i)
1381                 chip->read_buf(mtd, oob, i);
1382
1383         return max_bitflips;
1384 }
1385
1386 /**
1387  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1388  * @chip: nand chip structure
1389  * @oob: oob destination address
1390  * @ops: oob ops structure
1391  * @len: size of oob to transfer
1392  */
1393 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1394                                   struct mtd_oob_ops *ops, size_t len)
1395 {
1396         switch (ops->mode) {
1397
1398         case MTD_OPS_PLACE_OOB:
1399         case MTD_OPS_RAW:
1400                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1401                 return oob + len;
1402
1403         case MTD_OPS_AUTO_OOB: {
1404                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1405                 uint32_t boffs = 0, roffs = ops->ooboffs;
1406                 size_t bytes = 0;
1407
1408                 for (; free->length && len; free++, len -= bytes) {
1409                         /* Read request not from offset 0? */
1410                         if (unlikely(roffs)) {
1411                                 if (roffs >= free->length) {
1412                                         roffs -= free->length;
1413                                         continue;
1414                                 }
1415                                 boffs = free->offset + roffs;
1416                                 bytes = min_t(size_t, len,
1417                                               (free->length - roffs));
1418                                 roffs = 0;
1419                         } else {
1420                                 bytes = min_t(size_t, len, free->length);
1421                                 boffs = free->offset;
1422                         }
1423                         memcpy(oob, chip->oob_poi + boffs, bytes);
1424                         oob += bytes;
1425                 }
1426                 return oob;
1427         }
1428         default:
1429                 BUG();
1430         }
1431         return NULL;
1432 }
1433
1434 /**
1435  * nand_do_read_ops - [INTERN] Read data with ECC
1436  * @mtd: MTD device structure
1437  * @from: offset to read from
1438  * @ops: oob ops structure
1439  *
1440  * Internal function. Called with chip held.
1441  */
1442 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1443                             struct mtd_oob_ops *ops)
1444 {
1445         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1446         struct nand_chip *chip = mtd->priv;
1447         struct mtd_ecc_stats stats;
1448         int ret = 0;
1449         uint32_t readlen = ops->len;
1450         uint32_t oobreadlen = ops->ooblen;
1451         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1452                 mtd->oobavail : mtd->oobsize;
1453
1454         uint8_t *bufpoi, *oob, *buf;
1455         unsigned int max_bitflips = 0;
1456
1457         stats = mtd->ecc_stats;
1458
1459         chipnr = (int)(from >> chip->chip_shift);
1460         chip->select_chip(mtd, chipnr);
1461
1462         realpage = (int)(from >> chip->page_shift);
1463         page = realpage & chip->pagemask;
1464
1465         col = (int)(from & (mtd->writesize - 1));
1466
1467         buf = ops->datbuf;
1468         oob = ops->oobbuf;
1469         oob_required = oob ? 1 : 0;
1470
1471         while (1) {
1472                 bytes = min(mtd->writesize - col, readlen);
1473                 aligned = (bytes == mtd->writesize);
1474
1475                 /* Is the current page in the buffer? */
1476                 if (realpage != chip->pagebuf || oob) {
1477                         bufpoi = aligned ? buf : chip->buffers->databuf;
1478
1479                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1480
1481                         /*
1482                          * Now read the page into the buffer.  Absent an error,
1483                          * the read methods return max bitflips per ecc step.
1484                          */
1485                         if (unlikely(ops->mode == MTD_OPS_RAW))
1486                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1487                                                               oob_required,
1488                                                               page);
1489                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1490                                  !oob)
1491                                 ret = chip->ecc.read_subpage(mtd, chip,
1492                                                         col, bytes, bufpoi);
1493                         else
1494                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1495                                                           oob_required, page);
1496                         if (ret < 0) {
1497                                 if (!aligned)
1498                                         /* Invalidate page cache */
1499                                         chip->pagebuf = -1;
1500                                 break;
1501                         }
1502
1503                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1504
1505                         /* Transfer not aligned data */
1506                         if (!aligned) {
1507                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1508                                     !(mtd->ecc_stats.failed - stats.failed) &&
1509                                     (ops->mode != MTD_OPS_RAW)) {
1510                                         chip->pagebuf = realpage;
1511                                         chip->pagebuf_bitflips = ret;
1512                                 } else {
1513                                         /* Invalidate page cache */
1514                                         chip->pagebuf = -1;
1515                                 }
1516                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1517                         }
1518
1519                         buf += bytes;
1520
1521                         if (unlikely(oob)) {
1522                                 int toread = min(oobreadlen, max_oobsize);
1523
1524                                 if (toread) {
1525                                         oob = nand_transfer_oob(chip,
1526                                                 oob, ops, toread);
1527                                         oobreadlen -= toread;
1528                                 }
1529                         }
1530                 } else {
1531                         memcpy(buf, chip->buffers->databuf + col, bytes);
1532                         buf += bytes;
1533                         max_bitflips = max_t(unsigned int, max_bitflips,
1534                                              chip->pagebuf_bitflips);
1535                 }
1536
1537                 readlen -= bytes;
1538
1539                 if (!readlen)
1540                         break;
1541
1542                 /* For subsequent reads align to page boundary */
1543                 col = 0;
1544                 /* Increment page address */
1545                 realpage++;
1546
1547                 page = realpage & chip->pagemask;
1548                 /* Check, if we cross a chip boundary */
1549                 if (!page) {
1550                         chipnr++;
1551                         chip->select_chip(mtd, -1);
1552                         chip->select_chip(mtd, chipnr);
1553                 }
1554         }
1555         chip->select_chip(mtd, -1);
1556
1557         ops->retlen = ops->len - (size_t) readlen;
1558         if (oob)
1559                 ops->oobretlen = ops->ooblen - oobreadlen;
1560
1561         if (ret < 0)
1562                 return ret;
1563
1564         if (mtd->ecc_stats.failed - stats.failed)
1565                 return -EBADMSG;
1566
1567         return max_bitflips;
1568 }
1569
1570 /**
1571  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1572  * @mtd: MTD device structure
1573  * @from: offset to read from
1574  * @len: number of bytes to read
1575  * @retlen: pointer to variable to store the number of read bytes
1576  * @buf: the databuffer to put data
1577  *
1578  * Get hold of the chip and call nand_do_read.
1579  */
1580 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1581                      size_t *retlen, uint8_t *buf)
1582 {
1583         struct mtd_oob_ops ops;
1584         int ret;
1585
1586         nand_get_device(mtd, FL_READING);
1587         ops.len = len;
1588         ops.datbuf = buf;
1589         ops.oobbuf = NULL;
1590         ops.mode = MTD_OPS_PLACE_OOB;
1591         ret = nand_do_read_ops(mtd, from, &ops);
1592         *retlen = ops.retlen;
1593         nand_release_device(mtd);
1594         return ret;
1595 }
1596
1597 /**
1598  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1599  * @mtd: mtd info structure
1600  * @chip: nand chip info structure
1601  * @page: page number to read
1602  */
1603 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1604                              int page)
1605 {
1606         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1607         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1608         return 0;
1609 }
1610
1611 /**
1612  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1613  *                          with syndromes
1614  * @mtd: mtd info structure
1615  * @chip: nand chip info structure
1616  * @page: page number to read
1617  */
1618 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1619                                   int page)
1620 {
1621         uint8_t *buf = chip->oob_poi;
1622         int length = mtd->oobsize;
1623         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1624         int eccsize = chip->ecc.size;
1625         uint8_t *bufpoi = buf;
1626         int i, toread, sndrnd = 0, pos;
1627
1628         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1629         for (i = 0; i < chip->ecc.steps; i++) {
1630                 if (sndrnd) {
1631                         pos = eccsize + i * (eccsize + chunk);
1632                         if (mtd->writesize > 512)
1633                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1634                         else
1635                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1636                 } else
1637                         sndrnd = 1;
1638                 toread = min_t(int, length, chunk);
1639                 chip->read_buf(mtd, bufpoi, toread);
1640                 bufpoi += toread;
1641                 length -= toread;
1642         }
1643         if (length > 0)
1644                 chip->read_buf(mtd, bufpoi, length);
1645
1646         return 0;
1647 }
1648
1649 /**
1650  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1651  * @mtd: mtd info structure
1652  * @chip: nand chip info structure
1653  * @page: page number to write
1654  */
1655 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1656                               int page)
1657 {
1658         int status = 0;
1659         const uint8_t *buf = chip->oob_poi;
1660         int length = mtd->oobsize;
1661
1662         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1663         chip->write_buf(mtd, buf, length);
1664         /* Send command to program the OOB data */
1665         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1666
1667         status = chip->waitfunc(mtd, chip);
1668
1669         return status & NAND_STATUS_FAIL ? -EIO : 0;
1670 }
1671
1672 /**
1673  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1674  *                           with syndrome - only for large page flash
1675  * @mtd: mtd info structure
1676  * @chip: nand chip info structure
1677  * @page: page number to write
1678  */
1679 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1680                                    struct nand_chip *chip, int page)
1681 {
1682         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1683         int eccsize = chip->ecc.size, length = mtd->oobsize;
1684         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1685         const uint8_t *bufpoi = chip->oob_poi;
1686
1687         /*
1688          * data-ecc-data-ecc ... ecc-oob
1689          * or
1690          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1691          */
1692         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1693                 pos = steps * (eccsize + chunk);
1694                 steps = 0;
1695         } else
1696                 pos = eccsize;
1697
1698         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1699         for (i = 0; i < steps; i++) {
1700                 if (sndcmd) {
1701                         if (mtd->writesize <= 512) {
1702                                 uint32_t fill = 0xFFFFFFFF;
1703
1704                                 len = eccsize;
1705                                 while (len > 0) {
1706                                         int num = min_t(int, len, 4);
1707                                         chip->write_buf(mtd, (uint8_t *)&fill,
1708                                                         num);
1709                                         len -= num;
1710                                 }
1711                         } else {
1712                                 pos = eccsize + i * (eccsize + chunk);
1713                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1714                         }
1715                 } else
1716                         sndcmd = 1;
1717                 len = min_t(int, length, chunk);
1718                 chip->write_buf(mtd, bufpoi, len);
1719                 bufpoi += len;
1720                 length -= len;
1721         }
1722         if (length > 0)
1723                 chip->write_buf(mtd, bufpoi, length);
1724
1725         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1726         status = chip->waitfunc(mtd, chip);
1727
1728         return status & NAND_STATUS_FAIL ? -EIO : 0;
1729 }
1730
1731 /**
1732  * nand_do_read_oob - [INTERN] NAND read out-of-band
1733  * @mtd: MTD device structure
1734  * @from: offset to read from
1735  * @ops: oob operations description structure
1736  *
1737  * NAND read out-of-band data from the spare area.
1738  */
1739 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1740                             struct mtd_oob_ops *ops)
1741 {
1742         int page, realpage, chipnr;
1743         struct nand_chip *chip = mtd->priv;
1744         struct mtd_ecc_stats stats;
1745         int readlen = ops->ooblen;
1746         int len;
1747         uint8_t *buf = ops->oobbuf;
1748         int ret = 0;
1749
1750         pr_debug("%s: from = 0x%08Lx, len = %i\n",
1751                         __func__, (unsigned long long)from, readlen);
1752
1753         stats = mtd->ecc_stats;
1754
1755         if (ops->mode == MTD_OPS_AUTO_OOB)
1756                 len = chip->ecc.layout->oobavail;
1757         else
1758                 len = mtd->oobsize;
1759
1760         if (unlikely(ops->ooboffs >= len)) {
1761                 pr_debug("%s: attempt to start read outside oob\n",
1762                                 __func__);
1763                 return -EINVAL;
1764         }
1765
1766         /* Do not allow reads past end of device */
1767         if (unlikely(from >= mtd->size ||
1768                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1769                                         (from >> chip->page_shift)) * len)) {
1770                 pr_debug("%s: attempt to read beyond end of device\n",
1771                                 __func__);
1772                 return -EINVAL;
1773         }
1774
1775         chipnr = (int)(from >> chip->chip_shift);
1776         chip->select_chip(mtd, chipnr);
1777
1778         /* Shift to get page */
1779         realpage = (int)(from >> chip->page_shift);
1780         page = realpage & chip->pagemask;
1781
1782         while (1) {
1783                 if (ops->mode == MTD_OPS_RAW)
1784                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
1785                 else
1786                         ret = chip->ecc.read_oob(mtd, chip, page);
1787
1788                 if (ret < 0)
1789                         break;
1790
1791                 len = min(len, readlen);
1792                 buf = nand_transfer_oob(chip, buf, ops, len);
1793
1794                 readlen -= len;
1795                 if (!readlen)
1796                         break;
1797
1798                 /* Increment page address */
1799                 realpage++;
1800
1801                 page = realpage & chip->pagemask;
1802                 /* Check, if we cross a chip boundary */
1803                 if (!page) {
1804                         chipnr++;
1805                         chip->select_chip(mtd, -1);
1806                         chip->select_chip(mtd, chipnr);
1807                 }
1808         }
1809         chip->select_chip(mtd, -1);
1810
1811         ops->oobretlen = ops->ooblen - readlen;
1812
1813         if (ret < 0)
1814                 return ret;
1815
1816         if (mtd->ecc_stats.failed - stats.failed)
1817                 return -EBADMSG;
1818
1819         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1820 }
1821
1822 /**
1823  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1824  * @mtd: MTD device structure
1825  * @from: offset to read from
1826  * @ops: oob operation description structure
1827  *
1828  * NAND read data and/or out-of-band data.
1829  */
1830 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1831                          struct mtd_oob_ops *ops)
1832 {
1833         int ret = -ENOTSUPP;
1834
1835         ops->retlen = 0;
1836
1837         /* Do not allow reads past end of device */
1838         if (ops->datbuf && (from + ops->len) > mtd->size) {
1839                 pr_debug("%s: attempt to read beyond end of device\n",
1840                                 __func__);
1841                 return -EINVAL;
1842         }
1843
1844         nand_get_device(mtd, FL_READING);
1845
1846         switch (ops->mode) {
1847         case MTD_OPS_PLACE_OOB:
1848         case MTD_OPS_AUTO_OOB:
1849         case MTD_OPS_RAW:
1850                 break;
1851
1852         default:
1853                 goto out;
1854         }
1855
1856         if (!ops->datbuf)
1857                 ret = nand_do_read_oob(mtd, from, ops);
1858         else
1859                 ret = nand_do_read_ops(mtd, from, ops);
1860
1861 out:
1862         nand_release_device(mtd);
1863         return ret;
1864 }
1865
1866
1867 /**
1868  * nand_write_page_raw - [INTERN] raw page write function
1869  * @mtd: mtd info structure
1870  * @chip: nand chip info structure
1871  * @buf: data buffer
1872  * @oob_required: must write chip->oob_poi to OOB
1873  *
1874  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1875  */
1876 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1877                                 const uint8_t *buf, int oob_required)
1878 {
1879         chip->write_buf(mtd, buf, mtd->writesize);
1880         if (oob_required)
1881                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1882
1883         return 0;
1884 }
1885
1886 /**
1887  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1888  * @mtd: mtd info structure
1889  * @chip: nand chip info structure
1890  * @buf: data buffer
1891  * @oob_required: must write chip->oob_poi to OOB
1892  *
1893  * We need a special oob layout and handling even when ECC isn't checked.
1894  */
1895 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1896                                         struct nand_chip *chip,
1897                                         const uint8_t *buf, int oob_required)
1898 {
1899         int eccsize = chip->ecc.size;
1900         int eccbytes = chip->ecc.bytes;
1901         uint8_t *oob = chip->oob_poi;
1902         int steps, size;
1903
1904         for (steps = chip->ecc.steps; steps > 0; steps--) {
1905                 chip->write_buf(mtd, buf, eccsize);
1906                 buf += eccsize;
1907
1908                 if (chip->ecc.prepad) {
1909                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1910                         oob += chip->ecc.prepad;
1911                 }
1912
1913                 chip->read_buf(mtd, oob, eccbytes);
1914                 oob += eccbytes;
1915
1916                 if (chip->ecc.postpad) {
1917                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1918                         oob += chip->ecc.postpad;
1919                 }
1920         }
1921
1922         size = mtd->oobsize - (oob - chip->oob_poi);
1923         if (size)
1924                 chip->write_buf(mtd, oob, size);
1925
1926         return 0;
1927 }
1928 /**
1929  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1930  * @mtd: mtd info structure
1931  * @chip: nand chip info structure
1932  * @buf: data buffer
1933  * @oob_required: must write chip->oob_poi to OOB
1934  */
1935 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1936                                   const uint8_t *buf, int oob_required)
1937 {
1938         int i, eccsize = chip->ecc.size;
1939         int eccbytes = chip->ecc.bytes;
1940         int eccsteps = chip->ecc.steps;
1941         uint8_t *ecc_calc = chip->buffers->ecccalc;
1942         const uint8_t *p = buf;
1943         uint32_t *eccpos = chip->ecc.layout->eccpos;
1944
1945         /* Software ECC calculation */
1946         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1947                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1948
1949         for (i = 0; i < chip->ecc.total; i++)
1950                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1951
1952         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1953 }
1954
1955 /**
1956  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1957  * @mtd: mtd info structure
1958  * @chip: nand chip info structure
1959  * @buf: data buffer
1960  * @oob_required: must write chip->oob_poi to OOB
1961  */
1962 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1963                                   const uint8_t *buf, int oob_required)
1964 {
1965         int i, eccsize = chip->ecc.size;
1966         int eccbytes = chip->ecc.bytes;
1967         int eccsteps = chip->ecc.steps;
1968         uint8_t *ecc_calc = chip->buffers->ecccalc;
1969         const uint8_t *p = buf;
1970         uint32_t *eccpos = chip->ecc.layout->eccpos;
1971
1972         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1973                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1974                 chip->write_buf(mtd, p, eccsize);
1975                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1976         }
1977
1978         for (i = 0; i < chip->ecc.total; i++)
1979                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1980
1981         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1982
1983         return 0;
1984 }
1985
1986 /**
1987  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1988  * @mtd: mtd info structure
1989  * @chip: nand chip info structure
1990  * @buf: data buffer
1991  * @oob_required: must write chip->oob_poi to OOB
1992  *
1993  * The hw generator calculates the error syndrome automatically. Therefore we
1994  * need a special oob layout and handling.
1995  */
1996 static int nand_write_page_syndrome(struct mtd_info *mtd,
1997                                     struct nand_chip *chip,
1998                                     const uint8_t *buf, int oob_required)
1999 {
2000         int i, eccsize = chip->ecc.size;
2001         int eccbytes = chip->ecc.bytes;
2002         int eccsteps = chip->ecc.steps;
2003         const uint8_t *p = buf;
2004         uint8_t *oob = chip->oob_poi;
2005
2006         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2007
2008                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2009                 chip->write_buf(mtd, p, eccsize);
2010
2011                 if (chip->ecc.prepad) {
2012                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2013                         oob += chip->ecc.prepad;
2014                 }
2015
2016                 chip->ecc.calculate(mtd, p, oob);
2017                 chip->write_buf(mtd, oob, eccbytes);
2018                 oob += eccbytes;
2019
2020                 if (chip->ecc.postpad) {
2021                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2022                         oob += chip->ecc.postpad;
2023                 }
2024         }
2025
2026         /* Calculate remaining oob bytes */
2027         i = mtd->oobsize - (oob - chip->oob_poi);
2028         if (i)
2029                 chip->write_buf(mtd, oob, i);
2030
2031         return 0;
2032 }
2033
2034 /**
2035  * nand_write_page - [REPLACEABLE] write one page
2036  * @mtd: MTD device structure
2037  * @chip: NAND chip descriptor
2038  * @buf: the data to write
2039  * @oob_required: must write chip->oob_poi to OOB
2040  * @page: page number to write
2041  * @cached: cached programming
2042  * @raw: use _raw version of write_page
2043  */
2044 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2045                            const uint8_t *buf, int oob_required, int page,
2046                            int cached, int raw)
2047 {
2048         int status;
2049
2050         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2051
2052         if (unlikely(raw))
2053                 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
2054         else
2055                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2056
2057         if (status < 0)
2058                 return status;
2059
2060         /*
2061          * Cached progamming disabled for now. Not sure if it's worth the
2062          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2063          */
2064         cached = 0;
2065
2066         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2067
2068                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2069                 status = chip->waitfunc(mtd, chip);
2070                 /*
2071                  * See if operation failed and additional status checks are
2072                  * available.
2073                  */
2074                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2075                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2076                                                page);
2077
2078                 if (status & NAND_STATUS_FAIL)
2079                         return -EIO;
2080         } else {
2081                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2082                 status = chip->waitfunc(mtd, chip);
2083         }
2084
2085         return 0;
2086 }
2087
2088 /**
2089  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2090  * @mtd: MTD device structure
2091  * @oob: oob data buffer
2092  * @len: oob data write length
2093  * @ops: oob ops structure
2094  */
2095 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2096                               struct mtd_oob_ops *ops)
2097 {
2098         struct nand_chip *chip = mtd->priv;
2099
2100         /*
2101          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2102          * data from a previous OOB read.
2103          */
2104         memset(chip->oob_poi, 0xff, mtd->oobsize);
2105
2106         switch (ops->mode) {
2107
2108         case MTD_OPS_PLACE_OOB:
2109         case MTD_OPS_RAW:
2110                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2111                 return oob + len;
2112
2113         case MTD_OPS_AUTO_OOB: {
2114                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2115                 uint32_t boffs = 0, woffs = ops->ooboffs;
2116                 size_t bytes = 0;
2117
2118                 for (; free->length && len; free++, len -= bytes) {
2119                         /* Write request not from offset 0? */
2120                         if (unlikely(woffs)) {
2121                                 if (woffs >= free->length) {
2122                                         woffs -= free->length;
2123                                         continue;
2124                                 }
2125                                 boffs = free->offset + woffs;
2126                                 bytes = min_t(size_t, len,
2127                                               (free->length - woffs));
2128                                 woffs = 0;
2129                         } else {
2130                                 bytes = min_t(size_t, len, free->length);
2131                                 boffs = free->offset;
2132                         }
2133                         memcpy(chip->oob_poi + boffs, oob, bytes);
2134                         oob += bytes;
2135                 }
2136                 return oob;
2137         }
2138         default:
2139                 BUG();
2140         }
2141         return NULL;
2142 }
2143
2144 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2145
2146 /**
2147  * nand_do_write_ops - [INTERN] NAND write with ECC
2148  * @mtd: MTD device structure
2149  * @to: offset to write to
2150  * @ops: oob operations description structure
2151  *
2152  * NAND write with ECC.
2153  */
2154 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2155                              struct mtd_oob_ops *ops)
2156 {
2157         int chipnr, realpage, page, blockmask, column;
2158         struct nand_chip *chip = mtd->priv;
2159         uint32_t writelen = ops->len;
2160
2161         uint32_t oobwritelen = ops->ooblen;
2162         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2163                                 mtd->oobavail : mtd->oobsize;
2164
2165         uint8_t *oob = ops->oobbuf;
2166         uint8_t *buf = ops->datbuf;
2167         int ret, subpage;
2168         int oob_required = oob ? 1 : 0;
2169
2170         ops->retlen = 0;
2171         if (!writelen)
2172                 return 0;
2173
2174         /* Reject writes, which are not page aligned */
2175         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2176                 pr_notice("%s: attempt to write non page aligned data\n",
2177                            __func__);
2178                 return -EINVAL;
2179         }
2180
2181         column = to & (mtd->writesize - 1);
2182         subpage = column || (writelen & (mtd->writesize - 1));
2183
2184         if (subpage && oob)
2185                 return -EINVAL;
2186
2187         chipnr = (int)(to >> chip->chip_shift);
2188         chip->select_chip(mtd, chipnr);
2189
2190         /* Check, if it is write protected */
2191         if (nand_check_wp(mtd)) {
2192                 ret = -EIO;
2193                 goto err_out;
2194         }
2195
2196         realpage = (int)(to >> chip->page_shift);
2197         page = realpage & chip->pagemask;
2198         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2199
2200         /* Invalidate the page cache, when we write to the cached page */
2201         if (to <= (chip->pagebuf << chip->page_shift) &&
2202             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2203                 chip->pagebuf = -1;
2204
2205         /* Don't allow multipage oob writes with offset */
2206         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2207                 ret = -EINVAL;
2208                 goto err_out;
2209         }
2210
2211         while (1) {
2212                 int bytes = mtd->writesize;
2213                 int cached = writelen > bytes && page != blockmask;
2214                 uint8_t *wbuf = buf;
2215
2216                 /* Partial page write? */
2217                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2218                         cached = 0;
2219                         bytes = min_t(int, bytes - column, (int) writelen);
2220                         chip->pagebuf = -1;
2221                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2222                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2223                         wbuf = chip->buffers->databuf;
2224                 }
2225
2226                 if (unlikely(oob)) {
2227                         size_t len = min(oobwritelen, oobmaxlen);
2228                         oob = nand_fill_oob(mtd, oob, len, ops);
2229                         oobwritelen -= len;
2230                 } else {
2231                         /* We still need to erase leftover OOB data */
2232                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2233                 }
2234
2235                 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2236                                        cached, (ops->mode == MTD_OPS_RAW));
2237                 if (ret)
2238                         break;
2239
2240                 writelen -= bytes;
2241                 if (!writelen)
2242                         break;
2243
2244                 column = 0;
2245                 buf += bytes;
2246                 realpage++;
2247
2248                 page = realpage & chip->pagemask;
2249                 /* Check, if we cross a chip boundary */
2250                 if (!page) {
2251                         chipnr++;
2252                         chip->select_chip(mtd, -1);
2253                         chip->select_chip(mtd, chipnr);
2254                 }
2255         }
2256
2257         ops->retlen = ops->len - writelen;
2258         if (unlikely(oob))
2259                 ops->oobretlen = ops->ooblen;
2260
2261 err_out:
2262         chip->select_chip(mtd, -1);
2263         return ret;
2264 }
2265
2266 /**
2267  * panic_nand_write - [MTD Interface] NAND write with ECC
2268  * @mtd: MTD device structure
2269  * @to: offset to write to
2270  * @len: number of bytes to write
2271  * @retlen: pointer to variable to store the number of written bytes
2272  * @buf: the data to write
2273  *
2274  * NAND write with ECC. Used when performing writes in interrupt context, this
2275  * may for example be called by mtdoops when writing an oops while in panic.
2276  */
2277 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2278                             size_t *retlen, const uint8_t *buf)
2279 {
2280         struct nand_chip *chip = mtd->priv;
2281         struct mtd_oob_ops ops;
2282         int ret;
2283
2284         /* Wait for the device to get ready */
2285         panic_nand_wait(mtd, chip, 400);
2286
2287         /* Grab the device */
2288         panic_nand_get_device(chip, mtd, FL_WRITING);
2289
2290         ops.len = len;
2291         ops.datbuf = (uint8_t *)buf;
2292         ops.oobbuf = NULL;
2293         ops.mode = MTD_OPS_PLACE_OOB;
2294
2295         ret = nand_do_write_ops(mtd, to, &ops);
2296
2297         *retlen = ops.retlen;
2298         return ret;
2299 }
2300
2301 /**
2302  * nand_write - [MTD Interface] NAND write with ECC
2303  * @mtd: MTD device structure
2304  * @to: offset to write to
2305  * @len: number of bytes to write
2306  * @retlen: pointer to variable to store the number of written bytes
2307  * @buf: the data to write
2308  *
2309  * NAND write with ECC.
2310  */
2311 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2312                           size_t *retlen, const uint8_t *buf)
2313 {
2314         struct mtd_oob_ops ops;
2315         int ret;
2316
2317         nand_get_device(mtd, FL_WRITING);
2318         ops.len = len;
2319         ops.datbuf = (uint8_t *)buf;
2320         ops.oobbuf = NULL;
2321         ops.mode = MTD_OPS_PLACE_OOB;
2322         ret = nand_do_write_ops(mtd, to, &ops);
2323         *retlen = ops.retlen;
2324         nand_release_device(mtd);
2325         return ret;
2326 }
2327
2328 /**
2329  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2330  * @mtd: MTD device structure
2331  * @to: offset to write to
2332  * @ops: oob operation description structure
2333  *
2334  * NAND write out-of-band.
2335  */
2336 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2337                              struct mtd_oob_ops *ops)
2338 {
2339         int chipnr, page, status, len;
2340         struct nand_chip *chip = mtd->priv;
2341
2342         pr_debug("%s: to = 0x%08x, len = %i\n",
2343                          __func__, (unsigned int)to, (int)ops->ooblen);
2344
2345         if (ops->mode == MTD_OPS_AUTO_OOB)
2346                 len = chip->ecc.layout->oobavail;
2347         else
2348                 len = mtd->oobsize;
2349
2350         /* Do not allow write past end of page */
2351         if ((ops->ooboffs + ops->ooblen) > len) {
2352                 pr_debug("%s: attempt to write past end of page\n",
2353                                 __func__);
2354                 return -EINVAL;
2355         }
2356
2357         if (unlikely(ops->ooboffs >= len)) {
2358                 pr_debug("%s: attempt to start write outside oob\n",
2359                                 __func__);
2360                 return -EINVAL;
2361         }
2362
2363         /* Do not allow write past end of device */
2364         if (unlikely(to >= mtd->size ||
2365                      ops->ooboffs + ops->ooblen >
2366                         ((mtd->size >> chip->page_shift) -
2367                          (to >> chip->page_shift)) * len)) {
2368                 pr_debug("%s: attempt to write beyond end of device\n",
2369                                 __func__);
2370                 return -EINVAL;
2371         }
2372
2373         chipnr = (int)(to >> chip->chip_shift);
2374         chip->select_chip(mtd, chipnr);
2375
2376         /* Shift to get page */
2377         page = (int)(to >> chip->page_shift);
2378
2379         /*
2380          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2381          * of my DiskOnChip 2000 test units) will clear the whole data page too
2382          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2383          * it in the doc2000 driver in August 1999.  dwmw2.
2384          */
2385         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2386
2387         /* Check, if it is write protected */
2388         if (nand_check_wp(mtd)) {
2389                 chip->select_chip(mtd, -1);
2390                 return -EROFS;
2391         }
2392
2393         /* Invalidate the page cache, if we write to the cached page */
2394         if (page == chip->pagebuf)
2395                 chip->pagebuf = -1;
2396
2397         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2398
2399         if (ops->mode == MTD_OPS_RAW)
2400                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2401         else
2402                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2403
2404         chip->select_chip(mtd, -1);
2405
2406         if (status)
2407                 return status;
2408
2409         ops->oobretlen = ops->ooblen;
2410
2411         return 0;
2412 }
2413
2414 /**
2415  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2416  * @mtd: MTD device structure
2417  * @to: offset to write to
2418  * @ops: oob operation description structure
2419  */
2420 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2421                           struct mtd_oob_ops *ops)
2422 {
2423         int ret = -ENOTSUPP;
2424
2425         ops->retlen = 0;
2426
2427         /* Do not allow writes past end of device */
2428         if (ops->datbuf && (to + ops->len) > mtd->size) {
2429                 pr_debug("%s: attempt to write beyond end of device\n",
2430                                 __func__);
2431                 return -EINVAL;
2432         }
2433
2434         nand_get_device(mtd, FL_WRITING);
2435
2436         switch (ops->mode) {
2437         case MTD_OPS_PLACE_OOB:
2438         case MTD_OPS_AUTO_OOB:
2439         case MTD_OPS_RAW:
2440                 break;
2441
2442         default:
2443                 goto out;
2444         }
2445
2446         if (!ops->datbuf)
2447                 ret = nand_do_write_oob(mtd, to, ops);
2448         else
2449                 ret = nand_do_write_ops(mtd, to, ops);
2450
2451 out:
2452         nand_release_device(mtd);
2453         return ret;
2454 }
2455
2456 /**
2457  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2458  * @mtd: MTD device structure
2459  * @page: the page address of the block which will be erased
2460  *
2461  * Standard erase command for NAND chips.
2462  */
2463 static void single_erase_cmd(struct mtd_info *mtd, int page)
2464 {
2465         struct nand_chip *chip = mtd->priv;
2466         /* Send commands to erase a block */
2467         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2468         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2469 }
2470
2471 /**
2472  * multi_erase_cmd - [GENERIC] AND specific block erase command function
2473  * @mtd: MTD device structure
2474  * @page: the page address of the block which will be erased
2475  *
2476  * AND multi block erase command function. Erase 4 consecutive blocks.
2477  */
2478 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2479 {
2480         struct nand_chip *chip = mtd->priv;
2481         /* Send commands to erase a block */
2482         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2483         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2485         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2486         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2487 }
2488
2489 /**
2490  * nand_erase - [MTD Interface] erase block(s)
2491  * @mtd: MTD device structure
2492  * @instr: erase instruction
2493  *
2494  * Erase one ore more blocks.
2495  */
2496 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2497 {
2498         return nand_erase_nand(mtd, instr, 0);
2499 }
2500
2501 #define BBT_PAGE_MASK   0xffffff3f
2502 /**
2503  * nand_erase_nand - [INTERN] erase block(s)
2504  * @mtd: MTD device structure
2505  * @instr: erase instruction
2506  * @allowbbt: allow erasing the bbt area
2507  *
2508  * Erase one ore more blocks.
2509  */
2510 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2511                     int allowbbt)
2512 {
2513         int page, status, pages_per_block, ret, chipnr;
2514         struct nand_chip *chip = mtd->priv;
2515         loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2516         unsigned int bbt_masked_page = 0xffffffff;
2517         loff_t len;
2518
2519         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2520                         __func__, (unsigned long long)instr->addr,
2521                         (unsigned long long)instr->len);
2522
2523         if (check_offs_len(mtd, instr->addr, instr->len))
2524                 return -EINVAL;
2525
2526         /* Grab the lock and see if the device is available */
2527         nand_get_device(mtd, FL_ERASING);
2528
2529         /* Shift to get first page */
2530         page = (int)(instr->addr >> chip->page_shift);
2531         chipnr = (int)(instr->addr >> chip->chip_shift);
2532
2533         /* Calculate pages in each block */
2534         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2535
2536         /* Select the NAND device */
2537         chip->select_chip(mtd, chipnr);
2538
2539         /* Check, if it is write protected */
2540         if (nand_check_wp(mtd)) {
2541                 pr_debug("%s: device is write protected!\n",
2542                                 __func__);
2543                 instr->state = MTD_ERASE_FAILED;
2544                 goto erase_exit;
2545         }
2546
2547         /*
2548          * If BBT requires refresh, set the BBT page mask to see if the BBT
2549          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2550          * can not be matched. This is also done when the bbt is actually
2551          * erased to avoid recursive updates.
2552          */
2553         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2554                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2555
2556         /* Loop through the pages */
2557         len = instr->len;
2558
2559         instr->state = MTD_ERASING;
2560
2561         while (len) {
2562                 /* Check if we have a bad block, we do not erase bad blocks! */
2563                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2564                                         chip->page_shift, 0, allowbbt)) {
2565                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2566                                     __func__, page);
2567                         instr->state = MTD_ERASE_FAILED;
2568                         goto erase_exit;
2569                 }
2570
2571                 /*
2572                  * Invalidate the page cache, if we erase the block which
2573                  * contains the current cached page.
2574                  */
2575                 if (page <= chip->pagebuf && chip->pagebuf <
2576                     (page + pages_per_block))
2577                         chip->pagebuf = -1;
2578
2579                 chip->erase_cmd(mtd, page & chip->pagemask);
2580
2581                 status = chip->waitfunc(mtd, chip);
2582
2583                 /*
2584                  * See if operation failed and additional status checks are
2585                  * available
2586                  */
2587                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2588                         status = chip->errstat(mtd, chip, FL_ERASING,
2589                                                status, page);
2590
2591                 /* See if block erase succeeded */
2592                 if (status & NAND_STATUS_FAIL) {
2593                         pr_debug("%s: failed erase, page 0x%08x\n",
2594                                         __func__, page);
2595                         instr->state = MTD_ERASE_FAILED;
2596                         instr->fail_addr =
2597                                 ((loff_t)page << chip->page_shift);
2598                         goto erase_exit;
2599                 }
2600
2601                 /*
2602                  * If BBT requires refresh, set the BBT rewrite flag to the
2603                  * page being erased.
2604                  */
2605                 if (bbt_masked_page != 0xffffffff &&
2606                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2607                             rewrite_bbt[chipnr] =
2608                                         ((loff_t)page << chip->page_shift);
2609
2610                 /* Increment page address and decrement length */
2611                 len -= (1 << chip->phys_erase_shift);
2612                 page += pages_per_block;
2613
2614                 /* Check, if we cross a chip boundary */
2615                 if (len && !(page & chip->pagemask)) {
2616                         chipnr++;
2617                         chip->select_chip(mtd, -1);
2618                         chip->select_chip(mtd, chipnr);
2619
2620                         /*
2621                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2622                          * page mask to see if this BBT should be rewritten.
2623                          */
2624                         if (bbt_masked_page != 0xffffffff &&
2625                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2626                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2627                                         BBT_PAGE_MASK;
2628                 }
2629         }
2630         instr->state = MTD_ERASE_DONE;
2631
2632 erase_exit:
2633
2634         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2635
2636         /* Deselect and wake up anyone waiting on the device */
2637         chip->select_chip(mtd, -1);
2638         nand_release_device(mtd);
2639
2640         /* Do call back function */
2641         if (!ret)
2642                 mtd_erase_callback(instr);
2643
2644         /*
2645          * If BBT requires refresh and erase was successful, rewrite any
2646          * selected bad block tables.
2647          */
2648         if (bbt_masked_page == 0xffffffff || ret)
2649                 return ret;
2650
2651         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2652                 if (!rewrite_bbt[chipnr])
2653                         continue;
2654                 /* Update the BBT for chip */
2655                 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2656                                 __func__, chipnr, rewrite_bbt[chipnr],
2657                                 chip->bbt_td->pages[chipnr]);
2658                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2659         }
2660
2661         /* Return more or less happy */
2662         return ret;
2663 }
2664
2665 /**
2666  * nand_sync - [MTD Interface] sync
2667  * @mtd: MTD device structure
2668  *
2669  * Sync is actually a wait for chip ready function.
2670  */
2671 static void nand_sync(struct mtd_info *mtd)
2672 {
2673         pr_debug("%s: called\n", __func__);
2674
2675         /* Grab the lock and see if the device is available */
2676         nand_get_device(mtd, FL_SYNCING);
2677         /* Release it and go back */
2678         nand_release_device(mtd);
2679 }
2680
2681 /**
2682  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2683  * @mtd: MTD device structure
2684  * @offs: offset relative to mtd start
2685  */
2686 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2687 {
2688         return nand_block_checkbad(mtd, offs, 1, 0);
2689 }
2690
2691 /**
2692  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2693  * @mtd: MTD device structure
2694  * @ofs: offset relative to mtd start
2695  */
2696 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2697 {
2698         struct nand_chip *chip = mtd->priv;
2699         int ret;
2700
2701         ret = nand_block_isbad(mtd, ofs);
2702         if (ret) {
2703                 /* If it was bad already, return success and do nothing */
2704                 if (ret > 0)
2705                         return 0;
2706                 return ret;
2707         }
2708
2709         return chip->block_markbad(mtd, ofs);
2710 }
2711
2712 /**
2713  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2714  * @mtd: MTD device structure
2715  * @chip: nand chip info structure
2716  * @addr: feature address.
2717  * @subfeature_param: the subfeature parameters, a four bytes array.
2718  */
2719 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2720                         int addr, uint8_t *subfeature_param)
2721 {
2722         int status;
2723
2724         if (!chip->onfi_version)
2725                 return -EINVAL;
2726
2727         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2728         chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2729         status = chip->waitfunc(mtd, chip);
2730         if (status & NAND_STATUS_FAIL)
2731                 return -EIO;
2732         return 0;
2733 }
2734
2735 /**
2736  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2737  * @mtd: MTD device structure
2738  * @chip: nand chip info structure
2739  * @addr: feature address.
2740  * @subfeature_param: the subfeature parameters, a four bytes array.
2741  */
2742 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2743                         int addr, uint8_t *subfeature_param)
2744 {
2745         if (!chip->onfi_version)
2746                 return -EINVAL;
2747
2748         /* clear the sub feature parameters */
2749         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2750
2751         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2752         chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2753         return 0;
2754 }
2755
2756 /**
2757  * nand_suspend - [MTD Interface] Suspend the NAND flash
2758  * @mtd: MTD device structure
2759  */
2760 static int nand_suspend(struct mtd_info *mtd)
2761 {
2762         return nand_get_device(mtd, FL_PM_SUSPENDED);
2763 }
2764
2765 /**
2766  * nand_resume - [MTD Interface] Resume the NAND flash
2767  * @mtd: MTD device structure
2768  */
2769 static void nand_resume(struct mtd_info *mtd)
2770 {
2771         struct nand_chip *chip = mtd->priv;
2772
2773         if (chip->state == FL_PM_SUSPENDED)
2774                 nand_release_device(mtd);
2775         else
2776                 pr_err("%s called for a chip which is not in suspended state\n",
2777                         __func__);
2778 }
2779
2780 /* Set default functions */
2781 static void nand_set_defaults(struct nand_chip *chip, int busw)
2782 {
2783         /* check for proper chip_delay setup, set 20us if not */
2784         if (!chip->chip_delay)
2785                 chip->chip_delay = 20;
2786
2787         /* check, if a user supplied command function given */
2788         if (chip->cmdfunc == NULL)
2789                 chip->cmdfunc = nand_command;
2790
2791         /* check, if a user supplied wait function given */
2792         if (chip->waitfunc == NULL)
2793                 chip->waitfunc = nand_wait;
2794
2795         if (!chip->select_chip)
2796                 chip->select_chip = nand_select_chip;
2797         if (!chip->read_byte)
2798                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2799         if (!chip->read_word)
2800                 chip->read_word = nand_read_word;
2801         if (!chip->block_bad)
2802                 chip->block_bad = nand_block_bad;
2803         if (!chip->block_markbad)
2804                 chip->block_markbad = nand_default_block_markbad;
2805         if (!chip->write_buf)
2806                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2807         if (!chip->read_buf)
2808                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2809         if (!chip->scan_bbt)
2810                 chip->scan_bbt = nand_default_bbt;
2811
2812         if (!chip->controller) {
2813                 chip->controller = &chip->hwcontrol;
2814                 spin_lock_init(&chip->controller->lock);
2815                 init_waitqueue_head(&chip->controller->wq);
2816         }
2817
2818 }
2819
2820 /* Sanitize ONFI strings so we can safely print them */
2821 static void sanitize_string(uint8_t *s, size_t len)
2822 {
2823         ssize_t i;
2824
2825         /* Null terminate */
2826         s[len - 1] = 0;
2827
2828         /* Remove non printable chars */
2829         for (i = 0; i < len - 1; i++) {
2830                 if (s[i] < ' ' || s[i] > 127)
2831                         s[i] = '?';
2832         }
2833
2834         /* Remove trailing spaces */
2835         strim(s);
2836 }
2837
2838 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2839 {
2840         int i;
2841         while (len--) {
2842                 crc ^= *p++ << 8;
2843                 for (i = 0; i < 8; i++)
2844                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2845         }
2846
2847         return crc;
2848 }
2849
2850 /*
2851  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2852  */
2853 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2854                                         int *busw)
2855 {
2856         struct nand_onfi_params *p = &chip->onfi_params;
2857         int i;
2858         int val;
2859
2860         /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2861         if (chip->options & NAND_BUSWIDTH_16) {
2862                 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2863                 return 0;
2864         }
2865         /* Try ONFI for unknown chip or LP */
2866         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2867         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2868                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2869                 return 0;
2870
2871         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2872         for (i = 0; i < 3; i++) {
2873                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2874                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2875                                 le16_to_cpu(p->crc)) {
2876                         pr_info("ONFI param page %d valid\n", i);
2877                         break;
2878                 }
2879         }
2880
2881         if (i == 3)
2882                 return 0;
2883
2884         /* Check version */
2885         val = le16_to_cpu(p->revision);
2886         if (val & (1 << 5))
2887                 chip->onfi_version = 23;
2888         else if (val & (1 << 4))
2889                 chip->onfi_version = 22;
2890         else if (val & (1 << 3))
2891                 chip->onfi_version = 21;
2892         else if (val & (1 << 2))
2893                 chip->onfi_version = 20;
2894         else if (val & (1 << 1))
2895                 chip->onfi_version = 10;
2896         else
2897                 chip->onfi_version = 0;
2898
2899         if (!chip->onfi_version) {
2900                 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2901                 return 0;
2902         }
2903
2904         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2905         sanitize_string(p->model, sizeof(p->model));
2906         if (!mtd->name)
2907                 mtd->name = p->model;
2908         mtd->writesize = le32_to_cpu(p->byte_per_page);
2909         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2910         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2911         chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2912         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2913         *busw = 0;
2914         if (le16_to_cpu(p->features) & 1)
2915                 *busw = NAND_BUSWIDTH_16;
2916
2917         pr_info("ONFI flash detected\n");
2918         return 1;
2919 }
2920
2921 /*
2922  * nand_id_has_period - Check if an ID string has a given wraparound period
2923  * @id_data: the ID string
2924  * @arrlen: the length of the @id_data array
2925  * @period: the period of repitition
2926  *
2927  * Check if an ID string is repeated within a given sequence of bytes at
2928  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2929  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
2930  * if the repetition has a period of @period; otherwise, returns zero.
2931  */
2932 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2933 {
2934         int i, j;
2935         for (i = 0; i < period; i++)
2936                 for (j = i + period; j < arrlen; j += period)
2937                         if (id_data[i] != id_data[j])
2938                                 return 0;
2939         return 1;
2940 }
2941
2942 /*
2943  * nand_id_len - Get the length of an ID string returned by CMD_READID
2944  * @id_data: the ID string
2945  * @arrlen: the length of the @id_data array
2946
2947  * Returns the length of the ID string, according to known wraparound/trailing
2948  * zero patterns. If no pattern exists, returns the length of the array.
2949  */
2950 static int nand_id_len(u8 *id_data, int arrlen)
2951 {
2952         int last_nonzero, period;
2953
2954         /* Find last non-zero byte */
2955         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2956                 if (id_data[last_nonzero])
2957                         break;
2958
2959         /* All zeros */
2960         if (last_nonzero < 0)
2961                 return 0;
2962
2963         /* Calculate wraparound period */
2964         for (period = 1; period < arrlen; period++)
2965                 if (nand_id_has_period(id_data, arrlen, period))
2966                         break;
2967
2968         /* There's a repeated pattern */
2969         if (period < arrlen)
2970                 return period;
2971
2972         /* There are trailing zeros */
2973         if (last_nonzero < arrlen - 1)
2974                 return last_nonzero + 1;
2975
2976         /* No pattern detected */
2977         return arrlen;
2978 }
2979
2980 /*
2981  * Many new NAND share similar device ID codes, which represent the size of the
2982  * chip. The rest of the parameters must be decoded according to generic or
2983  * manufacturer-specific "extended ID" decoding patterns.
2984  */
2985 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2986                                 u8 id_data[8], int *busw)
2987 {
2988         int extid, id_len;
2989         /* The 3rd id byte holds MLC / multichip data */
2990         chip->cellinfo = id_data[2];
2991         /* The 4th id byte is the important one */
2992         extid = id_data[3];
2993
2994         id_len = nand_id_len(id_data, 8);
2995
2996         /*
2997          * Field definitions are in the following datasheets:
2998          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2999          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3000          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
3001          *
3002          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3003          * ID to decide what to do.
3004          */
3005         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3006                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3007                         id_data[5] != 0x00) {
3008                 /* Calc pagesize */
3009                 mtd->writesize = 2048 << (extid & 0x03);
3010                 extid >>= 2;
3011                 /* Calc oobsize */
3012                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3013                 case 1:
3014                         mtd->oobsize = 128;
3015                         break;
3016                 case 2:
3017                         mtd->oobsize = 218;
3018                         break;
3019                 case 3:
3020                         mtd->oobsize = 400;
3021                         break;
3022                 case 4:
3023                         mtd->oobsize = 436;
3024                         break;
3025                 case 5:
3026                         mtd->oobsize = 512;
3027                         break;
3028                 case 6:
3029                 default: /* Other cases are "reserved" (unknown) */
3030                         mtd->oobsize = 640;
3031                         break;
3032                 }
3033                 extid >>= 2;
3034                 /* Calc blocksize */
3035                 mtd->erasesize = (128 * 1024) <<
3036                         (((extid >> 1) & 0x04) | (extid & 0x03));
3037                 *busw = 0;
3038         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3039                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3040                 unsigned int tmp;
3041
3042                 /* Calc pagesize */
3043                 mtd->writesize = 2048 << (extid & 0x03);
3044                 extid >>= 2;
3045                 /* Calc oobsize */
3046                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3047                 case 0:
3048                         mtd->oobsize = 128;
3049                         break;
3050                 case 1:
3051                         mtd->oobsize = 224;
3052                         break;
3053                 case 2:
3054                         mtd->oobsize = 448;
3055                         break;
3056                 case 3:
3057                         mtd->oobsize = 64;
3058                         break;
3059                 case 4:
3060                         mtd->oobsize = 32;
3061                         break;
3062                 case 5:
3063                         mtd->oobsize = 16;
3064                         break;
3065                 default:
3066                         mtd->oobsize = 640;
3067                         break;
3068                 }
3069                 extid >>= 2;
3070                 /* Calc blocksize */
3071                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3072                 if (tmp < 0x03)
3073                         mtd->erasesize = (128 * 1024) << tmp;
3074                 else if (tmp == 0x03)
3075                         mtd->erasesize = 768 * 1024;
3076                 else
3077                         mtd->erasesize = (64 * 1024) << tmp;
3078                 *busw = 0;
3079         } else {
3080                 /* Calc pagesize */
3081                 mtd->writesize = 1024 << (extid & 0x03);
3082                 extid >>= 2;
3083                 /* Calc oobsize */
3084                 mtd->oobsize = (8 << (extid & 0x01)) *
3085                         (mtd->writesize >> 9);
3086                 extid >>= 2;
3087                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3088                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3089                 extid >>= 2;
3090                 /* Get buswidth information */
3091                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3092         }
3093 }
3094
3095 /*
3096  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3097  * decodes a matching ID table entry and assigns the MTD size parameters for
3098  * the chip.
3099  */
3100 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3101                                 struct nand_flash_dev *type, u8 id_data[8],
3102                                 int *busw)
3103 {
3104         int maf_id = id_data[0];
3105
3106         mtd->erasesize = type->erasesize;
3107         mtd->writesize = type->pagesize;
3108         mtd->oobsize = mtd->writesize / 32;
3109         *busw = type->options & NAND_BUSWIDTH_16;
3110
3111         /*
3112          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3113          * some Spansion chips have erasesize that conflicts with size
3114          * listed in nand_ids table.
3115          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3116          */
3117         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3118                         && id_data[6] == 0x00 && id_data[7] == 0x00
3119                         && mtd->writesize == 512) {
3120                 mtd->erasesize = 128 * 1024;
3121                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3122         }
3123 }
3124
3125 /*
3126  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3127  * heuristic patterns using various detected parameters (e.g., manufacturer,
3128  * page size, cell-type information).
3129  */
3130 static void nand_decode_bbm_options(struct mtd_info *mtd,
3131                                     struct nand_chip *chip, u8 id_data[8])
3132 {
3133         int maf_id = id_data[0];
3134
3135         /* Set the bad block position */
3136         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3137                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3138         else
3139                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3140
3141         /*
3142          * Bad block marker is stored in the last page of each block on Samsung
3143          * and Hynix MLC devices; stored in first two pages of each block on
3144          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3145          * AMD/Spansion, and Macronix.  All others scan only the first page.
3146          */
3147         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3148                         (maf_id == NAND_MFR_SAMSUNG ||
3149                          maf_id == NAND_MFR_HYNIX))
3150                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3151         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3152                                 (maf_id == NAND_MFR_SAMSUNG ||
3153                                  maf_id == NAND_MFR_HYNIX ||
3154                                  maf_id == NAND_MFR_TOSHIBA ||
3155                                  maf_id == NAND_MFR_AMD ||
3156                                  maf_id == NAND_MFR_MACRONIX)) ||
3157                         (mtd->writesize == 2048 &&
3158                          maf_id == NAND_MFR_MICRON))
3159                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3160 }
3161
3162 /*
3163  * Get the flash and manufacturer id and lookup if the type is supported.
3164  */
3165 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3166                                                   struct nand_chip *chip,
3167                                                   int busw,
3168                                                   int *maf_id, int *dev_id,
3169                                                   struct nand_flash_dev *type)
3170 {
3171         int i, maf_idx;
3172         u8 id_data[8];
3173
3174         /* Select the device */
3175         chip->select_chip(mtd, 0);
3176
3177         /*
3178          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3179          * after power-up.
3180          */
3181         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3182
3183         /* Send the command for reading device ID */
3184         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3185
3186         /* Read manufacturer and device IDs */
3187         *maf_id = chip->read_byte(mtd);
3188         *dev_id = chip->read_byte(mtd);
3189
3190         /*
3191          * Try again to make sure, as some systems the bus-hold or other
3192          * interface concerns can cause random data which looks like a
3193          * possibly credible NAND flash to appear. If the two results do
3194          * not match, ignore the device completely.
3195          */
3196
3197         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3198
3199         /* Read entire ID string */
3200         for (i = 0; i < 8; i++)
3201                 id_data[i] = chip->read_byte(mtd);
3202
3203         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3204                 pr_info("%s: second ID read did not match "
3205                         "%02x,%02x against %02x,%02x\n", __func__,
3206                         *maf_id, *dev_id, id_data[0], id_data[1]);
3207                 return ERR_PTR(-ENODEV);
3208         }
3209
3210         if (!type)
3211                 type = nand_flash_ids;
3212
3213         for (; type->name != NULL; type++)
3214                 if (*dev_id == type->id)
3215                         break;
3216
3217         chip->onfi_version = 0;
3218         if (!type->name || !type->pagesize) {
3219                 /* Check is chip is ONFI compliant */
3220                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3221                         goto ident_done;
3222         }
3223
3224         if (!type->name)
3225                 return ERR_PTR(-ENODEV);
3226
3227         if (!mtd->name)
3228                 mtd->name = type->name;
3229
3230         chip->chipsize = (uint64_t)type->chipsize << 20;
3231
3232         if (!type->pagesize && chip->init_size) {
3233                 /* Set the pagesize, oobsize, erasesize by the driver */
3234                 busw = chip->init_size(mtd, chip, id_data);
3235         } else if (!type->pagesize) {
3236                 /* Decode parameters from extended ID */
3237                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3238         } else {
3239                 nand_decode_id(mtd, chip, type, id_data, &busw);
3240         }
3241         /* Get chip options */
3242         chip->options |= type->options;
3243
3244         /*
3245          * Check if chip is not a Samsung device. Do not clear the
3246          * options for chips which do not have an extended id.
3247          */
3248         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3249                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3250 ident_done:
3251
3252         /* Try to identify manufacturer */
3253         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3254                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3255                         break;
3256         }
3257
3258         if (chip->options & NAND_BUSWIDTH_AUTO) {
3259                 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3260                 chip->options |= busw;
3261                 nand_set_defaults(chip, busw);
3262         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3263                 /*
3264                  * Check, if buswidth is correct. Hardware drivers should set
3265                  * chip correct!
3266                  */
3267                 pr_info("NAND device: Manufacturer ID:"
3268                         " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3269                         *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3270                 pr_warn("NAND bus width %d instead %d bit\n",
3271                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3272                            busw ? 16 : 8);
3273                 return ERR_PTR(-EINVAL);
3274         }
3275
3276         nand_decode_bbm_options(mtd, chip, id_data);
3277
3278         /* Calculate the address shift from the page size */
3279         chip->page_shift = ffs(mtd->writesize) - 1;
3280         /* Convert chipsize to number of pages per chip -1 */
3281         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3282
3283         chip->bbt_erase_shift = chip->phys_erase_shift =
3284                 ffs(mtd->erasesize) - 1;
3285         if (chip->chipsize & 0xffffffff)
3286                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3287         else {
3288                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3289                 chip->chip_shift += 32 - 1;
3290         }
3291
3292         chip->badblockbits = 8;
3293
3294         /* Check for AND chips with 4 page planes */
3295         if (chip->options & NAND_4PAGE_ARRAY)
3296                 chip->erase_cmd = multi_erase_cmd;
3297         else
3298                 chip->erase_cmd = single_erase_cmd;
3299
3300         /* Do not replace user supplied command function! */
3301         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3302                 chip->cmdfunc = nand_command_lp;
3303
3304         pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3305                 " %dMiB, page size: %d, OOB size: %d\n",
3306                 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3307                 chip->onfi_version ? chip->onfi_params.model : type->name,
3308                 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
3309
3310         return type;
3311 }
3312
3313 /**
3314  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3315  * @mtd: MTD device structure
3316  * @maxchips: number of chips to scan for
3317  * @table: alternative NAND ID table
3318  *
3319  * This is the first phase of the normal nand_scan() function. It reads the
3320  * flash ID and sets up MTD fields accordingly.
3321  *
3322  * The mtd->owner field must be set to the module of the caller.
3323  */
3324 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3325                     struct nand_flash_dev *table)
3326 {
3327         int i, busw, nand_maf_id, nand_dev_id;
3328         struct nand_chip *chip = mtd->priv;
3329         struct nand_flash_dev *type;
3330
3331         /* Get buswidth to select the correct functions */
3332         busw = chip->options & NAND_BUSWIDTH_16;
3333         /* Set the default functions */
3334         nand_set_defaults(chip, busw);
3335
3336         /* Read the flash type */
3337         type = nand_get_flash_type(mtd, chip, busw,
3338                                 &nand_maf_id, &nand_dev_id, table);
3339
3340         if (IS_ERR(type)) {
3341                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3342                         pr_warn("No NAND device found\n");
3343                 chip->select_chip(mtd, -1);
3344                 return PTR_ERR(type);
3345         }
3346
3347         chip->select_chip(mtd, -1);
3348
3349         /* Check for a chip array */
3350         for (i = 1; i < maxchips; i++) {
3351                 chip->select_chip(mtd, i);
3352                 /* See comment in nand_get_flash_type for reset */
3353                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3354                 /* Send the command for reading device ID */
3355                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3356                 /* Read manufacturer and device IDs */
3357                 if (nand_maf_id != chip->read_byte(mtd) ||
3358                     nand_dev_id != chip->read_byte(mtd)) {
3359                         chip->select_chip(mtd, -1);
3360                         break;
3361                 }
3362                 chip->select_chip(mtd, -1);
3363         }
3364         if (i > 1)
3365                 pr_info("%d NAND chips detected\n", i);
3366
3367         /* Store the number of chips and calc total size for mtd */
3368         chip->numchips = i;
3369         mtd->size = i * chip->chipsize;
3370
3371         return 0;
3372 }
3373 EXPORT_SYMBOL(nand_scan_ident);
3374
3375
3376 /**
3377  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3378  * @mtd: MTD device structure
3379  *
3380  * This is the second phase of the normal nand_scan() function. It fills out
3381  * all the uninitialized function pointers with the defaults and scans for a
3382  * bad block table if appropriate.
3383  */
3384 int nand_scan_tail(struct mtd_info *mtd)
3385 {
3386         int i;
3387         struct nand_chip *chip = mtd->priv;
3388
3389         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3390         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3391                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
3392
3393         if (!(chip->options & NAND_OWN_BUFFERS))
3394                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3395         if (!chip->buffers)
3396                 return -ENOMEM;
3397
3398         /* Set the internal oob buffer location, just after the page data */
3399         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3400
3401         /*
3402          * If no default placement scheme is given, select an appropriate one.
3403          */
3404         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3405                 switch (mtd->oobsize) {
3406                 case 8:
3407                         chip->ecc.layout = &nand_oob_8;
3408                         break;
3409                 case 16:
3410                         chip->ecc.layout = &nand_oob_16;
3411                         break;
3412                 case 64:
3413                         chip->ecc.layout = &nand_oob_64;
3414                         break;
3415                 case 128:
3416                         chip->ecc.layout = &nand_oob_128;
3417                         break;
3418                 default:
3419                         pr_warn("No oob scheme defined for oobsize %d\n",
3420                                    mtd->oobsize);
3421                         BUG();
3422                 }
3423         }
3424
3425         if (!chip->write_page)
3426                 chip->write_page = nand_write_page;
3427
3428         /* set for ONFI nand */
3429         if (!chip->onfi_set_features)
3430                 chip->onfi_set_features = nand_onfi_set_features;
3431         if (!chip->onfi_get_features)
3432                 chip->onfi_get_features = nand_onfi_get_features;
3433
3434         /*
3435          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3436          * selected and we have 256 byte pagesize fallback to software ECC
3437          */
3438
3439         switch (chip->ecc.mode) {
3440         case NAND_ECC_HW_OOB_FIRST:
3441                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3442                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3443                      !chip->ecc.hwctl) {
3444                         pr_warn("No ECC functions supplied; "
3445                                    "hardware ECC not possible\n");
3446                         BUG();
3447                 }
3448                 if (!chip->ecc.read_page)
3449                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3450
3451         case NAND_ECC_HW:
3452                 /* Use standard hwecc read page function? */
3453                 if (!chip->ecc.read_page)
3454                         chip->ecc.read_page = nand_read_page_hwecc;
3455                 if (!chip->ecc.write_page)
3456                         chip->ecc.write_page = nand_write_page_hwecc;
3457                 if (!chip->ecc.read_page_raw)
3458                         chip->ecc.read_page_raw = nand_read_page_raw;
3459                 if (!chip->ecc.write_page_raw)
3460                         chip->ecc.write_page_raw = nand_write_page_raw;
3461                 if (!chip->ecc.read_oob)
3462                         chip->ecc.read_oob = nand_read_oob_std;
3463                 if (!chip->ecc.write_oob)
3464                         chip->ecc.write_oob = nand_write_oob_std;
3465
3466         case NAND_ECC_HW_SYNDROME:
3467                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3468                      !chip->ecc.hwctl) &&
3469                     (!chip->ecc.read_page ||
3470                      chip->ecc.read_page == nand_read_page_hwecc ||
3471                      !chip->ecc.write_page ||
3472                      chip->ecc.write_page == nand_write_page_hwecc)) {
3473                         pr_warn("No ECC functions supplied; "
3474                                    "hardware ECC not possible\n");
3475                         BUG();
3476                 }
3477                 /* Use standard syndrome read/write page function? */
3478                 if (!chip->ecc.read_page)
3479                         chip->ecc.read_page = nand_read_page_syndrome;
3480                 if (!chip->ecc.write_page)
3481                         chip->ecc.write_page = nand_write_page_syndrome;
3482                 if (!chip->ecc.read_page_raw)
3483                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3484                 if (!chip->ecc.write_page_raw)
3485                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3486                 if (!chip->ecc.read_oob)
3487                         chip->ecc.read_oob = nand_read_oob_syndrome;
3488                 if (!chip->ecc.write_oob)
3489                         chip->ecc.write_oob = nand_write_oob_syndrome;
3490
3491                 if (mtd->writesize >= chip->ecc.size) {
3492                         if (!chip->ecc.strength) {
3493                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3494                                 BUG();
3495                         }
3496                         break;
3497                 }
3498                 pr_warn("%d byte HW ECC not possible on "
3499                            "%d byte page size, fallback to SW ECC\n",
3500                            chip->ecc.size, mtd->writesize);
3501                 chip->ecc.mode = NAND_ECC_SOFT;
3502
3503         case NAND_ECC_SOFT:
3504                 chip->ecc.calculate = nand_calculate_ecc;
3505                 chip->ecc.correct = nand_correct_data;
3506                 chip->ecc.read_page = nand_read_page_swecc;
3507                 chip->ecc.read_subpage = nand_read_subpage;
3508                 chip->ecc.write_page = nand_write_page_swecc;
3509                 chip->ecc.read_page_raw = nand_read_page_raw;
3510                 chip->ecc.write_page_raw = nand_write_page_raw;
3511                 chip->ecc.read_oob = nand_read_oob_std;
3512                 chip->ecc.write_oob = nand_write_oob_std;
3513                 if (!chip->ecc.size)
3514                         chip->ecc.size = 256;
3515                 chip->ecc.bytes = 3;
3516                 chip->ecc.strength = 1;
3517                 break;
3518
3519         case NAND_ECC_SOFT_BCH:
3520                 if (!mtd_nand_has_bch()) {
3521                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3522                         BUG();
3523                 }
3524                 chip->ecc.calculate = nand_bch_calculate_ecc;
3525                 chip->ecc.correct = nand_bch_correct_data;
3526                 chip->ecc.read_page = nand_read_page_swecc;
3527                 chip->ecc.read_subpage = nand_read_subpage;
3528                 chip->ecc.write_page = nand_write_page_swecc;
3529                 chip->ecc.read_page_raw = nand_read_page_raw;
3530                 chip->ecc.write_page_raw = nand_write_page_raw;
3531                 chip->ecc.read_oob = nand_read_oob_std;
3532                 chip->ecc.write_oob = nand_write_oob_std;
3533                 /*
3534                  * Board driver should supply ecc.size and ecc.bytes values to
3535                  * select how many bits are correctable; see nand_bch_init()
3536                  * for details. Otherwise, default to 4 bits for large page
3537                  * devices.
3538                  */
3539                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3540                         chip->ecc.size = 512;
3541                         chip->ecc.bytes = 7;
3542                 }
3543                 chip->ecc.priv = nand_bch_init(mtd,
3544                                                chip->ecc.size,
3545                                                chip->ecc.bytes,
3546                                                &chip->ecc.layout);
3547                 if (!chip->ecc.priv) {
3548                         pr_warn("BCH ECC initialization failed!\n");
3549                         BUG();
3550                 }
3551                 chip->ecc.strength =
3552                         chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3553                 break;
3554
3555         case NAND_ECC_NONE:
3556                 pr_warn("NAND_ECC_NONE selected by board driver. "
3557                            "This is not recommended!\n");
3558                 chip->ecc.read_page = nand_read_page_raw;
3559                 chip->ecc.write_page = nand_write_page_raw;
3560                 chip->ecc.read_oob = nand_read_oob_std;
3561                 chip->ecc.read_page_raw = nand_read_page_raw;
3562                 chip->ecc.write_page_raw = nand_write_page_raw;
3563                 chip->ecc.write_oob = nand_write_oob_std;
3564                 chip->ecc.size = mtd->writesize;
3565                 chip->ecc.bytes = 0;
3566                 chip->ecc.strength = 0;
3567                 break;
3568
3569         default:
3570                 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3571                 BUG();
3572         }
3573
3574         /* For many systems, the standard OOB write also works for raw */
3575         if (!chip->ecc.read_oob_raw)
3576                 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3577         if (!chip->ecc.write_oob_raw)
3578                 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3579
3580         /*
3581          * The number of bytes available for a client to place data into
3582          * the out of band area.
3583          */
3584         chip->ecc.layout->oobavail = 0;
3585         for (i = 0; chip->ecc.layout->oobfree[i].length
3586                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3587                 chip->ecc.layout->oobavail +=
3588                         chip->ecc.layout->oobfree[i].length;
3589         mtd->oobavail = chip->ecc.layout->oobavail;
3590
3591         /*
3592          * Set the number of read / write steps for one page depending on ECC
3593          * mode.
3594          */
3595         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3596         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3597                 pr_warn("Invalid ECC parameters\n");
3598                 BUG();
3599         }
3600         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3601
3602         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3603         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3604             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3605                 switch (chip->ecc.steps) {
3606                 case 2:
3607                         mtd->subpage_sft = 1;
3608                         break;
3609                 case 4:
3610                 case 8:
3611                 case 16:
3612                         mtd->subpage_sft = 2;
3613                         break;
3614                 }
3615         }
3616         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3617
3618         /* Initialize state */
3619         chip->state = FL_READY;
3620
3621         /* Invalidate the pagebuffer reference */
3622         chip->pagebuf = -1;
3623
3624         /* Large page NAND with SOFT_ECC should support subpage reads */
3625         if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3626                 chip->options |= NAND_SUBPAGE_READ;
3627
3628         /* Fill in remaining MTD driver data */
3629         mtd->type = MTD_NANDFLASH;
3630         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3631                                                 MTD_CAP_NANDFLASH;
3632         mtd->_erase = nand_erase;
3633         mtd->_point = NULL;
3634         mtd->_unpoint = NULL;
3635         mtd->_read = nand_read;
3636         mtd->_write = nand_write;
3637         mtd->_panic_write = panic_nand_write;
3638         mtd->_read_oob = nand_read_oob;
3639         mtd->_write_oob = nand_write_oob;
3640         mtd->_sync = nand_sync;
3641         mtd->_lock = NULL;
3642         mtd->_unlock = NULL;
3643         mtd->_suspend = nand_suspend;
3644         mtd->_resume = nand_resume;
3645         mtd->_block_isbad = nand_block_isbad;
3646         mtd->_block_markbad = nand_block_markbad;
3647         mtd->writebufsize = mtd->writesize;
3648
3649         /* propagate ecc info to mtd_info */
3650         mtd->ecclayout = chip->ecc.layout;
3651         mtd->ecc_strength = chip->ecc.strength;
3652         /*
3653          * Initialize bitflip_threshold to its default prior scan_bbt() call.
3654          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3655          * properly set.
3656          */
3657         if (!mtd->bitflip_threshold)
3658                 mtd->bitflip_threshold = mtd->ecc_strength;
3659
3660         /* Check, if we should skip the bad block table scan */
3661         if (chip->options & NAND_SKIP_BBTSCAN)
3662                 return 0;
3663
3664         /* Build bad block table */
3665         return chip->scan_bbt(mtd);
3666 }
3667 EXPORT_SYMBOL(nand_scan_tail);
3668
3669 /*
3670  * is_module_text_address() isn't exported, and it's mostly a pointless
3671  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3672  * to call us from in-kernel code if the core NAND support is modular.
3673  */
3674 #ifdef MODULE
3675 #define caller_is_module() (1)
3676 #else
3677 #define caller_is_module() \
3678         is_module_text_address((unsigned long)__builtin_return_address(0))
3679 #endif
3680
3681 /**
3682  * nand_scan - [NAND Interface] Scan for the NAND device
3683  * @mtd: MTD device structure
3684  * @maxchips: number of chips to scan for
3685  *
3686  * This fills out all the uninitialized function pointers with the defaults.
3687  * The flash ID is read and the mtd/chip structures are filled with the
3688  * appropriate values. The mtd->owner field must be set to the module of the
3689  * caller.
3690  */
3691 int nand_scan(struct mtd_info *mtd, int maxchips)
3692 {
3693         int ret;
3694
3695         /* Many callers got this wrong, so check for it for a while... */
3696         if (!mtd->owner && caller_is_module()) {
3697                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3698                 BUG();
3699         }
3700
3701         ret = nand_scan_ident(mtd, maxchips, NULL);
3702         if (!ret)
3703                 ret = nand_scan_tail(mtd);
3704         return ret;
3705 }
3706 EXPORT_SYMBOL(nand_scan);
3707
3708 /**
3709  * nand_release - [NAND Interface] Free resources held by the NAND device
3710  * @mtd: MTD device structure
3711  */
3712 void nand_release(struct mtd_info *mtd)
3713 {
3714         struct nand_chip *chip = mtd->priv;
3715
3716         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3717                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3718
3719         mtd_device_unregister(mtd);
3720
3721         /* Free bad block table memory */
3722         kfree(chip->bbt);
3723         if (!(chip->options & NAND_OWN_BUFFERS))
3724                 kfree(chip->buffers);
3725
3726         /* Free bad block descriptor memory */
3727         if (chip->badblock_pattern && chip->badblock_pattern->options
3728                         & NAND_BBT_DYNAMICSTRUCT)
3729                 kfree(chip->badblock_pattern);
3730 }
3731 EXPORT_SYMBOL_GPL(nand_release);
3732
3733 static int __init nand_base_init(void)
3734 {
3735         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3736         return 0;
3737 }
3738
3739 static void __exit nand_base_exit(void)
3740 {
3741         led_trigger_unregister_simple(nand_led_trigger);
3742 }
3743
3744 module_init(nand_base_init);
3745 module_exit(nand_base_exit);
3746
3747 MODULE_LICENSE("GPL");
3748 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3749 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3750 MODULE_DESCRIPTION("Generic NAND flash driver code");