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12 >ARM/StrongARM(SA11X0) Bright Star Engineering commEngine and nanoEngine</TITLE
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49 >eCos Reference Manual</TH
65 >Chapter 5. Installation and Testing</TD
85 NAME="NANO">ARM/StrongARM(SA11X0) Bright Star Engineering commEngine and nanoEngine</H1
91 NAME="AEN5802">Overview</H2
93 >RedBoot supports a serial port and the built in ethernet port
94 for communication and downloads. The default serial port settings are 38400,8,N,1.
95 RedBoot runs from and supports flash management for the system flash
98 >The following RedBoot configurations are supported:
101 CLASS="INFORMALTABLE"
141 >RedBoot running from the first free flash block
160 >RedBoot running from RAM with RedBoot in the
161 flash boot sector.</TD
179 NAME="AEN5837">Initial Installation</H2
181 >Unlike other targets, the nanoEngine comes equipped with boot firmware
182 which you cannot modify. See chapter 5, "nanoEngine Firmware" of the <I
184 >nanoEngine Hardware Reference Manual</I
185 > (we refer to "July 17, 2000
186 Rev 0.6") from Bright Star Engineering. </P
188 >Because of this, eCos, and therefore Redboot, only supports a
189 special configuration of the ROM mode, starting at offset 0x40000 in
192 >Briefly, the POST-configuration RedBoot image lives in flash following the
193 BSE firmware. The BSE firmware is configured, using its standard <B
196 > command, to run RedBoot at startup.</P
203 NAME="AEN5844">Download Instructions</H2
205 >You can perform the initial load of the POST-configuration RedBoot image into
206 flash using the BSE firmware's <B
210 This will load a binary file, using TFTP, and program it into flash in one
211 operation. Because no memory management is used in the BSE firmware, flash
212 is mapped from address zero upwards, so the address for the RedBoot POST image
213 is 0x40000. You must use the binary version of RedBoot for this,
216 >redboot-post.bin</TT
219 >This assumes you have set up the other BSE firmware config
220 parameters such that it can communicate over your network to your TFTP
233 >load redboot-post.bin 40000</B
236 loading ... erasing blk at 00040000
237 erasing blk at 00050000
238 94168 bytes loaded cksum 00008579
244 >set bootcmd "go 40000"</B
254 netmask = 255.255.255.0
256 gateway = 10.16.19.66
257 serverip = 10.16.19.66
272 >the BSE firmware runs its serial IO at 9600 Baud; RedBoot runs instead
273 at 38400 Baud. You must select the right baud rate in your terminal program
274 to be able to set up the BSE firmware.</P
279 After a reset, the BSE firmware will print
289 >Boot: BSE 2000 Sep 12 2000 14:00:30
290 autoboot: "go 40000" [hit ESC to abort]</PRE
296 and then RedBoot starts, switching to 38400 Baud.</P
298 >Once you have installed a bootable RedBoot in the system in this
299 manner, we advise re-installing using the generic method described in
301 HREF="updating-redboot.html"
303 > in order that the Flash Image System
304 contains an appropriate description of the flash entries.</P
311 NAME="AEN5860">Cohabiting with POST in Flash</H2
313 >The configuration file named <TT
315 >redboot_POST.ecm</TT
317 configures RedBoot to build for execution at address 0x50040000 (or, during
318 bootup, 0x00040000). This is to allow power-on self-test (POST) code or immutable
319 firmware to live in the lower addresses of the flash and to run before RedBoot
320 gets control. The assumption is that RedBoot will be entered at its base address
321 in physical memory, that is 0x00040000.</P
323 >Alternatively, for testing, you can call it in an already running system
329 > at another RedBoot prompt, or
330 a branch to that address. The address is where the reset vector
331 points. It is reported by RedBoot's <B
339 > command, amongst other
342 >Using the POST configuration enables a normal config option which causes
343 linking and initialization against memory layout files called "...post..."
344 rather than "...rom..." or "...ram..." in the <TT
347 > directory. Specifically:<P
348 CLASS="LITERALLAYOUT"
351 >include/pkgconf/mlt_arm_sa11x0_nano_post.h</TT
355 >include/pkgconf/mlt_arm_sa11x0_nano_post.ldi</TT
359 >include/pkgconf/mlt_arm_sa11x0_nano_post.mlt</TT
363 It is these you should edit if you wish to move the execution address
364 from 0x50040000 in the POST configuration. Startup mode naturally
365 remains ROM in this configuration.</P
367 >Because the nanoEngine contains immutable boot firmware at the start
368 of flash, RedBoot for this target is configured to reserve that area in the
369 Flash Image System, and to create by default an entry for the POST
385 Name FLASH addr Mem addr Length Entry point
386 (reserved) 0x50000000 0x50000000 0x00040000 0x00000000
387 RedBoot[post] 0x50040000 0x00100000 0x00020000 0x50040040
388 RedBoot config 0x503E0000 0x503E0000 0x00010000 0x00000000
389 FIS directory 0x503F0000 0x503F0000 0x00010000 0x00000000
395 The entry "(reserved)" ensures that the FIS cannot attempt
396 to overwrite the BSE firmware, thus ensuring that the board remains bootable
397 and recoverable even after installing a broken RedBoot image.</P
404 NAME="AEN5877">Special RedBoot Commands</H2
406 >The nanoEngine/commEngine has one or two Intel i82559 Ethernet controllers
407 installed, but these have no associated serial EEPROM in which to record their
408 Ethernet Station Address (ESA, or MAC address). The BSE firmware records an
409 ESA for the device it uses, but this information is not available to RedBoot;
410 we cannot share it.</P
412 >To keep the ESAs for the two ethernet interfaces, two new items of RedBoot
413 configuration data are introduced. You can list them with the RedBoot command <B
431 Run script at boot: false
432 Use BOOTP for network configuration: false
433 Local IP address: 10.16.19.91
434 Default server IP address: 10.16.19.66
435 Network hardware address [MAC] for eth0: 0x00:0xB5:0xE0:0xB5:0xE0:0x99
436 Network hardware address [MAC] for eth1: 0x00:0xB5:0xE0:0xB5:0xE0:0x9A
437 GDB connection port: 9000
438 Network debug at boot time: false
445 You should set them before running RedBoot or eCos applications with
446 the board connected to a network. The <B
450 command can be used as for any configuration data item; the entire ESA
451 is entered in one line.</P
458 NAME="AEN5885">Memory Maps</H2
460 >The first level page table is located at physical address 0xc0004000.
461 No second level tables are used. <DIV
468 >The virtual memory maps in this section use a C and B column to indicate
469 whether or not the region is cached (C) or buffered (B).</P
479 CLASS="PROGRAMLISTING"
480 >Physical Address Range Description
481 ----------------------- ----------------------------------
482 0x00000000 - 0x003fffff 4Mb FLASH (nCS0)
483 0x18000000 - 0x18ffffff Internal PCI bus - 2 x i82559 ethernet
484 0x40000000 - 0x4fffffff External IO or PCI bus
485 0x80000000 - 0xbfffffff SA-1110 Internal Registers
486 0xc0000000 - 0xc7ffffff DRAM Bank 0 - 32Mb SDRAM
487 0xc8000000 - 0xcfffffff DRAM Bank 1 - empty
488 0xe0000000 - 0xe7ffffff Cache Clean
490 Virtual Address Range C B Description
491 ----------------------- - - ----------------------------------
492 0x00000000 - 0x001fffff Y Y DRAM - 8Mb to 32Mb
493 0x18000000 - 0x180fffff N N Internal PCI bus - 2 x i82559 ethernet
494 0x40000000 - 0x4fffffff N N External IO or PCI bus
495 0x50000000 - 0x51ffffff Y Y Up to 32Mb FLASH (nCS0)
496 0x80000000 - 0xbfffffff N N SA-1110 Internal Registers
497 0xc0000000 - 0xc0ffffff N Y DRAM Bank 0: 8 or 16Mb
498 0xc8000000 - 0xc8ffffff N Y DRAM Bank 1: 8 or 16Mb or absent
499 0xe0000000 - 0xe7ffffff Y Y Cache Clean</PRE
505 >The ethernet devices use a "PCI window" to communicate with the CPU.
506 This is 1Mb of SDRAM which is shared with the ethernet devices that are on
507 the PCI bus. It is neither cached nor buffered, to ensure that CPU and PCI
508 accesses see correct data in the correct order. By default it is configured
509 to be megabyte number 30, at addresses 0x01e00000-0x01efffff. This can be
510 modified, and indeed must be, if less than 32Mb of SDRAM is installed, via
511 the memory layout tool, or by moving the section <TT
512 CLASS="COMPUTEROUTPUT"
514 > referred to by symbols <TT
515 CLASS="COMPUTEROUTPUT"
516 >CYGMEM_SECTION_pci_window*</TT
517 > in the linker script. </P
519 >Though the nanoEngine ships with 32Mb of SDRAM all attached to DRAM
520 bank 0, the code can cope with any of these combinations also; "2 x " in this
521 context means one device in each DRAM Bank. <P
522 CLASS="LITERALLAYOUT"
523 >1 x 8Mb = 8Mb 2 x 8Mb = 16Mb<br>
524 1 x 16Mb = 16Mb 2 x 16Mb = 32Mb</P
525 >All are programmed the same
526 in the memory controller. </P
528 >Startup code detects which is fitted and programs the memory map accordingly.
529 If the device(s) is 8Mb, then there are gaps in the physical memory map, because
530 a high order address bit is not connected. The gaps are the higher 2Mb out
533 > The SA11x0 OS timer is used as a polled timer to provide timeout
534 support within RedBoot.</P
541 NAME="AEN5899">Nano Platform Port</H2
543 >The nano is in the set of SA11X0-based platforms. It uses the arm architectural
544 HAL, the sa11x0 variant HAL, plus the nano platform hal. These are components
546 CLASS="LITERALLAYOUT"
547 >CYGPKG_HAL_ARM hal/arm/arch/<br>
548 CYGPKG_HAL_ARM_SA11X0 hal/arm/sa11x0/var<br>
549 CYGPKG_HAL_ARM_SA11X0_NANO hal/arm/sa11x0/nano</P
553 >The target name is "nano" which includes all these, plus the ethernet
554 driver packages, flash driver, and so on.</P
561 NAME="AEN5904">Ethernet Driver</H2
563 >The ethernet driver is in two parts: </P
565 >A generic ether driver for Intel i8255x series devices, specifically
567 CLASS="COMPUTEROUTPUT"
568 >devs/eth/intel/i82559</TT
571 CLASS="COMPUTEROUTPUT"
572 >CYGPKG_DEVS_ETH_INTEL_I82559</TT
576 >The platform-specific ether driver is <TT
577 CLASS="COMPUTEROUTPUT"
578 >devs/eth/arm/nano</TT
579 >. Its package is <TT
580 CLASS="COMPUTEROUTPUT"
581 >CYGPKG_DEVS_ETH_ARM_NANO</TT
582 >. This tells the generic driver the address in IO memory
583 of the chip, for example, and other configuration details. This driver picks
584 up the ESA from RedBoot's configuration data - unless configured to use a
585 static ESA in the usual manner. </P
592 NAME="AEN5913">Rebuilding RedBoot</H2
594 >These shell variables provide the platform-specific information
595 needed for building RedBoot according to the procedure described in
597 HREF="rebuilding-redboot.html"
607 CLASS="PROGRAMLISTING"
610 export PLATFORM_DIR=sa11x0/nano</PRE
616 >The names of configuration files are listed above with the
617 description of the associated modes.</P
625 SUMMARY="Footer navigation table"
664 >ARM/StrongARM(SA1110) Intel SA1110 (Assabet)</TD
670 HREF="installation-and-testing.html"
678 >ARM/StrongARM(SA11X0) Compaq iPAQ PocketPC</TD
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