1 //==========================================================================
5 // Driver for LXT970 PHY
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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30 // License. However the source code for this file must still be made available
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34 // this file might be covered by the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: gthomas, jskov
45 // Grant Edwards <grante@visi.com>
50 //####DESCRIPTIONEND####
52 //========================================================================*/
57 // address of the LX970 phy
58 #ifdef CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
59 #define LX970_ADDR CYGPKG_DEVS_ETH_ARM_KS32C5000_PHYADDR
64 // LX970 register offsets
65 #define LX970_CNTL_REG 0x00
66 #define LX970_STATUS_REG 0x01
67 #define LX970_ID_REG1 0x02
68 #define LX970_ID_REG2 0x03
69 #define LX970_ANA_REG 0x04
70 #define LX970_ANLPAR_REG 0x05
71 #define LX970_ANE_REG 0x06
72 #define LX970_MIRROR_REG 0x10
73 #define LX970_INTEN_REG 0x11
74 #define LX970_INTSTAT_REG 0x12
75 #define LX970_CONFIG_REG 0x13
76 #define LX970_CHIPSTAT_REG 0x14
78 // LX970 Control register bit defines
79 #define LX970_CNTL_RESET 0x8000
80 #define LX970_CNTL_LOOPBACK 0x4000
81 #define LX970_CNTL_SPEED 0x2000 // 1=100Meg, 0=10Meg
82 #define LX970_CNTL_AN 0x1000 // 1=Enable auto negotiation, 0=disable it
83 #define LX970_CNTL_PWRDN 0x0800 // 1=Enable power down
84 #define LX970_CNTL_ISOLATE 0x0400 // 1=Isolate from MII
85 #define LX970_CNTL_RSTRT_AN 0x0200 // 1=Restart Auto Negotioation process
86 #define LX970_CNTL_FULL_DUP 0x0100 // 1=Enable full duplex mode, 0=half dup
87 #define LX970_CNTL_TST_COLL 0x0080 // 1=Enable collision test
89 #define Bit(n) (1<<(n))
91 #define LX970_ANA_PAUSE_ENA Bit(10)
92 #define LX970_ANA_100T4 Bit(9)
93 #define LX970_ANA_100TX_FULL Bit(8)
94 #define LX970_ANA_100TX Bit(7)
95 #define LX970_ANA_10T_FULL Bit(6)
96 #define LX970_ANA_10T Bit(5)
97 #define LX970_ANA_SEL_802_3 Bit(0)
99 #define LX970_CHIPSTAT_LINKUP Bit(13)
100 #define LX970_CHIPSTAT_FULLDUP Bit(12)
101 #define LX970_CHIPSTAT_100M Bit(11)
102 #define LX970_CHIPSTAT_ANEG_DONE Bit(9)
103 #define LX970_CHIPSTAT_PAGE_RX Bit(8)
104 #define LX970_CHIPSTAT_LOWVOLT Bit(2)
106 // phy functions for Level1 PHY LXT970
110 // first software reset the LX970
111 MiiStationWrite(LX970_CNTL_REG, LX970_ADDR, LX970_CNTL_RESET);
112 MiiStationWrite(LX970_CNTL_REG, LX970_ADDR, 0);
114 // set low level drive for MII lines, enable interrupt output
115 MiiStationWrite(17, LX970_ADDR, BIT3+BIT1);
117 // default values for 100M encryption are wrong, so fix them
118 // and configure LEDC to be activity indicator
119 MiiStationWrite(19, LX970_ADDR, BIT7);
121 // initialize auto-negotiation capabilities
122 MiiStationWrite(LX970_ANA_REG,LX970_ADDR,
125 LX970_ANA_100TX_FULL+
129 LX970_ANA_SEL_802_3);
131 // Now start an auto negotiation
132 MiiStationWrite(LX970_CNTL_REG, LX970_ADDR,
134 LX970_CNTL_RSTRT_AN);
136 // force to 10M full duplex
137 MiiStationWrite(LX970_CNTL_REG, LX970_ADDR,
138 LX970_CNTL_FULL_DUP);
142 unsigned PhyStatus(void)
144 unsigned lxt970Status = MiiStationRead(LX970_CHIPSTAT_REG,LX970_ADDR);
146 if (lxt970Status & LX970_CHIPSTAT_LINKUP)
147 r |= PhyStatus_LinkUp;
148 if (lxt970Status & LX970_CHIPSTAT_FULLDUP)
149 r |= PhyStatus_FullDuplex;
150 if (lxt970Status & LX970_CHIPSTAT_100M)
151 r |= PhyStatus_100Mb;
155 void PhyInterruptAck(void)
157 MiiStationRead(1,LX970_ADDR);
158 MiiStationRead(18,LX970_ADDR);