1 //==========================================================================
5 // Fast ethernet device driver for PowerPC MPC8260 boards
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //==========================================================================
42 //#####DESCRIPTIONBEGIN####
45 // Contributors: pfine
48 // Description: hardware driver for MPC8260 FEC
51 //####DESCRIPTIONEND####
53 //==========================================================================
55 #include <pkgconf/devs_eth_powerpc_quicc2.h>
56 #include <cyg/infra/cyg_type.h>
57 #include <cyg/infra/diag.h>
59 #include <cyg/hal/hal_arch.h>
60 #include <cyg/hal/hal_cache.h>
61 #include <cyg/hal/hal_intr.h>
62 #include <cyg/hal/var_intr.h>
63 #include <cyg/hal/drv_api.h>
64 #include <cyg/hal/hal_if.h>
65 #include <cyg/hal/mpc8260.h>
67 #include <cyg/io/eth/netdev.h>
68 #include <cyg/io/eth/eth_drv.h>
71 #include <pkgconf/net.h>
77 #define ALIGN_TO_CACHE_LINES(x) ( (long)((x) + 31) & 0xffffffe0 )
79 static unsigned char fec_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM *
80 (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)];
81 static unsigned char fec_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM *
82 (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)];
84 // Buffer descriptors are in dual ported RAM, which is marked non-cached
85 #define FEC_BDs_NONCACHED
86 static struct fec_bd *const fec_eth_rxring = (struct fec_bd *)
87 (QUICC2_VADS_IMM_BASE + FEC_PRAM_RxBD_Base);
88 static struct fec_bd *const fec_eth_txring = (struct fec_bd *)
89 (QUICC2_VADS_IMM_BASE + FEC_PRAM_TxBD_Base);
91 static struct fec_eth_info fec_eth0_info;
93 static unsigned short _default_enaddr[] = {0x1234, 0x5678, 0x90a1};
94 static unsigned char enaddr[6];
97 #include <pkgconf/redboot.h>
98 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
100 #include <flash_config.h>
101 RedBoot_config_option("Network hardware address [MAC]",
103 ALWAYS_ENABLED, true,
106 RedBoot_config_option("Attempt to find 100 Mbps Ethernet",
108 ALWAYS_ENABLED, true,
114 #define os_printf diag_printf
116 // CONFIG_ESA and CONFIG_BOOL are defined in redboot/include/flash_config.h
118 #define CONFIG_ESA 6 // ethernet address length ...
122 #define CONFIG_BOOL 1
125 ETH_DRV_SC(fec_eth0_sc,
126 &fec_eth0_info, // Driver specific data
127 "eth0", // Name for this interface
138 NETDEVTAB_ENTRY(fec_netdev,
144 static cyg_interrupt fec_eth_interrupt;
145 static cyg_handle_t fec_eth_interrupt_handle;
147 static void fec_eth_int(struct eth_drv_sc *data);
149 #define FEC_ETH_INT CYGNUM_HAL_INTERRUPT_FCC2
151 // This ISR is called when the ethernet interrupt occurs
154 fec_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
156 cyg_drv_interrupt_mask(FEC_ETH_INT);
157 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
161 // Deliver function (ex-DSR) handles the ethernet [logical] processing
163 fec_eth_deliver(struct eth_drv_sc * sc)
167 // Clearing the event register acknowledges FCC2 interrupt ...
168 // cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
169 cyg_drv_interrupt_unmask(FEC_ETH_INT);
175 // Initialize the interface - performed at system startup
176 // This function must set up the interface, including arranging to
177 // handle interrupts, etc, so that it may be "started" cheaply later.
179 fec_eth_init(struct cyg_netdevtab_entry *tab)
181 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
182 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
184 volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
185 volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET);
186 volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e);
187 #if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
188 volatile t_BCSR *CSR = (t_BCSR *) 0x04500000;
194 unsigned char *c_ptr;
197 // Link the memory to the driver control memory
198 qi->fcc_reg = & (IMM->fcc_regs[FCC2]);
200 // just in case : disable Transmit and Receive
201 qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
203 // Via BCSR, (re)start LXT970
204 #if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
208 // Try to read the ethernet address of the transciever ...
209 #ifdef CYGPKG_REDBOOT
210 esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL);
212 esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
213 "fec_100", &fec_100, CONFIG_BOOL);
216 link_speed = NOTLINKED;
217 if(esa_ok && fec_100){
218 // Via MII Management pins, tell LXT970 to initialize
219 os_printf("Attempting to acquire 100 Mbps half_duplex link ...");
220 InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
221 (VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
224 link_speed = LinkTestPHY();
226 if(link_speed == NOTLINKED){
227 os_printf("Failed to get 100 Mbps half_duplex link.\n");
230 if(link_speed == NOTLINKED){
231 os_printf("Attempting to acquire 10 Mbps half_duplex link ...");
232 InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
233 (VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
235 link_speed = LinkTestPHY();
237 if(link_speed == NOTLINKED){
238 link_speed = LinkTestPHY();
239 os_printf("Failed to get 10 Mbps half_duplex link.\n");
243 switch ( link_speed ) {
246 os_printf("100 MB full-duplex ethernet link \n");
249 os_printf("100 MB half-duplex ethernet link \n");
252 os_printf("10 MB full-duplex ethernet link \n");
255 os_printf("10 MB half-duplex ethernet link \n");
258 os_printf("NO ethernet link \n");
261 // Connect PORTC pins: (C19) to clk13, (C18) to clk 14
262 IMM->io_regs[PORT_C].ppar |= 0x00003000;
263 IMM->io_regs[PORT_C].podr &= ~(0x00003000);
264 IMM->io_regs[PORT_C].psor &= ~(0x00003000);
265 IMM->io_regs[PORT_C].pdir &= ~(0x00003000);
267 // Connect clk13 to RxClk and clk14 to TxClk on FCC2
268 IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks
269 IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks (see 15-14)
270 IMM->cpm_mux_cmxuar = 0x0000; // Utopia address reg, just clear
272 // Initialize parallel port registers to connect FCC2 to MII
273 IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31
274 IMM->io_regs[PORT_B].psor &= 0xffffc000;
275 IMM->io_regs[PORT_B].pdir &= 0xffffc000;
277 IMM->io_regs[PORT_B].psor |= 0x00000004;
278 IMM->io_regs[PORT_B].pdir |= 0x000003c5;
279 IMM->io_regs[PORT_B].ppar |= 0x00003fff;
281 // Initialize Receive Buffer Descriptors
282 qi->rbase = fec_eth_rxring;
283 qi->rxbd = fec_eth_rxring;
284 qi->rnext = fec_eth_rxring;
285 c_ptr = fec_eth_rxbufs;
287 for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) {
289 fec_eth_rxring[i].ctrl = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int);
290 fec_eth_rxring[i].length = 0; // reset
291 c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
292 fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr;
293 c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
296 fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap;
298 // Initialize Transmit Buffer Descriptors
299 qi->tbase = fec_eth_txring;
300 qi->txbd = fec_eth_txring;
301 qi->tnext = fec_eth_txring;
302 c_ptr = fec_eth_txbufs;
304 for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) {
306 fec_eth_txring[i].ctrl = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int);
307 fec_eth_txring[i].length = 0; // reset : Write before send
308 c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
309 fec_eth_txring[i].buffer = (volatile unsigned char *)c_ptr;
310 c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
313 fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap;
315 // Common FCC Parameter RAM initialization
316 fcc->riptr = FEC_PRAM_RIPTR; // in dual port RAM (see 28-11)
317 fcc->tiptr = FEC_PRAM_TIPTR; // in dual port RAM (see 28-11)
318 fcc->mrblr = FEC_PRAM_MRBLR; // ?? FROM 8101 code ...
319 fcc->rstate &= FEC_FCR_INIT;
320 fcc->rstate |= FEC_FCR_MOT_BO;
321 fcc->rbase = (long) fec_eth_rxring;
322 fcc->tstate &= FEC_FCR_INIT;
323 fcc->tstate |= FEC_FCR_MOT_BO;
324 fcc->tbase = (long) fec_eth_txring;
326 // Ethernet Specific FCC Parameter RAM Initialization
327 E_fcc->c_mask = FEC_PRAM_C_MASK; // (see 30-9)
328 E_fcc->c_pres = FEC_PRAM_C_PRES;
332 E_fcc->ret_lim = FEC_PRAM_RETLIM;
333 E_fcc->p_per = FEC_PRAM_PER_LO;
337 E_fcc->mflr = FEC_MAX_FLR;
339 // Try to read the ethernet address of the transciever ...
340 #ifdef CYGPKG_REDBOOT
341 esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
343 esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
344 "fec_esa", enaddr, CONFIG_ESA);
347 // If can't use the default ...
348 os_printf("FEC_ETH - Warning! ESA unknown\n");
349 memcpy(enaddr, _default_enaddr, sizeof(enaddr));
352 E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2];
353 E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1];
354 E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0];
358 E_fcc->minflr = FEC_MIN_FLR;
362 E_fcc->pad_ptr = FEC_PRAM_TIPTR; // No special padding char ...
364 E_fcc->maxd1 = FEC_PRAM_MAXD;
365 E_fcc->maxd2 = FEC_PRAM_MAXD;
367 // FCC register initialization
368 IMM->fcc_regs[FCC2].fcc_gfmr = FEC_GFMR_INIT;
369 IMM->fcc_regs[FCC2].fcc_psmr = FEC_PSMR_INIT;
370 IMM->fcc_regs[FCC2].fcc_dsr = FEC_DSR_INIT;
373 // clear the events of FCC2
374 IMM->fcc_regs[FCC2].fcc_fcce = 0xFFFF0000;
375 IMM->fcc_regs[FCC2].fcc_fccm = FEC_EV_TXE | FEC_EV_TXB | FEC_EV_RXF;
377 // Set up to handle interrupts
378 cyg_drv_interrupt_create(FEC_ETH_INT,
379 0, // Highest //CYGARC_SIU_PRIORITY_HIGH,
380 (cyg_addrword_t)sc, // Data passed to ISR
381 (cyg_ISR_t *)fec_eth_isr,
382 (cyg_DSR_t *)eth_drv_dsr,
383 &fec_eth_interrupt_handle,
385 cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
386 cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
387 cyg_drv_interrupt_unmask(FEC_ETH_INT);
390 // Mask the interrupts
391 IMM->fcc_regs[FCC2].fcc_fccm = 0;
394 // Issue Init RX & TX Parameters Command for FCC2
395 while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
397 IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS |
400 CPCR_FLG; /* ISSUE COMMAND */
402 while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD);
404 // Initialize upper level driver for ecos
405 (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
411 // This function is called to "start up" the interface. It may be called
412 // multiple times, even when the hardware is already running. It will be
413 // called whenever something "hardware oriented" changes and should leave
414 // the hardware ready to send/receive packets.
417 fec_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
419 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
421 // Enable the device :
422 // Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive
423 qi->fcc_reg->fcc_gfmr |= (FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
428 // This function is called to shut down the interface.
431 fec_eth_stop(struct eth_drv_sc *sc)
433 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
435 // Disable the device :
436 // Clear the ENT/ENR bits in the GFMR -- Disable Transmit/Receive
437 qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
442 // This function is called for low level "control" operations
445 fec_eth_control(struct eth_drv_sc *sc, unsigned long key,
446 void *data, int length)
449 case ETH_DRV_SET_MAC_ADDRESS:
460 // This function is called to see if another packet can be sent.
461 // It should return the number of packets which can be handled.
462 // Zero should be returned if the interface is busy and can not send any more.
465 fec_eth_can_send(struct eth_drv_sc *sc)
467 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
468 volatile struct fec_bd *txbd = qi->txbd;
471 HAL_DCACHE_IS_ENABLED(cache_state);
472 #ifndef FEC_BDs_NONCACHED
474 HAL_DCACHE_INVALIDATE(fec_eth_txring,
475 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
479 return ((txbd->ctrl & (FCC_BD_Tx_TC | FCC_BD_Tx_Ready)) == 0);
483 // This routine is called to send data to the hardware.
485 fec_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
486 int total_len, unsigned long key)
488 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
489 struct fec_bd *txbd, *txfirst;
491 int i, txindex, cache_state;
493 HAL_DCACHE_IS_ENABLED(cache_state);
494 #ifndef FEC_BDs_NONCACHED
496 HAL_DCACHE_INVALIDATE(fec_eth_txring,
497 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
501 // Find a free buffer
502 txbd = txfirst = qi->txbd;
503 while (txbd->ctrl & FEC_BD_Tx_Ready) {
504 // This buffer is busy, move to next one
505 if (txbd->ctrl & FEC_BD_Tx_Wrap) {
510 if (txbd == txfirst) {
512 panic ("No free xmit buffers");
514 os_printf("FEC Ethernet: No free xmit buffers\n");
519 // Remember the next buffer to try
520 if (txbd->ctrl & FEC_BD_Tx_Wrap) {
521 qi->txbd = qi->tbase;
526 txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
527 qi->txkey[txindex] = key;
530 txbd->length = total_len;
532 for (i = 0; i < sg_len; i++) {
533 memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
534 bp += sg_list[i].len;
537 // Make sure no stale data buffer ...
539 HAL_DCACHE_FLUSH(txbd->buffer, txbd->length);
541 // Send it on it's way
542 txbd->ctrl |= FEC_BD_Tx_Ready | FEC_BD_Tx_Last | FEC_BD_Tx_TC;
543 #ifndef FEC_BDs_NONCACHED
545 HAL_DCACHE_FLUSH(fec_eth_txring,
546 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
553 // This function is called when a packet has been received. It's job is
554 // to prepare to unload the packet from the hardware. Once the length of
555 // the packet is known, the upper layer of the driver can be told. When
556 // the upper layer is ready to unload the packet, the internal function
557 // 'fec_eth_recv' will be called to actually fetch it from the hardware.
560 fec_eth_RxEvent(struct eth_drv_sc *sc)
562 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
566 HAL_DCACHE_IS_ENABLED(cache_state);
567 #ifndef FEC_BDs_NONCACHED
569 HAL_DCACHE_INVALIDATE(fec_eth_rxring,
570 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM);
575 while ((rxbd->ctrl & FEC_BD_Rx_Empty) == 0) {
576 qi->rxbd = rxbd; // Save for callback
578 // This is the right way of doing it, but dcbi has a bug ...
579 // if (cache_state) {
580 // HAL_DCACHE_INVALIDATE(rxbd->buffer, rxbd->length);
582 (sc->funs->eth_drv->recv)(sc, rxbd->length);
584 HAL_DCACHE_FLUSH(rxbd->buffer, rxbd->length);
587 rxbd->ctrl |= FEC_BD_Rx_Empty;
588 if (rxbd->ctrl & FEC_BD_Rx_Wrap) {
594 // Remember where we left off
595 qi->rnext = (struct fec_bd *)rxbd;
597 // Make sure no stale data
598 #ifndef FEC_BDs_NONCACHED
600 HAL_DCACHE_FLUSH(fec_eth_rxring,
601 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM);
608 // This function is called as a result of the "eth_drv_recv()" call above.
609 // It's job is to actually fetch data for a packet from the hardware once
610 // memory buffers have been allocated for the packet. Note that the buffers
611 // may come in pieces, using a scatter-gather list. This allows for more
612 // efficient processing in the upper layers of the stack.
615 fec_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
617 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
621 bp = (unsigned char *)qi->rxbd->buffer;
623 for (i = 0; i < sg_len; i++) {
624 if (sg_list[i].buf != 0) {
625 memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
626 bp += sg_list[i].len;
633 fec_eth_TxEvent(struct eth_drv_sc *sc, int stat)
635 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
637 int txindex, cache_state;
639 // Make sure no stale data
640 HAL_DCACHE_IS_ENABLED(cache_state);
641 #ifndef FEC_BDs_NONCACHED
643 HAL_DCACHE_INVALIDATE(fec_eth_txring,
644 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
649 // Note: TC field is used to indicate the buffer has/had data in it
650 while ( (txbd->ctrl & (FEC_BD_Tx_TC | FEC_BD_Tx_Ready)) == FEC_BD_Tx_TC ) {
651 txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
652 (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
653 txbd->ctrl &= ~FEC_BD_Tx_TC;
654 if (txbd->ctrl & FEC_BD_Tx_Wrap) {
660 // Remember where we left off
661 qi->tnext = (struct fec_bd *)txbd;
663 // Make sure no stale data
664 #ifndef FEC_BDs_NONCACHED
666 HAL_DCACHE_FLUSH(fec_eth_txring,
667 8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM);
674 // Interrupt processing
677 fec_eth_int(struct eth_drv_sc *sc)
679 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
680 unsigned long iEvent;
682 while ((iEvent = qi->fcc_reg->fcc_fcce) != 0){
684 // Writing 1's clear fcce, Writing 0's have no effect
685 qi->fcc_reg->fcc_fcce = iEvent;
687 // Tx Done or Tx Error
688 if ( iEvent & (FEC_EV_TXB | FEC_EV_TXE) ) {
689 fec_eth_TxEvent(sc, iEvent);
692 // Complete or non-complete frame receive
693 if (iEvent & (FEC_EV_RXF | FEC_EV_RXB) ) {
706 fec_eth_int_vector(struct eth_drv_sc *sc)
708 return (FEC_ETH_INT);