1 #ifndef CYGONCE_DEVS_ETH_SH_ETHERC_H
2 #define CYGONCE_DEVS_ETH_SH_ETHERC_H
3 //==========================================================================
7 // SH EtherC Ethernet CPU module controller
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
46 // Contributors: jskov
48 // Purpose: Hardware description of SH EtherC controller.
51 //####DESCRIPTIONEND####
53 //==========================================================================
55 #include <cyg/hal/hal_io.h>
57 //------------------------------------------------------------------------
58 // Get macros from platform header
60 #include CYGDAT_DEVS_ETH_SH_ETHERC_INL
63 //------------------------------------------------------------------------
65 // 0 disables all debug output
66 // 1 for process debug output
67 // 2 for added data IO output: get_reg, put_reg
68 // 4 for packet allocation/free output
69 // 8 for only startup status, so we can tell we're installed OK
73 #define DEBUG_FUNCTION() do { db_printf("%s\n", __FUNCTION__); } while (0)
75 #define DEBUG_FUNCTION() do {} while(0)
78 // ------------------------------------------------------------------------
79 // Debug print function
80 #if defined(CYGPKG_REDBOOT) && DEBUG
82 static void db_printf( char *fmt, ... )
84 extern int start_console(void);
85 extern void end_console(int);
89 old_console = start_console();
90 diag_vprintf( fmt, a );
91 end_console(old_console);
97 #define db_printf diag_printf
101 // ------------------------------------------------------------------------
102 // Macros for keeping track of statistics
103 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
104 # define KEEP_STATISTICS
107 #ifdef KEEP_STATISTICS
108 # define INCR_STAT( _x_ ) (cpd->stats. _x_ ++)
110 # define INCR_STAT( _x_ ) CYG_EMPTY_STATEMENT
113 //------------------------------------------------------------------------
115 #ifndef CYGARC_UNCACHED_ADDRESS
116 # define CYGARC_UNCACHED_ADDRESS(x) (x)
119 // ------------------------------------------------------------------------
120 // Macros for accessing structure elements
122 #define _SU8( _base_, _offset_) \
123 *((cyg_uint8 *)((CYG_ADDRWORD)_base_+(_offset_)))
124 #define _SU16( _base_, _offset_) \
125 *((cyg_uint16 *)((CYG_ADDRWORD)_base_+(_offset_)))
126 #define _SU32( _base_, _offset_) \
127 *((cyg_uint32 *)((CYG_ADDRWORD)_base_+(_offset_)))
129 #define _SI8( _base_, _offset_) \
130 *((cyg_int8 *)((CYG_ADDRWORD)_base_+(_offset_)))
131 #define _SI16( _base_, _offset_) \
132 *((cyg_int16 *)((CYG_ADDRWORD)_base_+(_offset_)))
133 #define _SI32( _base_, _offset_) \
134 *((cyg_int32 *)((CYG_ADDRWORD)_base_+(_offset_)))
136 // ------------------------------------------------------------------------
137 // Controller registers in offset form
138 #define _REG_EDMR 0x00
139 #define _REG_EDTRR 0x04
140 #define _REG_EDRRR 0x08
141 #define _REG_TDLAR 0x0c
142 #define _REG_RDLAR 0x10
143 #define _REG_EESR 0x14
144 #define _REG_EESIPR 0x18
145 #define _REG_TRSCER 0x1c
146 #define _REG_RMFCR 0x20
147 #define _REG_TFTR 0x24
148 #define _REG_FDR 0x28
149 #define _REG_RCR 0x2c
150 #define _REG_EDOCR 0x30
151 #define _REG_RBWAR 0x40
152 #define _REG_RDFAR 0x44
153 #define _REG_TBRAR 0x4c
154 #define _REG_TDFAR 0x50
156 #define _REG_ECMR 0x60
157 #define _REG_ECSR 0x64
158 #define _REG_ECSIPR 0x68
159 #define _REG_PIR 0x6c
160 #define _REG_MAHR 0x70
161 #define _REG_MALR 0x74
162 #define _REG_RFLR 0x78
163 #define _REG_PSR 0x7c
164 #define _REG_TROCR 0x80
165 #define _REG_CDCR 0x84
166 #define _REG_LCCR 0x88
167 #define _REG_CNDCR 0x8c
168 #define _REG_IFLCR 0x90
169 #define _REG_CECFR 0x94
170 #define _REG_FRECR 0x98
171 #define _REG_TSFRCR 0x9c
172 #define _REG_TLFRCR 0xa0
173 #define _REG_RFCR 0xa4
174 #define _REG_MAFCR 0xa8
176 //----------------------------------------------------------------------------
177 // Receive buffer Descriptor
178 #define ETHERC_RD_STAT 0x00 // 32 bit
179 #define ETHERC_RD_RBL 0x04 // 16 bit - receive buffer length
180 #define ETHERC_RD_RDL 0x06 // 16 bit - receive data length (-CRC)
181 #define ETHERC_RD_RBA 0x08 // 32 bit - receive buffer address
182 #define ETHERC_RD_PAD 0x0c // 32 bit
183 #define ETHERC_RD_SIZE 0x10
185 #define ETHERC_RD_STAT_RACT 0x80000000
186 #define ETHERC_RD_STAT_RDLE 0x40000000
187 #define ETHERC_RD_STAT_RFP_OTO 0x30000000 // one buffer to one frame
188 #define ETHERC_RD_STAT_RFE 0x08000000
189 #define ETHERC_RD_STAT_RFOF 0x00000200
190 #define ETHERC_RD_STAT_RMAF 0x00000080
191 #define ETHERC_RD_STAT_RRF 0x00000010
192 #define ETHERC_RD_STAT_RTLF 0x00000008
193 #define ETHERC_RD_STAT_RTSF 0x00000004
194 #define ETHERC_RD_STAT_PRE 0x00000002
195 #define ETHERC_RD_STAT_CERF 0x00000001
197 #define ETHERC_RD_STAT_CLEAR 0x70000000
199 // Transmit buffer Descriptor
200 #define ETHERC_TD_STAT 0x00 // 32 bit
201 #define ETHERC_TD_TDL 0x04 // 16 bit - transmit data length
202 #define ETHERC_TD_PAD0 0x06 // 16 bit
203 #define ETHERC_TD_TBA 0x08 // 32 bit - transmit buffer address
204 #define ETHERC_TD_PAD1 0x0c // 32 bit
205 #define ETHERC_TD_SIZE 0x10
207 #define ETHERC_TD_STAT_TACT 0x80000000
208 #define ETHERC_TD_STAT_TDLE 0x40000000
209 #define ETHERC_TD_STAT_TFP_OTO 0x30000000 // one buffer to one frame
210 #define ETHERC_TD_STAT_TDFE 0x08000000
211 #define ETHERC_TD_STAT_ITF 0x00000010
212 #define ETHERC_TD_STAT_CND 0x00000008
213 #define ETHERC_TD_STAT_DLC 0x00000004
214 #define ETHERC_TD_STAT_CD 0x00000002
215 #define ETHERC_TD_STAT_TRO 0x00000001
218 // Initialization Buffer
219 #define ETHERC_IB_MODE 0
220 #define ETHERC_IB_PADR0 2
221 #define ETHERC_IB_PADR1 4
222 #define ETHERC_IB_PADR2 6
223 #define ETHERC_IB_LADRF0 8
224 #define ETHERC_IB_LADRF1 10
225 #define ETHERC_IB_LADRF2 12
226 #define ETHERC_IB_LADRF3 14
227 #define ETHERC_IB_RDRA 16
228 #define ETHERC_IB_TDRA 20
229 #define ETHERC_IB_SIZE 24
231 #define ETHERC_IB_TDRA_CNT_shift 29
232 #define ETHERC_IB_TDRA_PTR_mask 0x00ffffff
233 #define ETHERC_IB_RDRA_CNT_shift 29
234 #define ETHERC_IB_RDRA_PTR_mask 0x00ffffff
236 // ------------------------------------------------------------------------
238 #ifdef KEEP_STATISTICS
239 struct sh_etherc_stats {
240 unsigned int tx_good ;
241 unsigned int tx_max_collisions ;
242 unsigned int tx_late_collisions ;
243 unsigned int tx_underrun ;
244 unsigned int tx_carrier_loss ;
245 unsigned int tx_deferred ;
246 unsigned int tx_sqetesterrors ;
247 unsigned int tx_single_collisions;
248 unsigned int tx_mult_collisions ;
249 unsigned int tx_total_collisions ;
250 unsigned int rx_good ;
251 unsigned int rx_crc_errors ;
252 unsigned int rx_align_errors ;
253 unsigned int rx_resource_errors ;
254 unsigned int rx_overrun_errors ;
255 unsigned int rx_collisions ;
256 unsigned int rx_short_frames ;
257 unsigned int rx_too_long_frames ;
258 unsigned int rx_symbol_errors ;
259 unsigned int interrupts ;
260 unsigned int rx_count ;
261 unsigned int rx_deliver ;
262 unsigned int rx_resource ;
263 unsigned int rx_restart ;
264 unsigned int tx_count ;
265 unsigned int tx_complete ;
266 unsigned int tx_dropped ;
270 struct etherc_priv_data;
271 typedef cyg_bool (*provide_esa_t)(struct etherc_priv_data* cpd);
273 typedef struct etherc_priv_data {
275 cyg_uint8 // (split up for atomic byte access)
276 mac_addr_ok:1, // can we bring up?
277 active:1, // has this if been brung up?
278 hardwired_esa:1, // set if ESA is hardwired via CDL
279 txbusy:1, // A packet has been sent
282 unsigned long txkey; // Used to ack when packet sent
283 unsigned char* base; // Base address of controller EPROM region
284 int interrupt; // Interrupt vector used by controller
285 unsigned char esa[6]; // Controller ESA
286 // Function to configure the ESA - may fetch ESA from EPROM or
287 // RedBoot config option.
288 void (*config_esa)(struct etherc_priv_data* cpd);
289 void *ndp; // Network Device Pointer
290 provide_esa_t provide_esa;
292 cyg_handle_t interrupt_handle;
293 cyg_interrupt interrupt_object;
296 cyg_uint8* rx_buffers; // ptr to base of buffer mem
297 cyg_uint8* rx_ring; // ptr to base of rx ring memory
298 int rx_ring_cnt; // number of entries in ring
299 int rx_ring_next; // index of next full ring entry
301 cyg_uint8* tx_buffers;
304 int tx_ring_free; // index of next free ring entry
305 int tx_ring_alloc; // index of first controller owned ring
306 int tx_ring_owned; // number of controller owned ring entries
309 #ifdef KEEP_STATISTICS
310 struct sh_etherc_stats stats;
317 // ------------------------------------------------------------------------
319 static __inline__ cyg_uint32
320 get_reg(struct etherc_priv_data *cpd, int regno)
324 HAL_READ_UINT32(cpd->base+regno, val);
327 db_printf("read reg %d val 0x%08x\n", regno, val);
332 static __inline__ void
333 put_reg(struct etherc_priv_data *cpd, int regno, cyg_uint32 val)
335 HAL_WRITE_UINT32(cpd->base+regno, val);
338 db_printf("write reg %d val 0x%08x\n", regno, val);
342 // ------------------------------------------------------------------------
343 #endif // CYGONCE_DEVS_ETH_SH_ETHERC_H