packages/devs/serial/generic/16x5x/v2_0/src/ser_16x5x.c

   1 //==========================================================================
   2 //
   3 //      io/serial/generic/16x5x/ser_16x5x.c
   4 //
   5 //      Generic 16x5x serial driver
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 // Copyright (C) 2003 Gary Thomas
  13 // Copyright (C) 2006 eCosCentric Limited
  14 //
  15 // eCos is free software; you can redistribute it and/or modify it under
  16 // the terms of the GNU General Public License as published by the Free
  17 // Software Foundation; either version 2 or (at your option) any later version.
  18 //
  19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  22 // for more details.
  23 //
  24 // You should have received a copy of the GNU General Public License along
  25 // with eCos; if not, write to the Free Software Foundation, Inc.,
  26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  27 //
  28 // As a special exception, if other files instantiate templates or use macros
  29 // or inline functions from this file, or you compile this file and link it
  30 // with other works to produce a work based on this file, this file does not
  31 // by itself cause the resulting work to be covered by the GNU General Public
  32 // License. However the source code for this file must still be made available
  33 // in accordance with section (3) of the GNU General Public License.
  34 //
  35 // This exception does not invalidate any other reasons why a work based on
  36 // this file might be covered by the GNU General Public License.
  37 // -------------------------------------------
  38 //####ECOSGPLCOPYRIGHTEND####
  39 //==========================================================================
  40 //#####DESCRIPTIONBEGIN####
  41 //
  42 // Author(s):    gthomas
  43 // Contributors: gthomas, jlarmour, jskov
  44 // Date:         1999-02-04
  45 // Purpose:      16x5x generic serial driver
  46 // Description:
  47 //
  48 //####DESCRIPTIONEND####
  49 //
  50 //==========================================================================
  51
  52 #include <pkgconf/system.h>
  53 #include <pkgconf/io_serial.h>
  54 #include <pkgconf/io.h>
  55
  56 #include <cyg/io/io.h>
  57 #include <cyg/hal/hal_intr.h>
  58 #include <cyg/io/devtab.h>
  59 #include <cyg/io/serial.h>
  60 #include <cyg/infra/diag.h>
  61 #include <cyg/infra/cyg_ass.h>
  62 #include <cyg/hal/hal_io.h>
  63
  64 // Only compile driver if an inline file with driver details was selected.
  65 #ifdef CYGDAT_IO_SERIAL_GENERIC_16X5X_INL
  66
  67 #ifndef CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP
  68 #define CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP 1
  69 #endif
  70
  71 #define SER_REG(_x_) ((_x_)*CYGPRI_IO_SERIAL_GENERIC_16X5X_STEP)
  72
  73 // Receive control Registers
  74 #define REG_rhr SER_REG(0)    // Receive holding register
  75 #define REG_isr SER_REG(2)    // Interrupt status register
  76 #define REG_lsr SER_REG(5)    // Line status register
  77 #define REG_msr SER_REG(6)    // Modem status register
  78 #define REG_scr SER_REG(7)    // Scratch register
  79
  80 // Transmit control Registers
  81 #define REG_thr SER_REG(0)    // Transmit holding register
  82 #define REG_ier SER_REG(1)    // Interrupt enable register
  83 #define REG_fcr SER_REG(2)    // FIFO control register
  84 #define REG_lcr SER_REG(3)    // Line control register
  85 #define REG_mcr SER_REG(4)    // Modem control register
  86 #define REG_ldl SER_REG(0)    // LSB of baud rate
  87 #define REG_mdl SER_REG(1)    // MSB of baud rate
  88
  89 // Interrupt Enable Register
  90 #define IER_RCV 0x01
  91 #define IER_XMT 0x02
  92 #define IER_LS  0x04
  93 #define IER_MS  0x08
  94
  95 // Line Control Register
  96 #define LCR_WL5 0x00    // Word length
  97 #define LCR_WL6 0x01
  98 #define LCR_WL7 0x02
  99 #define LCR_WL8 0x03
 100 #define LCR_SB1 0x00    // Number of stop bits
 101 #define LCR_SB1_5 0x04  // 1.5 -> only valid with 5 bit words
 102 #define LCR_SB2 0x04
 103 #define LCR_PN  0x00    // Parity mode - none
 104 #define LCR_PE  0x18    // Parity mode - even
 105 #define LCR_PO  0x08    // Parity mode - odd
 106 #define LCR_PM  0x28    // Forced "mark" parity
 107 #define LCR_PS  0x38    // Forced "space" parity
 108 #define LCR_DL  0x80    // Enable baud rate latch
 109
 110 // Line Status Register
 111 #define LSR_RSR 0x01
 112 #define LSR_OE  0x02
 113 #define LSR_PE  0x04
 114 #define LSR_FE  0x08
 115 #define LSR_BI  0x10
 116 #define LSR_THE 0x20
 117 #define LSR_TEMT 0x40
 118 #define LSR_FIE 0x80
 119
 120 // Modem Control Register
 121 #define MCR_DTR  0x01
 122 #define MCR_RTS  0x02
 123 #define MCR_INT  0x08   // Enable interrupts
 124 #define MCR_LOOP 0x10   // Loopback mode
 125
 126 // Interrupt status Register
 127 #define ISR_MS        0x00
 128 #define ISR_nIP       0x01
 129 #define ISR_Tx        0x02
 130 #define ISR_Rx        0x04
 131 #define ISR_LS        0x06
 132 #define ISR_RxTO      0x0C
 133 #define ISR_64BFIFO   0x20
 134 #define ISR_FIFOworks 0x40
 135 #define ISR_FIFOen    0x80
 136
 137 // Modem Status Register
 138 #define MSR_DCTS 0x01
 139 #define MSR_DDSR 0x02
 140 #define MSR_TERI 0x04
 141 #define MSR_DDCD 0x08
 142 #define MSR_CTS  0x10
 143 #define MSR_DSR  0x20
 144 #define MSR_RI   0x40
 145 #define MSR_CD   0x80
 146
 147 // FIFO Control Register
 148 #define FCR_FE   0x01    // FIFO enable
 149 #define FCR_CRF  0x02    // Clear receive FIFO
 150 #define FCR_CTF  0x04    // Clear transmit FIFO
 151 #define FCR_DMA  0x08    // DMA mode select
 152 #define FCR_F64  0x20    // Enable 64 byte fifo (16750+)
 153 #define FCR_RT14 0xC0    // Set Rx trigger at 14
 154 #define FCR_RT8  0x80    // Set Rx trigger at 8
 155 #define FCR_RT4  0x40    // Set Rx trigger at 4
 156 #define FCR_RT1  0x00    // Set Rx trigger at 1
 157
 158 static unsigned char select_word_length[] = {
 159     LCR_WL5,    // 5 bits / word (char)
 160     LCR_WL6,
 161     LCR_WL7,
 162     LCR_WL8
 163 };
 164
 165 static unsigned char select_stop_bits[] = {
 166     0,
 167     LCR_SB1,    // 1 stop bit
 168     LCR_SB1_5,  // 1.5 stop bit
 169     LCR_SB2     // 2 stop bits
 170 };
 171
 172 static unsigned char select_parity[] = {
 173     LCR_PN,     // No parity
 174     LCR_PE,     // Even parity
 175     LCR_PO,     // Odd parity
 176     LCR_PM,     // Mark parity
 177     LCR_PS,     // Space parity
 178 };
 179
 180 // selec_baud[] must be define by the client
 181
 182 typedef struct pc_serial_info {
 183     cyg_addrword_t base;
 184     int            int_num;
 185 #ifdef CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
 186     int            int_prio;
 187 #endif // CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
 188     cyg_interrupt  serial_interrupt;
 189     cyg_handle_t   serial_interrupt_handle;
 190 #ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
 191     enum {
 192         sNone = 0,
 193         s8250,
 194         s16450,
 195         s16550,
 196         s16550a
 197     } deviceType;
 198     unsigned tx_fifo_size;
 199     volatile unsigned tx_fifo_avail;
 200 #endif
 201 } pc_serial_info;
 202
 203 static bool pc_serial_init(struct cyg_devtab_entry *tab);
 204 static bool pc_serial_putc(serial_channel *chan, unsigned char c);
 205 static Cyg_ErrNo pc_serial_lookup(struct cyg_devtab_entry **tab,
 206                                   struct cyg_devtab_entry *sub_tab,
 207                                   const char *name);
 208 static unsigned char pc_serial_getc(serial_channel *chan);
 209 static Cyg_ErrNo pc_serial_set_config(serial_channel *chan, cyg_uint32 key,
 210                                       const void *xbuf, cyg_uint32 *len);
 211 static void pc_serial_start_xmit(serial_channel *chan);
 212 static void pc_serial_stop_xmit(serial_channel *chan);
 213
 214 static cyg_uint32 pc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
 215 static void       pc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count,
 216                                 cyg_addrword_t data);
 217
 218 static SERIAL_FUNS(pc_serial_funs,
 219                    pc_serial_putc,
 220                    pc_serial_getc,
 221                    pc_serial_set_config,
 222                    pc_serial_start_xmit,
 223                    pc_serial_stop_xmit
 224     );
 225
 226 #include CYGDAT_IO_SERIAL_GENERIC_16X5X_INL
 227
 228 #ifndef CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY
 229 # define CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY 4
 230 #endif
 231
 232
 233 // Internal function to actually configure the hardware to desired
 234 // baud rate, etc.
 235 static bool
 236 serial_config_port(serial_channel *chan,
 237                    cyg_serial_info_t *new_config, bool init)
 238 {
 239     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 240     cyg_addrword_t base = ser_chan->base;
 241     //
 242     // If the device supports a dynamic per channel baudrate generator
 243     // then we call the CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR()
 244     // macro to get the baud divisor. The macro takes the serial channel data
 245     // pointer and the baudrate as parameters and returns the baud divisior
 246     //
 247 #ifdef CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR
 248     unsigned short baud_divisor = CYG_IO_SERIAL_GENERIC_16X5X_CHAN_BAUD_GENERATOR(ser_chan, new_config->baud);
 249 #else
 250     unsigned short baud_divisor = select_baud[new_config->baud];
 251 #endif
 252     unsigned char _lcr, _ier;
 253     if (baud_divisor == 0) return false;  // Invalid configuration
 254
 255     // Disable port interrupts while changing hardware
 256     HAL_READ_UINT8(base+REG_ier, _ier);
 257     HAL_WRITE_UINT8(base+REG_ier, 0);
 258
 259     _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
 260         select_stop_bits[new_config->stop] |
 261         select_parity[new_config->parity];
 262     HAL_WRITE_UINT8(base+REG_lcr, _lcr | LCR_DL);
 263     HAL_WRITE_UINT8(base+REG_mdl, baud_divisor >> 8);
 264     HAL_WRITE_UINT8(base+REG_ldl, baud_divisor & 0xFF);
 265     HAL_WRITE_UINT8(base+REG_lcr, _lcr);
 266     if (init) {
 267 #ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
 268         unsigned char _fcr_thresh;
 269         cyg_uint8 b;
 270
 271         /* First, find out what kind of device it is. */
 272         ser_chan->deviceType = sNone;
 273         HAL_WRITE_UINT8(base+REG_mcr, MCR_LOOP); // enable loopback mode
 274         HAL_READ_UINT8(base+REG_msr, b);
 275         if (0 == (b & 0xF0)) {   // see if MSR had CD, RI, DSR or CTS set
 276             HAL_WRITE_UINT8(base+REG_mcr, MCR_LOOP|MCR_DTR|MCR_RTS);
 277             HAL_READ_UINT8(base+REG_msr, b);
 278             if (0xF0 != (b & 0xF0))  // check that all of CD,RI,DSR and CTS set
 279                 ser_chan->deviceType = s8250;
 280         }
 281         HAL_WRITE_UINT8(base+REG_mcr, 0); // disable loopback mode
 282
 283         if (ser_chan->deviceType == s8250) {
 284             // Check for a scratch register; scratch register
 285             // indicates 16450 or above.
 286             HAL_WRITE_UINT8(base+REG_scr, 0x55);
 287             HAL_READ_UINT8(base+REG_scr, b);
 288             if (b == 0x55) {
 289                 HAL_WRITE_UINT8(base+REG_scr, 0xAA);
 290                 HAL_READ_UINT8(base+REG_scr, b);
 291                 if (b == 0xAA)
 292                     ser_chan->deviceType = s16450;
 293             }
 294         }
 295
 296         if (ser_chan->deviceType == s16450) {
 297             // Check for a FIFO
 298             HAL_WRITE_UINT8(base+REG_fcr, FCR_FE);
 299             HAL_READ_UINT8(base+REG_isr, b);
 300             if (b & ISR_FIFOen)
 301                 ser_chan->deviceType = s16550; // but FIFO doesn't
 302                                                // necessarily work
 303             if (b & ISR_FIFOworks)
 304                 ser_chan->deviceType = s16550a; // 16550a FIFOs work
 305         }
 306
 307         if (ser_chan->deviceType == s16550a) {
 308             switch(CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO_RX_THRESHOLD) {
 309             default:
 310             case 1:
 311                 _fcr_thresh=FCR_RT1; break;
 312             case 4:
 313                 _fcr_thresh=FCR_RT4; break;
 314             case 8:
 315                 _fcr_thresh=FCR_RT8; break;
 316             case 14:
 317                 _fcr_thresh=FCR_RT14; break;
 318             }
 319             _fcr_thresh|=FCR_FE|FCR_CRF|FCR_CTF;
 320             ser_chan->tx_fifo_size =
 321               CYGNUM_IO_SERIAL_GENERIC_16X5X_FIFO_TX_SIZE;
 322             // Enable and clear FIFO
 323             HAL_WRITE_UINT8(base+REG_fcr, _fcr_thresh);
 324         }
 325         else {
 326             ser_chan->tx_fifo_size = 1;
 327             HAL_WRITE_UINT8(base+REG_fcr, 0); // make sure it's disabled
 328         }
 329
 330         ser_chan->tx_fifo_avail = ser_chan->tx_fifo_size;
 331 #endif
 332         if (chan->out_cbuf.len != 0) {
 333             _ier = IER_RCV;
 334         } else {
 335             _ier = 0;
 336         }
 337         // Master interrupt enable
 338         HAL_WRITE_UINT8(base+REG_mcr, MCR_INT|MCR_DTR|MCR_RTS);
 339     }
 340 #ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS
 341     _ier |= (IER_LS|IER_MS);
 342 #endif
 343     HAL_WRITE_UINT8(base+REG_ier, _ier);
 344
 345 #ifdef CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK
 346     CYGPRI_IO_SERIAL_GENERIC_16X5X_PLF_INIT_HOOK( ser_chan, new_config );
 347 #endif
 348
 349     if (new_config != &chan->config) {
 350         chan->config = *new_config;
 351     }
 352     return true;
 353 }
 354
 355 // Function to initialize the device.  Called at bootstrap time.
 356 static bool
 357 pc_serial_init(struct cyg_devtab_entry *tab)
 358 {
 359     serial_channel *chan = (serial_channel *)tab->priv;
 360     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 361
 362 #ifdef CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR
 363     // Fill in baud rate table - used for platforms where this cannot
 364     // be determined statically
 365     int baud_idx, baud_val;
 366     if (select_baud[0] == 9999) {
 367         // Table not yet initialized
 368         // Assumes that 'select_baud' looks like this:
 369         //   static int select_baud[] = {
 370         //       9999,  -- marker
 371         //       50,    -- first baud rate
 372         //       110,   -- second baud rate
 373         // etc.
 374         for (baud_idx = 1;  baud_idx < sizeof(select_baud)/sizeof(select_baud[0]);  baud_idx++) {
 375             baud_val = CYG_IO_SERIAL_GENERIC_16X5X_BAUD_GENERATOR(select_baud[baud_idx]);
 376             select_baud[baud_idx] = baud_val;
 377         }
 378         select_baud[0] = 0;
 379     }
 380 #endif
 381
 382 #ifdef CYGDBG_IO_INIT
 383     diag_printf("16x5x SERIAL init - dev: %x.%d\n",
 384                 ser_chan->base, ser_chan->int_num);
 385 #endif
 386     // Really only required for interrupt driven devices
 387     (chan->callbacks->serial_init)(chan);
 388     //
 389     // If the device supports per channel interrupt priorities then
 390     // we take the priority from the serial channel data. If it does
 391     // not support per channel interrupt priority we fall back to
 392     // the old method and use CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY
 393     // to define the priority
 394     //
 395 #ifdef CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
 396     cyg_priority_t intprio = ser_chan->int_prio;
 397 #else
 398     cyg_priority_t intprio = CYG_IO_SERIAL_GENERIC_16X5X_INT_PRIORITY;
 399 #endif // CYGINT_IO_SERIAL_GENERIC_16X5X_CHAN_INTPRIO
 400     if (chan->out_cbuf.len != 0) {
 401         cyg_drv_interrupt_create(ser_chan->int_num,
 402                                  intprio,
 403                                  (cyg_addrword_t)chan,
 404                                  pc_serial_ISR,
 405                                  pc_serial_DSR,
 406                                  &ser_chan->serial_interrupt_handle,
 407                                  &ser_chan->serial_interrupt);
 408         cyg_drv_interrupt_attach(ser_chan->serial_interrupt_handle);
 409         cyg_drv_interrupt_unmask(ser_chan->int_num);
 410     }
 411     serial_config_port(chan, &chan->config, true);
 412     return true;
 413 }
 414
 415 // This routine is called when the device is "looked" up (i.e. attached)
 416 static Cyg_ErrNo
 417 pc_serial_lookup(struct cyg_devtab_entry **tab,
 418                  struct cyg_devtab_entry *sub_tab,
 419                  const char *name)
 420 {
 421     serial_channel *chan = (serial_channel *)(*tab)->priv;
 422
 423     // Really only required for interrupt driven devices
 424     (chan->callbacks->serial_init)(chan);
 425     return ENOERR;
 426 }
 427
 428 // Send a character to the device output buffer.
 429 // Return 'true' if character is sent to device
 430 static bool
 431 pc_serial_putc(serial_channel *chan, unsigned char c)
 432 {
 433 #ifndef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
 434     cyg_uint8 _lsr;
 435 #endif
 436     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 437     cyg_addrword_t base = ser_chan->base;
 438
 439 #ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
 440     if (ser_chan->tx_fifo_avail > 0) {
 441         HAL_WRITE_UINT8(base+REG_thr, c);
 442         --ser_chan->tx_fifo_avail;
 443         return true;
 444     }
 445 #else
 446     HAL_READ_UINT8(base+REG_lsr, _lsr);
 447     if (_lsr & LSR_THE) {
 448         // Transmit buffer is empty
 449         HAL_WRITE_UINT8(base+REG_thr, c);
 450         return true;
 451     }
 452 #endif
 453     // No space
 454     return false;
 455 }
 456
 457 // Fetch a character from the device input buffer, waiting if necessary
 458 static unsigned char
 459 pc_serial_getc(serial_channel *chan)
 460 {
 461     unsigned char c;
 462     cyg_uint8 _lsr;
 463     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 464     cyg_addrword_t base = ser_chan->base;
 465
 466     // Wait for char
 467     do {
 468         HAL_READ_UINT8(base+REG_lsr, _lsr);
 469     } while ((_lsr & LSR_RSR) == 0);
 470
 471     HAL_READ_UINT8(base+REG_rhr, c);
 472     return c;
 473 }
 474
 475 // Set up the device characteristics; baud rate, etc.
 476 static Cyg_ErrNo
 477 pc_serial_set_config(serial_channel *chan, cyg_uint32 key, const void *xbuf,
 478                      cyg_uint32 *len)
 479 {
 480     switch (key) {
 481     case CYG_IO_SET_CONFIG_SERIAL_INFO:
 482       {
 483         cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
 484         if ( *len < sizeof(cyg_serial_info_t) ) {
 485             return -EINVAL;
 486         }
 487         *len = sizeof(cyg_serial_info_t);
 488         if ( true != serial_config_port(chan, config, false) )
 489             return -EINVAL;
 490       }
 491       break;
 492 #ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW
 493     case CYG_IO_SET_CONFIG_SERIAL_HW_RX_FLOW_THROTTLE:
 494       {
 495           cyg_uint8 _mcr;
 496           pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 497           cyg_addrword_t base = ser_chan->base;
 498           cyg_uint32 *f = (cyg_uint32 *)xbuf;
 499           unsigned char mask=0;
 500           if ( *len < sizeof(*f) )
 501               return -EINVAL;
 502
 503           if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_RX )
 504               mask = MCR_RTS;
 505           if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_RX )
 506               mask |= MCR_DTR;
 507           HAL_READ_UINT8(base+REG_mcr, _mcr);
 508           if (*f) // we should throttle
 509               _mcr &= ~mask;
 510           else // we should no longer throttle
 511               _mcr |= mask;
 512           HAL_WRITE_UINT8(base+REG_mcr, _mcr);
 513       }
 514       break;
 515     case CYG_IO_SET_CONFIG_SERIAL_HW_FLOW_CONFIG:
 516         // Nothing to do because we do support both RTSCTS and DSRDTR flow
 517         // control.
 518         // Other targets would clear any unsupported flags here and
 519         // would then return -ENOSUPP - the higher layer can then query
 520         // what flags are set and decide what to do. This is optimised for
 521         // the most common case - i.e. that authors know what their hardware
 522         // is capable of.
 523         // We just return ENOERR.
 524       break;
 525 #endif
 526     default:
 527         return -EINVAL;
 528     }
 529     return ENOERR;
 530 }
 531
 532 // Enable the transmitter on the device
 533 static void
 534 pc_serial_start_xmit(serial_channel *chan)
 535 {
 536     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 537     cyg_addrword_t base = ser_chan->base;
 538     cyg_uint8 _ier;
 539
 540     HAL_READ_UINT8(base+REG_ier, _ier);
 541     _ier |= IER_XMT;                    // Enable xmit interrupt
 542     HAL_WRITE_UINT8(base+REG_ier, _ier);
 543 #ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_XMIT_REQUIRE_PRIME
 544     (chan->callbacks->xmt_char)(chan);
 545 #endif
 546 }
 547
 548 // Disable the transmitter on the device
 549 static void
 550 pc_serial_stop_xmit(serial_channel *chan)
 551 {
 552     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 553     cyg_addrword_t base = ser_chan->base;
 554     cyg_uint8 _ier;
 555
 556     HAL_READ_UINT8(base+REG_ier, _ier);
 557     _ier &= ~IER_XMT;                   // Disable xmit interrupt
 558     HAL_WRITE_UINT8(base+REG_ier, _ier);
 559 }
 560
 561 // Serial I/O - low level interrupt handler (ISR)
 562 static cyg_uint32
 563 pc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
 564 {
 565     serial_channel *chan = (serial_channel *)data;
 566     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 567     cyg_drv_interrupt_mask(ser_chan->int_num);
 568     cyg_drv_interrupt_acknowledge(ser_chan->int_num);
 569     return CYG_ISR_CALL_DSR;  // Cause DSR to be run
 570 }
 571
 572 // Serial I/O - high level interrupt handler (DSR)
 573 static void
 574 pc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
 575 {
 576     serial_channel *chan = (serial_channel *)data;
 577     pc_serial_info *ser_chan = (pc_serial_info *)chan->dev_priv;
 578     cyg_addrword_t base = ser_chan->base;
 579     cyg_uint8 _isr;
 580
 581     // Check if we have an interrupt pending - note that the interrupt
 582     // is pending of the low bit of the isr is *0*, not 1.
 583     HAL_READ_UINT8(base+REG_isr, _isr);
 584     while ((_isr & ISR_nIP) == 0) {
 585         switch (_isr&0xE) {
 586         case ISR_Rx:
 587         case ISR_RxTO:
 588         {
 589             cyg_uint8 _lsr;
 590             unsigned char c;
 591             HAL_READ_UINT8(base+REG_lsr, _lsr);
 592             while(_lsr & LSR_RSR) {
 593                 HAL_READ_UINT8(base+REG_rhr, c);
 594                 (chan->callbacks->rcv_char)(chan, c);
 595                 HAL_READ_UINT8(base+REG_lsr, _lsr);
 596             }
 597             break;
 598         }
 599         case ISR_Tx:
 600 #ifdef CYGPKG_IO_SERIAL_GENERIC_16X5X_FIFO
 601             ser_chan->tx_fifo_avail = ser_chan->tx_fifo_size;
 602 #endif
 603             (chan->callbacks->xmt_char)(chan);
 604             break;
 605
 606 #ifdef CYGOPT_IO_SERIAL_SUPPORT_LINE_STATUS
 607         case ISR_LS:
 608             {
 609                 cyg_serial_line_status_t stat;
 610                 cyg_uint8 _lsr;
 611                 HAL_READ_UINT8(base+REG_lsr, _lsr);
 612
 613                 // this might look expensive, but it is rarely the case that
 614                 // more than one of these is set
 615                 stat.value = 1;
 616                 if ( _lsr & LSR_OE ) {
 617                     stat.which = CYGNUM_SERIAL_STATUS_OVERRUNERR;
 618                     (chan->callbacks->indicate_status)(chan, &stat );
 619                 }
 620                 if ( _lsr & LSR_PE ) {
 621                     stat.which = CYGNUM_SERIAL_STATUS_PARITYERR;
 622                     (chan->callbacks->indicate_status)(chan, &stat );
 623                 }
 624                 if ( _lsr & LSR_FE ) {
 625                     stat.which = CYGNUM_SERIAL_STATUS_FRAMEERR;
 626                     (chan->callbacks->indicate_status)(chan, &stat );
 627                 }
 628                 if ( _lsr & LSR_BI ) {
 629                     stat.which = CYGNUM_SERIAL_STATUS_BREAK;
 630                     (chan->callbacks->indicate_status)(chan, &stat );
 631                 }
 632             }
 633             break;
 634
 635         case ISR_MS:
 636             {
 637                 cyg_serial_line_status_t stat;
 638                 cyg_uint8 _msr;
 639
 640                 HAL_READ_UINT8(base+REG_msr, _msr);
 641 #ifdef CYGOPT_IO_SERIAL_FLOW_CONTROL_HW
 642                 if ( _msr & MSR_DDSR )
 643                     if ( chan->config.flags & CYGNUM_SERIAL_FLOW_DSRDTR_TX ) {
 644                         stat.which = CYGNUM_SERIAL_STATUS_FLOW;
 645                         stat.value = (0 != (_msr & MSR_DSR));
 646                         (chan->callbacks->indicate_status)(chan, &stat );
 647                     }
 648                 if ( _msr & MSR_DCTS )
 649                     if ( chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX ) {
 650                         stat.which = CYGNUM_SERIAL_STATUS_FLOW;
 651                         stat.value = (0 != (_msr & MSR_CTS));
 652                         (chan->callbacks->indicate_status)(chan, &stat );
 653                     }
 654 #endif
 655                 if ( _msr & MSR_DDCD ) {
 656                     stat.which = CYGNUM_SERIAL_STATUS_CARRIERDETECT;
 657                     stat.value = (0 != (_msr & MSR_CD));
 658                     (chan->callbacks->indicate_status)(chan, &stat );
 659                 }
 660                 if ( _msr & MSR_RI ) {
 661                     stat.which = CYGNUM_SERIAL_STATUS_RINGINDICATOR;
 662                     stat.value = 1;
 663                     (chan->callbacks->indicate_status)(chan, &stat );
 664                 }
 665                 if ( _msr & MSR_TERI ) {
 666                     stat.which = CYGNUM_SERIAL_STATUS_RINGINDICATOR;
 667                     stat.value = 0;
 668                     (chan->callbacks->indicate_status)(chan, &stat );
 669                 }
 670             }
 671             break;
 672 #endif
 673         default:
 674             // Yes, this assertion may well not be visible. *But*
 675             // if debugging, we may still successfully hit a breakpoint
 676             // on cyg_assert_fail, which _is_ useful
 677             CYG_FAIL("unhandled serial interrupt state");
 678         }
 679
 680         HAL_READ_UINT8(base+REG_isr, _isr);
 681     } // while
 682
 683     cyg_drv_interrupt_unmask(ser_chan->int_num);
 684 }
 685 #endif
 686
 687 // EOF ser_16x5x.c