1 //==========================================================================
5 // Atmel AT91 (ARM) SPI driver
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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30 // License. However the source code for this file must still be made available
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): Savin Zlobec <savin@elatec.si>
46 //####DESCRIPTIONEND####
48 //==========================================================================
50 #include <pkgconf/hal.h>
51 #include <pkgconf/io_spi.h>
52 #include <pkgconf/devs_spi_arm_at91.h>
54 #include <cyg/infra/cyg_type.h>
55 #include <cyg/infra/cyg_ass.h>
56 #include <cyg/hal/hal_io.h>
57 #include <cyg/hal/hal_if.h>
58 #include <cyg/hal/hal_intr.h>
59 #include <cyg/hal/drv_api.h>
60 #include <cyg/io/spi.h>
61 #include <cyg/io/spi_at91.h>
62 #include <cyg/error/codes.h>
64 // -------------------------------------------------------------------------
66 static cyg_uint32 spi_at91_ISR(cyg_vector_t vector, cyg_addrword_t data);
68 static void spi_at91_DSR(cyg_vector_t vector,
72 static void spi_at91_transaction_begin(cyg_spi_device *dev);
74 static void spi_at91_transaction_transfer(cyg_spi_device *dev,
77 const cyg_uint8 *tx_data,
81 static void spi_at91_transaction_tick(cyg_spi_device *dev,
85 static void spi_at91_transaction_end(cyg_spi_device* dev);
87 static int spi_at91_get_config(cyg_spi_device *dev,
92 static int spi_at91_set_config(cyg_spi_device *dev,
97 // -------------------------------------------------------------------------
100 cyg_spi_at91_bus_t cyg_spi_at91_bus = {
101 .spi_bus.spi_transaction_begin = spi_at91_transaction_begin,
102 .spi_bus.spi_transaction_transfer = spi_at91_transaction_transfer,
103 .spi_bus.spi_transaction_tick = spi_at91_transaction_tick,
104 .spi_bus.spi_transaction_end = spi_at91_transaction_end,
105 .spi_bus.spi_get_config = spi_at91_get_config,
106 .spi_bus.spi_set_config = spi_at91_set_config
109 CYG_SPI_DEFINE_BUS_TABLE(cyg_spi_at91_device_t, 0);
111 // -------------------------------------------------------------------------
114 cyg_spi_at91_bus_init(void)
116 // Create and attach SPI interrupt object
117 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_SPI,
119 (cyg_addrword_t)&cyg_spi_at91_bus,
122 &cyg_spi_at91_bus.spi_interrupt_handle,
123 &cyg_spi_at91_bus.spi_interrupt);
125 cyg_drv_interrupt_attach(cyg_spi_at91_bus.spi_interrupt_handle);
127 // Init transfer mutex and condition
128 cyg_drv_mutex_init(&cyg_spi_at91_bus.transfer_mx);
129 cyg_drv_cond_init(&cyg_spi_at91_bus.transfer_cond,
130 &cyg_spi_at91_bus.transfer_mx);
133 cyg_spi_at91_bus.transfer_end = true;
134 cyg_spi_at91_bus.cs_up = false;
136 // Soft reset the SPI controller
137 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SWRST);
139 // Configure SPI pins
141 // NOTE: here we let the SPI controller control
142 // the data in, out and clock signals, but
143 // we need to handle the chip selects manually
144 // in order to achieve better chip select control
145 // inbetween transactions.
147 // Put SPI MISO, MOIS and SPCK pins into peripheral mode
148 HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PDR, AT91_PIO_PSR_SPCK |
152 // Put SPI chip select pins in IO output mode
153 HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_SODR, AT91_SPI_PIO_NPCS(0x0F));
154 HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PER, AT91_SPI_PIO_NPCS(0x0F));
155 HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_OER, AT91_SPI_PIO_NPCS(0x0F));
157 // Call upper layer bus init
158 CYG_SPI_BUS_COMMON_INIT(&cyg_spi_at91_bus.spi_bus);
161 // -------------------------------------------------------------------------
164 spi_at91_ISR(cyg_vector_t vector, cyg_addrword_t data)
168 // Read the status register and disable
169 // the SPI int events that have occoured
171 HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, stat);
172 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_IDR, stat);
174 cyg_drv_interrupt_mask(vector);
175 cyg_drv_interrupt_acknowledge(vector);
177 return CYG_ISR_CALL_DSR;
181 spi_at91_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
183 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *) data;
186 // Read the status register and
187 // check for transfer completition
189 HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, stat);
191 if((stat & AT91_SPI_SR_ENDRX) && (stat & AT91_SPI_SR_ENDTX))
194 spi_bus->transfer_end = true;
195 cyg_drv_cond_signal(&spi_bus->transfer_cond);
199 // Transfer still in progress - unmask the SPI
200 // int so we can get more SPI int events
201 cyg_drv_interrupt_unmask(vector);
206 spi_at91_calc_scbr(cyg_spi_at91_device_t *dev)
211 // Calculate SCBR from baud rate
213 scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / (2*dev->cl_brate);
225 scbr = CYGNUM_HAL_ARM_AT91_CLOCK_SPEED / (64*dev->cl_brate);
238 dev->cl_scbr = (cyg_uint8)scbr;
242 dev->cl_scbr = (cyg_uint8)scbr;
250 spi_at91_start_transfer(cyg_spi_at91_device_t *dev)
252 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
257 // Force minimal delay between two transfers - in case two transfers
258 // follow each other w/o delay, then we have to wait here in order for
259 // the peripheral device to detect cs transition from inactive to active.
260 CYGACC_CALL_IF_DELAY_US(dev->tr_bt_udly);
264 #ifdef CYGHWR_DEVS_SPI_ARM_AT91_PCSDEC
265 HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_CODR,
266 AT91_SPI_PIO_NPCS(~dev->dev_num));
268 HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_CODR,
269 AT91_SPI_PIO_NPCS(1<<dev->dev_num));
271 CYGACC_CALL_IF_DELAY_US(dev->cs_up_udly);
273 spi_bus->cs_up = true;
277 spi_at91_drop_cs(cyg_spi_at91_device_t *dev)
279 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
286 CYGACC_CALL_IF_DELAY_US(dev->cs_dw_udly);
287 HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_SODR, AT91_SPI_PIO_NPCS(0x0F));
288 spi_bus->cs_up = false;
292 spi_at91_transfer(cyg_spi_at91_device_t *dev,
294 const cyg_uint8 *tx_data,
297 cyg_spi_at91_bus_t *spi_bus = (cyg_spi_at91_bus_t *)dev->spi_device.spi_bus;
299 // Since PDC transfer buffer counters are 16 bit long,
300 // we have to split longer transfers into chunks.
303 cyg_uint16 tr_count = count > 0xFFFF ? 0xFFFF : count;
305 // Set rx buf pointer and counter
308 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_RPR, (cyg_uint32)rx_data);
309 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_RCR, (cyg_uint32)tr_count);
312 // Set tx buf pointer and counter
313 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_TPR, (cyg_uint32)tx_data);
314 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_TCR, (cyg_uint32)tr_count);
316 // Enable the SPI int events we are interested in
317 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_IER, AT91_SPI_SR_ENDRX |
320 cyg_drv_mutex_lock(&spi_bus->transfer_mx);
322 spi_bus->transfer_end = false;
324 // Unmask the SPI int
325 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_SPI);
327 // Wait for its completition
330 while (!spi_bus->transfer_end)
331 cyg_drv_cond_wait(&spi_bus->transfer_cond);
333 cyg_drv_dsr_unlock();
335 cyg_drv_mutex_unlock(&spi_bus->transfer_mx);
341 // If rx buffer was NULL, then the PDC receiver data transfer
342 // was not started and we didn't wait for ENDRX, but only for
343 // ENDTX. Meaning that right now the last byte is being serialized
344 // over the line and when finished input data will appear in
345 // rx data reg. We have to wait for this to happen here, if we
346 // don't we'll get the last received byte as the first one in the
349 // FIXME: is there any better way to do this?
350 // If not, then precalculate this value.
351 val = 8000000/dev->cl_brate;
352 CYGACC_CALL_IF_DELAY_US(val > 1 ? val : 1);
354 // Clear the rx data reg
355 HAL_READ_UINT32(AT91_SPI+AT91_SPI_RDR, val);
358 // Adjust running variables
368 spi_at91_transfer_polled(cyg_spi_at91_device_t *dev,
370 const cyg_uint8 *tx_data,
375 // Transmit and receive byte by byte
378 // Wait for transmit data register empty
381 HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, val);
382 } while ( !(val & AT91_SPI_SR_TDRE) );
384 // Send next byte over the wire
386 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_TDR, val);
388 // Wait for reveive data register full
391 HAL_READ_UINT32(AT91_SPI+AT91_SPI_SR, val);
392 } while ( !(val & AT91_SPI_SR_RDRF) );
394 // Store received byte
395 HAL_READ_UINT32(AT91_SPI+AT91_SPI_RDR, val);
401 // -------------------------------------------------------------------------
404 spi_at91_transaction_begin(cyg_spi_device *dev)
406 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
409 if (!at91_spi_dev->init)
411 at91_spi_dev->init = true;
412 spi_at91_calc_scbr(at91_spi_dev);
415 // Configure SPI channel 0 - this is the only channel we
416 // use for all devices since we drive chip selects manually
418 val = AT91_SPI_CSR_BITS8;
420 if (1 == at91_spi_dev->cl_pol)
421 val |= AT91_SPI_CSR_CPOL;
423 if (1 == at91_spi_dev->cl_pha)
424 val |= AT91_SPI_CSR_NCPHA;
426 val |= AT91_SPI_CSR_SCBR(at91_spi_dev->cl_scbr);
428 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CSR0, val);
431 HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCER, AT91_PMC_PCER_SPI);
433 // Enable the SPI controller
434 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SPIEN);
436 // Put SPI bus into master mode
437 if (1 == at91_spi_dev->cl_div32)
438 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_MR, AT91_SPI_MR_MSTR |
441 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_MR, AT91_SPI_MR_MSTR);
445 spi_at91_transaction_transfer(cyg_spi_device *dev,
448 const cyg_uint8 *tx_data,
452 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
454 // Select the device if not already selected
455 spi_at91_start_transfer(at91_spi_dev);
457 // Perform the transfer
459 spi_at91_transfer_polled(at91_spi_dev, count, tx_data, rx_data);
461 spi_at91_transfer(at91_spi_dev, count, tx_data, rx_data);
463 // Deselect the device if requested
465 spi_at91_drop_cs(at91_spi_dev);
469 spi_at91_transaction_tick(cyg_spi_device *dev,
473 const cyg_uint32 zeros[10] = { 0,0,0,0,0,0,0,0,0,0 };
475 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
477 // Transfer count zeros to the device - we don't touch the
478 // chip select, the device could be selected or deselected.
479 // It is up to the device driver to decide in wich state the
480 // device will be ticked.
484 int tcnt = count > 40 ? 40 : count;
487 spi_at91_transfer_polled(at91_spi_dev, tcnt,
488 (const cyg_uint8 *) zeros, NULL);
490 spi_at91_transfer(at91_spi_dev, tcnt,
491 (const cyg_uint8 *) zeros, NULL);
498 spi_at91_transaction_end(cyg_spi_device* dev)
500 // Disable the SPI controller
501 HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SPIDIS);
504 HAL_WRITE_UINT32(AT91_PMC+AT91_PMC_PCDR, AT91_PMC_PCER_SPI);
506 spi_at91_drop_cs((cyg_spi_at91_device_t *) dev);
510 spi_at91_get_config(cyg_spi_device *dev,
515 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
519 case CYG_IO_GET_CONFIG_SPI_CLOCKRATE:
521 if (*len != sizeof(cyg_uint32))
525 cyg_uint32 *cl_brate = (cyg_uint32 *)buf;
526 *cl_brate = at91_spi_dev->cl_brate;
537 spi_at91_set_config(cyg_spi_device *dev,
542 cyg_spi_at91_device_t *at91_spi_dev = (cyg_spi_at91_device_t *) dev;
546 case CYG_IO_SET_CONFIG_SPI_CLOCKRATE:
548 if (*len != sizeof(cyg_uint32))
552 cyg_uint32 cl_brate = *((cyg_uint32 *)buf);
553 cyg_uint32 old_cl_brate = at91_spi_dev->cl_brate;
555 at91_spi_dev->cl_brate = cl_brate;
557 if (!spi_at91_calc_scbr(at91_spi_dev))
559 at91_spi_dev->cl_brate = old_cl_brate;
560 spi_at91_calc_scbr(at91_spi_dev);
572 // -------------------------------------------------------------------------