1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
3 //=============================================================================
7 // HAL cache control API
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): nickg, gthomas
46 // Contributors: nickg, gthomas
48 // Purpose: Cache control API
49 // Description: The macros defined here provide the HAL APIs for handling
50 // cache control operations.
52 // #include <cyg/hal/hal_cache.h>
56 //####DESCRIPTIONEND####
58 //=============================================================================
60 #include <cyg/infra/cyg_type.h>
61 #include <cyg/hal/hal_io.h>
62 #include <cyg/hal/plf_io.h>
64 //-----------------------------------------------------------------------------
65 // Cache dimensions - one unified cache
67 #define HAL_CACHE_UNIFIED
69 #define HAL_UCACHE_SIZE 0x2000 // Size of cache in bytes
70 #define HAL_UCACHE_LINE_SIZE 16 // Size of a cache line
71 #define HAL_UCACHE_WAYS 2 // Associativity of the cache
73 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
75 //-----------------------------------------------------------------------------
76 // Global control of cache
79 #define HAL_UCACHE_ENABLE() \
82 HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
83 syscfg |= KS32C_SYSCFG_CE; \
84 HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \
88 #define HAL_UCACHE_DISABLE() \
91 HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
92 syscfg &= ~KS32C_SYSCFG_CE; \
93 HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \
96 // Invalidate the entire cache
97 #define HAL_UCACHE_INVALIDATE_ALL() \
99 register cyg_uint32* tag = (cyg_uint32*)KS32C_CACHE_TAG_ADDR; \
101 for (i = 0; i < HAL_UCACHE_SETS/4; i++) { \
109 // Synchronize the contents of the cache with memory.
110 // No action necessary. Cache is write-through.
111 #define HAL_UCACHE_SYNC()
113 // Query the state of the cache
114 #define HAL_UCACHE_IS_ENABLED(_state_) \
117 HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
118 (_state_) = (syscfg & KS32C_SYSCFG_CE) ? 1 : 0; \
121 // Purge contents of cache
122 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
124 // Set the cache refill burst size
125 //#define HAL_UCACHE_BURST_SIZE(_size_)
127 // Set the cache write mode
128 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
130 //#define HAL_UCACHE_WRITETHRU_MODE 0
131 //#define HAL_UCACHE_WRITEBACK_MODE 1
133 // Load the contents of the given address range into the cache
134 // and then lock the cache so that it stays there.
135 //#define HAL_UCACHE_LOCK(_base_, _size_)
137 // Undo a previous lock operation
138 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
140 // Unlock entire cache
141 //#define HAL_UCACHE_UNLOCK_ALL()
143 //-----------------------------------------------------------------------------
144 // Cache line control
146 // Allocate cache lines for the given address range without reading its
147 // contents from memory.
148 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
150 // Write dirty cache lines to memory and invalidate the cache entries
151 // for the given address range.
152 //#define HAL_UCACHE_FLUSH( _base_ , _size_ )
154 // Invalidate cache lines in the given range without writing to memory.
155 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
157 // Write dirty cache lines to memory for the given address range.
158 //#define HAL_UCACHE_STORE( _base_ , _size_ )
160 // Preread the given range into the cache with the intention of reading
162 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
164 // Preread the given range into the cache with the intention of writing
166 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
168 // Allocate and zero the cache lines associated with the given range.
169 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
171 //-----------------------------------------------------------------------------
173 //-----------------------------------------------------------------------------
174 // Data and instruction cache macros map onto the both-cache macros
176 //-----------------------------------------------------------------------------
177 // Global control of data cache
179 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
180 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
181 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
182 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
184 // Enable the data cache
185 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
187 // Disable the data cache
188 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
190 // Invalidate the entire cache
191 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
193 // Synchronize the contents of the cache with memory.
194 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
196 // Query the state of the data cache
197 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
199 // Set the data cache refill burst size
200 //#define HAL_DCACHE_BURST_SIZE(_size_)
202 // Set the data cache write mode
203 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
205 //#define HAL_DCACHE_WRITETHRU_MODE 0
206 //#define HAL_DCACHE_WRITEBACK_MODE 1
208 // Load the contents of the given address range into the data cache
209 // and then lock the cache so that it stays there.
210 //#define HAL_DCACHE_LOCK(_base_, _size_)
212 // Undo a previous lock operation
213 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
215 // Unlock entire cache
216 //#define HAL_DCACHE_UNLOCK_ALL()
218 //-----------------------------------------------------------------------------
219 // Data cache line control
221 // Allocate cache lines for the given address range without reading its
222 // contents from memory.
223 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
225 // Write dirty cache lines to memory and invalidate the cache entries
226 // for the given address range.
227 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
229 // Invalidate cache lines in the given range without writing to memory.
230 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
232 // Write dirty cache lines to memory for the given address range.
233 //#define HAL_DCACHE_STORE( _base_ , _size_ )
235 // Preread the given range into the cache with the intention of reading
237 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
239 // Preread the given range into the cache with the intention of writing
241 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
243 // Allocate and zero the cache lines associated with the given range.
244 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
246 //-----------------------------------------------------------------------------
247 // Global control of Instruction cache
249 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
250 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
251 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
252 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
254 // Enable the instruction cache
255 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
257 // Disable the instruction cache
258 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
260 // Invalidate the entire cache
261 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
264 // Synchronize the contents of the cache with memory.
265 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
267 // Query the state of the instruction cache
268 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
270 // Set the instruction cache refill burst size
271 //#define HAL_ICACHE_BURST_SIZE(_size_)
273 // Load the contents of the given address range into the instruction cache
274 // and then lock the cache so that it stays there.
276 //#define HAL_ICACHE_LOCK(_base_, _size_)
278 // Undo a previous lock operation
279 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
281 // Unlock entire cache
282 //#define HAL_ICACHE_UNLOCK_ALL()
284 //-----------------------------------------------------------------------------
285 // Instruction cache line control
287 // Invalidate cache lines in the given range without writing to memory.
288 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
290 #endif // ifndef CYGONCE_HAL_CACHE_H
291 // End of hal_cache.h