1 //=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): michael anburaj <michaelanburaj@hotmail.com>
44 // Contributors: michael anburaj <michaelanburaj@hotmail.com>
46 // Purpose: HAL diagnostic output
47 // Description: Implementations of HAL diagnostic output support.
49 //####DESCRIPTIONEND####
51 //=============================================================================
53 #include <pkgconf/hal.h>
54 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
55 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
57 #include <cyg/infra/cyg_type.h> // base types
58 #include <cyg/infra/cyg_trac.h> // tracing macros
59 #include <cyg/infra/cyg_ass.h> // assertion macros
61 #include <cyg/hal/hal_arch.h> // basic machine info
62 #include <cyg/hal/hal_intr.h> // interrupt macros
63 #include <cyg/hal/hal_io.h> // IO macros
64 #include <cyg/hal/hal_diag.h>
65 #include <cyg/hal/drv_api.h>
66 #include <cyg/hal/hal_if.h> // interface API
67 #include <cyg/hal/hal_misc.h> // Helper functions
68 #include <cyg/hal/s3c2410x.h> // platform definitions
70 //-----------------------------------------------------------------------------
73 cyg_int32 msec_timeout;
77 static channel_data_t smdk_ser_channels[2] = {
78 {(cyg_uint32)ULCON0, 1000, CYGNUM_HAL_INTERRUPT_UART0},
79 {(cyg_uint32)ULCON1, 1000, CYGNUM_HAL_INTERRUPT_UART1}
83 #define __READ_UINT32( _register_ ) *((volatile CYG_WORD32 *)(_register_))
86 //-----------------------------------------------------------------------------
89 cyg_hal_plf_serial_init_channel(void* __ch_data)
91 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
93 //UART FIFO control register
94 HAL_WRITE_UINT32(base+OFS_UFCON, (3<<6) | (3<<4) | (1<<2) | (1<<1) | (1<<0));
96 //UART modem control register
97 HAL_WRITE_UINT32(base+OFS_UMCON, 0);
99 //UART line control register: Normal,No parity,1 stop,8 bits
100 HAL_WRITE_UINT32(base+OFS_ULCON, 0x3);
102 //UART control register
103 HAL_WRITE_UINT32(base+OFS_UCON, 0x245);
105 //UART baud divider register
106 HAL_WRITE_UINT32(base+OFS_UBRDIV, (cyg_uint32)((FCLK/4)/16./CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD+0.5) -1);
110 cyg_hal_plf_serial_putc(void* __ch_data, char c)
112 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
114 CYGARC_HAL_SAVE_GP();
116 // Wait for Tx FIFO not full
119 HAL_READ_UINT32(base+OFS_UFSTAT, status);
121 while (status & 0x200) ;
123 //UART TX data register
124 HAL_WRITE_UINT8(base+OFS_UTXH, c);
126 CYGARC_HAL_RESTORE_GP();
130 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
132 cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
135 HAL_READ_UINT32(base+OFS_UFSTAT, status);
138 HAL_READ_UINT8(base+OFS_URXH, *ch);
146 cyg_hal_plf_serial_getc(void* __ch_data)
149 CYGARC_HAL_SAVE_GP();
151 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
153 CYGARC_HAL_RESTORE_GP();
158 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
161 CYGARC_HAL_SAVE_GP();
164 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
166 CYGARC_HAL_RESTORE_GP();
170 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
172 CYGARC_HAL_SAVE_GP();
175 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
177 CYGARC_HAL_RESTORE_GP();
181 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
184 channel_data_t* chan = (channel_data_t*)__ch_data;
186 CYGARC_HAL_SAVE_GP();
188 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
191 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
192 if (res || 0 == delay_count--)
195 CYGACC_CALL_IF_DELAY_US(100);
198 CYGARC_HAL_RESTORE_GP();
203 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
205 static int irq_state = 0;
206 channel_data_t* chan = (channel_data_t*)__ch_data;
208 CYGARC_HAL_SAVE_GP();
211 case __COMMCTL_IRQ_ENABLE:
213 HAL_INTERRUPT_UNMASK(chan->isr_vector);
215 case __COMMCTL_IRQ_DISABLE:
218 HAL_INTERRUPT_MASK(chan->isr_vector);
220 case __COMMCTL_DBG_ISR_VECTOR:
221 ret = chan->isr_vector;
223 case __COMMCTL_SET_TIMEOUT:
227 va_start(ap, __func);
229 ret = chan->msec_timeout;
230 chan->msec_timeout = va_arg(ap, cyg_uint32);
237 CYGARC_HAL_RESTORE_GP();
242 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
243 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
246 channel_data_t* chan = (channel_data_t*)__ch_data;
249 CYGARC_HAL_SAVE_GP();
251 cyg_drv_interrupt_acknowledge(chan->isr_vector);
254 HAL_READ_UINT32(chan->base+OFS_UFSTAT, lsr);
257 HAL_READ_UINT8(chan->base+OFS_URXH, c);
258 if( cyg_hal_is_break( &c , 1 ) )
261 res = CYG_ISR_HANDLED;
264 CYGARC_HAL_RESTORE_GP();
269 cyg_hal_plf_serial_init(void)
271 hal_virtual_comm_table_t* comm;
272 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
274 // Disable interrupts.
275 HAL_INTERRUPT_MASK(smdk_ser_channels[0].isr_vector);
276 HAL_INTERRUPT_MASK(smdk_ser_channels[1].isr_vector);
278 //Unmask UART0/1 RX interrupt
279 HAL_WRITE_UINT32(INTSUBMSK, __READ_UINT32(INTSUBMSK) & ~(BIT_SUB_RXD0|BIT_SUB_RXD1));
282 cyg_hal_plf_serial_init_channel(&smdk_ser_channels[0]);
283 cyg_hal_plf_serial_init_channel(&smdk_ser_channels[1]);
285 // Setup procs in the vector table
288 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
289 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
290 CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[0]);
291 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
292 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
293 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
294 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
295 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
296 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
297 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
300 CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
301 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
302 CYGACC_COMM_IF_CH_DATA_SET(*comm, &smdk_ser_channels[1]);
303 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
304 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
305 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
306 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
307 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
308 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
309 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
311 // Restore original console
312 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
316 cyg_hal_plf_comms_init(void)
318 static int initialized = 0;
325 cyg_hal_plf_serial_init();
328 //-----------------------------------------------------------------------------