1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //=============================================================================
42 //#####DESCRIPTIONBEGIN####
45 // Contributors:gthomas, tdrury, nickg, block
47 // Purpose: AT91/phycore platform specific support routines
49 // Usage: #include <cyg/hal/hal_platform_setup.h>
51 //####DESCRIPTIONEND####
53 //===========================================================================*/
55 #include <cyg/hal/var_io.h>
57 //===========================================================================*/
62 str r1,[r0,#AT91_PIO_PER]
63 str r1,[r0,#AT91_PIO_OER]
70 str r1,[r0,#AT91_PIO_SODR]
72 str r1,[r0,#AT91_PIO_CODR]
76 ldr r0,=AT91_PMC // Power saving interface
77 ldr r1,=0xFFFFFFFF // Enable all peripheral [clocks]
78 str r1,[r0,#AT91_PMC_PCER]
82 ldr r0,=AT91_PIOA // Disable PIO (so peripherals can use bits)
83 ldr r1,=(0x006d8000) // Enable UARTS 0/1/2 to use pins
84 str r1,[r0,#AT91_PIO_PDR]
87 #define CYGHWR_LED_MACRO _led \x
89 //===========================================================================*/
91 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
93 #define AT91_PMC_CGMR_INIT0 (AT91_PMC_CGMR_MOSC_XTAL | \
94 AT91_PMC_CGMR_MOSC_ENA | \
95 AT91_PMC_CGMR_OSC_CNT(47))
97 #define AT91_PMC_CGMR_INIT1 (AT91_PMC_CGMR_INIT0 | \
98 AT91_PMC_CGMR_CSS_MOSC)
100 #define AT91_PMC_CGMR_INIT2 (AT91_PMC_CGMR_INIT1 | \
101 AT91_PMC_CGMR_PLL_MUL(1) | \
102 AT91_PMC_CGMR_PLL_CNT(255))
104 #define AT91_PMC_CGMR_INIT3 (AT91_PMC_CGMR_INIT0 | \
105 AT91_PMC_CGMR_PLL_MUL(1) | \
106 AT91_PMC_CGMR_PLL_CNT(3) | \
107 AT91_PMC_CGMR_CSS_PLL)
112 // Change system frequency from 32kHz to 32MHz.
114 // First enable the master oscillator to run at 16MHz from
117 ldr r3,=AT91_PMC_CGMR_INIT0
118 str r3,[r2,#AT91_PMC_CGMR]
120 // Wait for MOSC to stabilize.
121 mov r4,#AT91_PMC_SR_MOSCS
123 ldr r3,[r2,#AT91_PMC_SR]
125 cmp r3,r4 //#AT91_PMC_SR_MOSCS
128 // Now switch CPU clock to use master oscillator, after this we
129 // should be running at 16MHz.
130 ldr r3,=AT91_PMC_CGMR_INIT1
131 str r3,[r2,#AT91_PMC_CGMR]
133 // Now enable PLL to run at twice MOSC frequency
134 ldr r3,=AT91_PMC_CGMR_INIT2
135 str r3,[r2,#AT91_PMC_CGMR]
137 // Wait for PLL to stabilize
138 mov r4,#AT91_PMC_SR_LOCK
140 ldr r3,[r2,#AT91_PMC_SR]
145 // Finally, switch CPU clock from MOSC to PLL
146 ldr r3,=AT91_PMC_CGMR_INIT3
147 str r3,[r2,#AT91_PMC_CGMR]
149 // All done, we should be running at 32MHz now
151 ldr r10,=_InitMemory // Initialize memory controller
152 movs r0,pc,lsr #20 // If ROM startup, PC < 0x100000
153 moveq r10,r10,lsl #12 // mask address to low 20 bits
154 moveq r10,r10,lsr #12
155 ldmia r10!,{r0-r9,r11-r12} // Table of initialization constants
156 #if defined(CYG_HAL_STARTUP_ROMRAM)
162 stmia r11!,{r0-r9} // Write to controller
163 mov pc,r12 // Change address space, break pipeline
165 .long 0x01002529 // 0x01000000, 16MB, 2 cycles after transfer, 16-bit, 6 wait states
166 .long 0x020034A5 // 0x02000000, 16MB, 0 cycles after transfer, 16-bit, 1 wait state
167 .long 0x20000000 // unused
168 .long 0x30000000 // unused
169 .long 0x40000000 // unused
170 .long 0x50000000 // unused
171 .long 0x60000000 // unused
172 .long 0x70000000 // unused
173 .long 0x00000001 // REMAP command
174 .long 0x00000000 // Standard read protocol
175 .long AT91_EBI // External Bus Interface address
176 .long 10f // address where to jump
178 #if defined(CYG_HAL_STARTUP_ROMRAM)
179 ldr r0,=0x01000000 // Relocate FLASH/ROM to on-chip RAM
180 ldr r1,=0x02000000 // RAM base & length
194 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
206 #define PLATFORM_SETUP1 _setup
209 //-----------------------------------------------------------------------------
210 // end of hal_platform_setup.h
211 #endif // CYGONCE_HAL_PLATFORM_SETUP_H