1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): nickg, gthomas
47 // Contributors: nickg, gthomas
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/hal_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <cyg/infra/cyg_type.h>
62 #include <cyg/hal/hal_io.h>
63 #include <cyg/hal/plf_io.h>
65 //-----------------------------------------------------------------------------
66 // Cache dimensions - one unified cache
68 #define HAL_CACHE_UNIFIED
70 #define HAL_UCACHE_SIZE 0x2000 // Size of cache in bytes
71 #define HAL_UCACHE_LINE_SIZE 16 // Size of a cache line
72 #define HAL_UCACHE_WAYS 2 // Associativity of the cache
74 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
76 //-----------------------------------------------------------------------------
77 // Global control of cache
80 #define HAL_UCACHE_ENABLE() \
83 HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
84 syscfg |= E7T_SYSCFG_CE; \
85 HAL_WRITE_UINT32(E7T_SYSCFG, syscfg); \
89 #define HAL_UCACHE_DISABLE() \
92 HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
93 syscfg &= ~E7T_SYSCFG_CE; \
94 HAL_WRITE_UINT32(E7T_SYSCFG, syscfg); \
97 // Invalidate the entire cache
98 #define HAL_UCACHE_INVALIDATE_ALL() \
100 register cyg_uint32* tag = (cyg_uint32*)E7T_CACHE_TAG_ADDR; \
102 for (i = 0; i < HAL_UCACHE_SETS/4; i++) { \
110 // Synchronize the contents of the cache with memory.
111 // No action necessary. Cache is write-through.
112 #define HAL_UCACHE_SYNC()
114 // Query the state of the cache
115 #define HAL_UCACHE_IS_ENABLED(_state_) \
118 HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
119 (_state_) = (syscfg & E7T_SYSCFG_CE) ? 1 : 0; \
122 // Purge contents of cache
123 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
125 // Set the cache refill burst size
126 //#define HAL_UCACHE_BURST_SIZE(_size_)
128 // Set the cache write mode
129 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
131 //#define HAL_UCACHE_WRITETHRU_MODE 0
132 //#define HAL_UCACHE_WRITEBACK_MODE 1
134 // Load the contents of the given address range into the cache
135 // and then lock the cache so that it stays there.
136 //#define HAL_UCACHE_LOCK(_base_, _size_)
138 // Undo a previous lock operation
139 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
141 // Unlock entire cache
142 //#define HAL_UCACHE_UNLOCK_ALL()
144 //-----------------------------------------------------------------------------
145 // Cache line control
147 // Allocate cache lines for the given address range without reading its
148 // contents from memory.
149 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
151 // Write dirty cache lines to memory and invalidate the cache entries
152 // for the given address range.
153 //#define HAL_UCACHE_FLUSH( _base_ , _size_ )
155 // Invalidate cache lines in the given range without writing to memory.
156 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
158 // Write dirty cache lines to memory for the given address range.
159 //#define HAL_UCACHE_STORE( _base_ , _size_ )
161 // Preread the given range into the cache with the intention of reading
163 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
165 // Preread the given range into the cache with the intention of writing
167 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
169 // Allocate and zero the cache lines associated with the given range.
170 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
172 //-----------------------------------------------------------------------------
174 //-----------------------------------------------------------------------------
175 // Data and instruction cache macros map onto the both-cache macros
177 //-----------------------------------------------------------------------------
178 // Global control of data cache
180 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
181 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
182 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
183 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
185 // Enable the data cache
186 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
188 // Disable the data cache
189 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
191 // Invalidate the entire cache
192 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
194 // Synchronize the contents of the cache with memory.
195 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
197 // Query the state of the data cache
198 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
200 // Set the data cache refill burst size
201 //#define HAL_DCACHE_BURST_SIZE(_size_)
203 // Set the data cache write mode
204 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
206 //#define HAL_DCACHE_WRITETHRU_MODE 0
207 //#define HAL_DCACHE_WRITEBACK_MODE 1
209 // Load the contents of the given address range into the data cache
210 // and then lock the cache so that it stays there.
211 //#define HAL_DCACHE_LOCK(_base_, _size_)
213 // Undo a previous lock operation
214 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
216 // Unlock entire cache
217 //#define HAL_DCACHE_UNLOCK_ALL()
219 //-----------------------------------------------------------------------------
220 // Data cache line control
222 // Allocate cache lines for the given address range without reading its
223 // contents from memory.
224 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
226 // Write dirty cache lines to memory and invalidate the cache entries
227 // for the given address range.
228 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
230 // Invalidate cache lines in the given range without writing to memory.
231 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
233 // Write dirty cache lines to memory for the given address range.
234 //#define HAL_DCACHE_STORE( _base_ , _size_ )
236 // Preread the given range into the cache with the intention of reading
238 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
240 // Preread the given range into the cache with the intention of writing
242 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
244 // Allocate and zero the cache lines associated with the given range.
245 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
247 //-----------------------------------------------------------------------------
248 // Global control of Instruction cache
250 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
251 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
252 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
253 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
255 // Enable the instruction cache
256 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
258 // Disable the instruction cache
259 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
261 // Invalidate the entire cache
262 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
265 // Synchronize the contents of the cache with memory.
266 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
268 // Query the state of the instruction cache
269 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
271 // Set the instruction cache refill burst size
272 //#define HAL_ICACHE_BURST_SIZE(_size_)
274 // Load the contents of the given address range into the instruction cache
275 // and then lock the cache so that it stays there.
277 //#define HAL_ICACHE_LOCK(_base_, _size_)
279 // Undo a previous lock operation
280 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
282 // Unlock entire cache
283 //#define HAL_ICACHE_UNLOCK_ALL()
285 //-----------------------------------------------------------------------------
286 // Instruction cache line control
288 // Invalidate cache lines in the given range without writing to memory.
289 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
291 #endif // ifndef CYGONCE_HAL_CACHE_H
292 // End of hal_cache.h